Hitachi S10Mini SV.Link, Hardware Manual, Page: 9 / 75

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4.8.2 Communication delay time setup ·············································································· 38
4.9 Ladder Program Example································································································ 39
4.10 Relationship to CPU Module ·························································································· 41
4.11 Communication
Cycle ····································································································· 42
4.12 Limitations······················································································································· 43
5. OPERATION ························································································································ 45
5.1 Start-up
Procedure ··········································································································· 46
6. MAINTENANCE ················································································································· 49
6.1 Maintenance
Inspection··································································································· 50
6.2 Troubleshooting··············································································································· 51
6.2.1 Procedure··················································································································· 51
6.2.2 Before suspecting a failure ························································································ 52
6.3 Errors and Actions To Be Taken ····················································································· 54
6.3.1 CPU LED display messages······················································································ 54
6.3.2 Hardware
errors········································································································· 55
6.3.3 Communication error codes ······················································································ 58
7. APPENDIX ··························································································································· 61
7.1 SV.LINK State Transitions······························································································ 62
7.2 CPU Memory Map ·········································································································· 63
7.3 Memory Map of SV.LINK Module················································································· 64
7.4 Trouble Investigation Sheet····························································································· 65