D8UF
34
BLOCK DIAGRAMS
P50A402 and P50A202 page 2/2
Power System block diagram for the whole TV set.
PDP Panel Module
Digital
Audio Amp.
Sub
MICRO
Main PWB
+10V
DC-DC
+9V
Reg.
LPF
+3.3V
Reg.
+3.3V
Reg.
Audio ADC
SD
MMC
+3.3V
Reg.
+1.0V
DC-DC
+1.8V
Reg.
Demodulator
+3.3V
Reg.
Vari.
Reg.
FAN
Sync.
Sep.
+3.3V
Reg.
+1.3V
Reg.
Cable
Equalizer
Key
ROM
+5V
Reg.
DDC5V
SW
Audio
DSP
Flash
Memory
(OneNand)
AC120V
+5.6V
STBY+5.6V
Audio+17V
Vcc
Va
Vs
Power Supply Unit
+17V
+2.5V
Reg.
+1.3V
Reg.
+3.3V
Reg.
Seine2-A’
VCXO
PLL
+2.5V
Reg.
+3.3V
DC-DC
+1.3V
DC-DC
Seine2-D
+1.8V
DC-DC
Seine2-D
DDR2
Buffer
OPT
Output
I2C
Level
shift
A/V
SW
+5V
Reg.
Control PWB
Power SW
LED PWB
IR-receiver
(38kHz)
LED
(Blue/Orange)
LED
(Red)
Light
Sensor
VT
+5V
Reg.
Digital/Analog Tuner
+5V
Reg.
Summary of Contents for P50A202/D8UF
Page 63: ...D8UF TABLE OF CONTENTS Schematic Diagram page 20 63 1 MAIN BOARD SHEET 001 Slow Bus Flash ...
Page 67: ...D8UF TABLE OF CONTENTS Schematic Diagram page 20 67 MAIN BOARD SHEET 006 Seine2A Video in 5 ...
Page 71: ...D8UF TABLE OF CONTENTS Schematic Diagram page 20 71 MAIN BOARD SHEET 010 VCXO PLL 9 sheet 11 ...
Page 77: ...D8UF TABLE OF CONTENTS Schematic Diagram page 20 77 16 16 MAIN BOARD SHEET 017 Terminal 15 ...
Page 92: ...PA NO 0235 MADE IN MEXICO ...