Hitachi HD6433822 Hardware Manual Download Page 93

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Figure 3-5 Interrupt Sequence

Vector fetch

Internal

address bus

Internal read

signal

Internal write

signal

(2)

Internal data bus

(16 bits)

Interrupt

request signal

(9)

(1)

Internal

processing

Prefetch instruction of

interrupt-handling routine

(1) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.)

(2)(4) Instruction code (not executed)

(3) Instruction prefetch address (Instruction is not executed.)

(5) SP – 2

(6) SP – 4

(7) CCR

(8) Vector address

(9) Starting address of interrupt-handling routine (contents of vector)

(10) First instruction of interrupt-handling routine

(3)

(9)

(8)

(6)

(5)

(4)

(1)

(7)

(10)

Stack access

Internal

processing

Instruction

prefetch

Interrupt level

decision and wait for

end of instruction

Interrupt is

accepted

Summary of Contents for HD6433822

Page 1: ...6 H8 3865 HD6433865 H8 3864 HD6433864 H8 3863 HD6433863 H8 3862 HD6433862 H8 3827 Series H8 3827 HD6473827 HD6433827 H8 3826 HD6433826 H8 3825 HD6433825 H8 3824 HD6433824 H8 3823 HD6433823 H8 3822 HD6433822 Hardware Manual ADE 602 142B Rev 3 2 1 99 Hitachi Ltd ...

Page 2: ... injury such as aerospace aeronautics nuclear power combustion control transportation traffic safety equipment or medical equipment for life support 4 Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating operating supply voltage range heat radiation characteristics installation conditions and other characteristics Hitachi bears...

Page 3: ...k 92 Figure 4 9 Pin Connection when not Modification Using Subclock 95 Table 5 1 Operating Modes Modification of subsleep mode watch mode descriptions 97 Table 5 2 Internal State in Each Modification of Note 4 Operating Mode 99 5 1 1 System Control Registers Addition of Notes to Bits 6 to 4 1 System control register 1 SYSCR1 100 2 System control register 2 SYSCR2 Modification of Bit 4 contents 102...

Page 4: ...dition of 9 and 10 357 14 2 When Using the Internal Power Modification of description Supply Step Down Circuit 360 15 2 1 Power Supply Voltage Modification of 1 to 3 to 362 and Operating Range 363 Table 15 2 DC Characteristics Addition and modification to 368 369 Table 15 3 Control Signal Timing Addition and modification to 370 371 Table 15 4 Serial Interface SCI3 1 Addition of Notes SCI3 2 Timing...

Page 5: ...ontroller driver six timers a 14 bit PWM a two channel seri al communication interface and an A D converter This allows H8 3867 Series devices to be used as embedded microcomputers in systems requiring LCD display The H8 3867 Series incorporates an LCD drive power supply and step up constant power supply 5 V enabling a fixed 5 V voltage to be obtained independently of VCC This manual describes the...

Page 6: ...mats 19 2 4 Addressing Modes 20 2 4 1 Addressing Modes 20 2 4 2 Effective Address Calculation 22 2 5 Instruction Set 26 2 5 1 Data Transfer Instructions 28 2 5 2 Arithmetic Operations 30 2 5 3 Logic Operations 31 2 5 4 Shift Operations 31 2 5 5 Bit Manipulations 33 2 5 6 Branching Instructions 37 2 5 7 System Control Instructions 39 2 5 8 Block Data Transfer Instruction 40 2 6 Basic Operational Ti...

Page 7: ...1 Notes on Stack Area Use 84 3 4 2 Notes on Rewriting Port Mode Registers 85 Section 4 Clock Pulse Generators 87 4 1 Overview 87 4 1 1 Block Diagram 87 4 1 2 System Clock and Subclock 87 4 2 System Clock Generator 88 4 3 Subclock Generator 91 4 4 Prescalers 93 4 5 Note on Oscillators 94 Section 5 Power Down Modes 95 5 1 Overview 95 5 1 1 System Control Registers 98 5 2 Sleep Mode 102 5 2 1 Transit...

Page 8: ...m Speed Mode 109 5 8 Direct Transfer 110 5 8 1 Overview of Direct Transfer 110 5 8 2 Direct Transition Times 111 5 9 Module Standby Mode 114 5 9 1 Setting Module Standby Mode 114 5 9 2 Clearing Module Standby Mode 114 Section 6 ROM 117 6 1 Overview 117 6 1 1 Block Diagram 117 6 2 H8 3867 and H8 3827 PROM Mode 118 6 2 1 Setting to PROM Mode 118 6 2 2 Socket Adapter Pin Arrangement and Memory Map 11...

Page 9: ... 155 8 5 5 MOS Input Pull Up 155 8 6 Port 6 156 8 6 1 Overview 156 8 6 2 Register Configuration and Description 156 8 6 3 Pin Functions 158 8 6 4 Pin States 158 8 6 5 MOS Input Pull Up 158 8 7 Port 7 159 8 7 1 Overview 159 8 7 2 Register Configuration and Description 159 8 7 3 Pin Functions 161 8 7 4 Pin States 161 8 8 Port 8 162 8 8 1 Overview 162 8 8 2 Register Configuration and Description 162 ...

Page 10: ...Descriptions 195 9 4 3 CPU Interface 203 9 4 4 Operation 206 9 4 5 Application Notes 210 9 5 Timer G 212 9 5 1 Overview 212 9 5 2 Register Descriptions 215 9 5 3 Noise Canceler 220 9 5 4 Operation 222 9 5 5 Application Notes 226 9 5 6 Timer G Application Example 230 9 6 Watchdog Timer 232 9 6 1 Overview 232 9 6 2 Register Descriptions 233 9 6 3 Timer Operation 237 9 6 4 Watchdog Timer Operation St...

Page 11: ...n 271 10 3 1 Overview 271 10 3 2 Operation in Asynchronous Mode 275 10 3 3 Operation in Synchronous Mode 284 10 3 4 Multiprocessor Communication Function 291 10 4 Interrupts 298 10 5 Application Notes 299 Section 11 14 Bit PWM 305 11 1 Overview 305 11 1 1 Features 305 11 1 2 Block Diagram 305 11 1 3 Pin Configuration 306 11 1 4 Register Configuration 306 11 2 Register Descriptions 307 11 2 1 PWM C...

Page 12: ...1 13 2 3 LCD Control Register 2 LCR2 333 13 2 4 Clock Stop Register 2 CKSTPR2 335 13 3 Operation 336 13 3 1 Settings up to LCD Display 336 13 3 2 Relationship between LCD RAM and Display 339 13 3 3 Luminance Adjustment Function V0 Pin 347 13 3 4 Step Up Constant Voltage 5 V Power Supply 348 13 3 5 Low Power Consumption LCD Drive System 348 13 3 6 Operation in Power Down Modes 352 13 3 7 Boosting t...

Page 13: ...389 Appendix B Internal I O Registers 396 B 1 Addresses 396 B 2 Functions 400 Appendix C I O Port Block Diagrams 449 C 1 Block Diagrams of Port 1 449 C 2 Block Diagrams of Port 3 453 C 3 Block Diagrams of Port 4 460 C 4 Block Diagram of Port 5 464 C 5 Block Diagram of Port 6 465 C 6 Block Diagram of Port 7 466 C 7 Block Diagrams of Port 8 467 C 8 Block Diagram of Port A 468 C 9 Block Diagram of Po...

Page 14: ... H8 3825 with 40 kbyte ROM and 2 kbyte RAM the H8 3866 and H8 3826 with 48 kbyte ROM and 2 kbyte RAM and the H8 3867 and H8 3827 with 60 kbyte ROM and 2 kbyte RAM The H8 3867 and H8 3827 are also available in a ZTAT version with on chip PROM which can be programmed as required by the user Table 1 1 summarizes the features of the H8 3867 Series and H8 3827 Series Note ZTAT Zero Turn Around Time is ...

Page 15: ...H8 3862 H8 3822 16 kbyte ROM 1 kbyte RAM H8 3863 H8 3823 24 kbyte ROM 1 kbyte RAM H8 3864 H8 3824 32 kbyte ROM 2 kbyte RAM H8 3865 H8 3825 40 kbyte ROM 2 kbyte RAM H8 3866 H8 3826 48 kbyte ROM 2 kbyte RAM H8 3867 H8 3827 60 kbyte ROM 2 kbyte RAM I O ports 64 pins 55 I O pins 9 input pins Timers Six on chip timers Timer A 8 bit timer Count up timer with selection of eight internal clock signals div...

Page 16: ... interface channels on chip interface SCI3 1 8 bit synchronous asynchronous serial interface Incorporates multiprocessor communication function SCI3 2 8 bit synchronous asynchronous serial interface Incorporates multiprocessor communication function 14 bit PWM Pulse division PWM output for reduced ripple Can be used as a 14 bit D A converter by connecting to an external low pass filter A D convert...

Page 17: ...FP 80A ROM 32 kbytes HD6433824H RAM 2 kbytes HD6433864F 80 pin QFP FP 80B HD6433824F HD6433864W 80 pin TQFP TFP 80C HD6433824W HD6433865H 80 pin QFP FP 80A ROM 40 kbytes HD6433825H RAM 2 kbytes HD6433865F 80 pin QFP FP 80B HD6433825F HD6433865W 80 pin TQFP TFP 80C HD6433825W HD6433866H 80 pin QFP FP 80A ROM 48 kbytes HD6433826H RAM 2 kbytes HD6433866F 80 pin QFP FP 80B HD6433826F HD6433866W 80 pin...

Page 18: ... Port 3 Port 4 Port 5 X 1 X 2 Sub Clock OSC V SS V SS V CC CV CC RES TEST H8 300L CPU LCD Power Supply ROM 60k 48k 40k 32k 24k 16k RAM 2k 1k Timer A Timer C Timer F Timer G Asynchronous counter Serial communication interface 3 1 Serial communication interface 3 2 14 bit PWM WDT LCD Controller A D 10bit V0 V1 V2 V3 PA3 COM4 PA2 COM3 PA1 COM2 PA0 COM1 P87 SEG32 CL1 P86 SEG31 CL2 P85 SEG30 DO P84 SEG...

Page 19: ...6 SEG31CL2 P87 SEG32CL1 P40 SCK32 P41 RXD32 P42 TXD32 P43 IRQ0 AVCC PB0 AN0 PB1 AN1 PB2 AN2 PB3 AN3 PB4 AN4 PB5 AN5 PB6 AN6 PB 7 AN 7 AV SS X 1 X 2 V SS OSC 2 OSC 1 TEST RES P1 0 TMOW P1 1 TMOFL P1 2 TMOFH P1 3 TMIG P1 4 IRQ 4 ADTRG P1 5 IRQ 1 TMIC P1 6 IRQ 2 P1 7 IRQ 3 TMIF P3 0 PWM P3 1 UD P3 2 RESO P53 WKP3 SEG4 P52 WKP2 SEG3 P51 WKP1 SEG2 P50 WKP0 SEG1 PA0 COM1 PA1 COM2 PA2 COM3 PA3 COM4 VCC V...

Page 20: ...2 P6 2 SEG11 P6 1 SEG10 P6 0 SEG9 P5 7 WKP 7 SEG8 P5 6 WKP 6 SEG7 P5 5 WKP 5 SEG6 P5 4 WKP 4 SEG5 P5 3 WKP 3 SEG4 P5 2 WKP 2 SEG3 P82 SEG27 P83 SEG28 P84 SEG29 M P85 SEG30 DO P86 SEG31 CL2 P87 SEG32 CL1 P40 SCK32 P41 RXD32 P42 TXD32 P43 IRQ0 AVCC PB0 AN0 PB1 AN1 PB2 AN2 PB3 AN3 PB4 AN4 P51 WKP1 SEG2 P50 WKP0 SEG1 PA0 COM1 PA1 COM2 PA2 COM3 PA3 COM4 VCC V0 V1 V2 V3 VSS CVCC P37 AEVL P36 AEVH P35 TX...

Page 21: ... D converter ground pin It should be connected to the system power supply 0V V0 31 33 Output LCD power supply These are the power supply pins for the LCD controller V1 30 32 Input driver They incorporate a power supply V2 29 31 split resistance and are normally used V3 28 30 with V0 and V1 shorted Clock pins OSC1 7 9 Input These pins connect to a crystal or ceramic oscillator or can be OSC2 6 8 Ou...

Page 22: ...utput circuit AEVL 25 27 Input Asynchronous event counter event AEVH 24 26 input This is an event input pin for input to the asynchronous event counter TMIC 15 17 Input Timer C event input This is an event input pin for input to the timer C counter UD 19 21 Input Timer C up down select This pin selects up or down counting for the timer C counter The counter operates as an up counter when this pin ...

Page 23: ...O Port 1 This is an 8 bit I O port Input or P10 output can be designated for each bit by means of port control register 1 PCR1 P37 to 25 to 18 27 to 20 I O Port 3 This is an 8 bit I O port Input or P30 output can be designated for each bit by means of port control register 3 PCR3 P57 to 44 to 37 46 to 39 I O Port 5 This is an 8 bit I O port Input or P50 output can be designated for each bit by mea...

Page 24: ...o 74 80 to 76 These are analog data input channels to the A D converter ADTRG 14 16 Input A D converter trigger input This is the external trigger input pin to the A D converter LCD COM4 to 33 to 36 35 to 38 Output LCD common output These are the controller COM1 LCD common output pins driver SEG32 to 68 to 37 70 to 39 Output LCD segment output These are the SEG1 LCD segment output pins CL1 68 70 O...

Page 25: ...structions Powerful bit manipulation instructions Eight addressing modes Register direct Register indirect Register indirect with displacement Register indirect with post increment or pre decrement Absolute address Immediate Program counter relative Memory indirect 64 kbyte address space High speed operation All frequently used instructions are executed in two to four states High speed arithmetic ...

Page 26: ...8 300L CPU There are two groups of registers the general registers and control registers Figure 2 1 CPU Registers 7 0 7 0 15 0 PC R0H R1H R2H R3H R4H R5H R6H R7H R0L R1L R2L R3L R4L R5L R6L R7L SP SP Stack pointer PC Program counter CCR Condition code register Carry flag Overflow flag Zero flag Negative flag Half carry flag Interrupt mask bit User bit User bit CCR I U H U N Z V C General registers...

Page 27: ...SP used implicitly by hardware in exception processing and subroutine calls When it functions as the stack pointer as indicated in figure 2 2 SP R7 points to the top of the stack Figure 2 2 Stack Pointer 2 2 2 Control Registers The CPU control registers include a 16 bit program counter PC and an 8 bit condition code register CCR Program Counter PC This 16 bit register indicates the address of the ...

Page 28: ...to 0 otherwise The H flag is used implicitly by the DAA and DAS instructions When the ADD W SUB W or CMP W instruction is executed the H flag is set to 1 if there is a carry or borrow at bit 11 and is cleared to 0 otherwise Bit 4 User Bit U Can be used freely by the user Bit 3 Negative Flag N Indicates the most significant bit sign bit of the result of an instruction Bit 2 Zero Flag Z Set to 1 to ...

Page 29: ...ecuted after a reset 2 3 Data Formats The H8 300L CPU can process 1 bit data 4 bit BCD data 8 bit byte data and 16 bit word data Bit manipulation instructions operate on 1 bit data specified as bit n in a byte operand n 0 1 2 7 All arithmetic and logic instructions except ADDS and SUBS can operate on byte data The MOV W ADD W SUB W CMP W ADDS SUBS MULXU 8 bits 8 bits and DIVXU 16 bits 8 bits instr...

Page 30: ...7 0 1 bit data RnH 7 6 5 4 3 2 1 0 don t care 7 0 1 bit data RnL MSB LSB don t care 7 0 Byte data RnH Byte data RnL Word data Rn 4 bit BCD data RnH 4 bit BCD data RnL Notation RnH RnL MSB LSB Upper byte of general register Lower byte of general register Most significant bit Least significant bit MSB LSB don t care 7 0 MSB LSB 15 0 Upper digit Lower digit don t care 7 0 3 4 don t care Upper digit L...

Page 31: ... 2 4 Memory Data Formats When the stack is accessed using R7 as an address register word access should always be performed When the CCR is pushed on the stack two identical copies of the CCR are pushed to make a complete word When they are restored the lower byte is ignored Data Format 7 6 5 4 3 2 1 0 Address Data Type 7 0 Address n MSB LSB MSB LSB Upper 8 bits Lower 8 bits MSB LSB CCR CCR MSB LSB...

Page 32: ...gister Direct Rn The register field of the instruction specifies an 8 or 16 bit general register containing the operand Only the MOV W ADD W SUB W CMP W ADDS SUBS MULXU 8 bits 8 bits and DIVXU 16 bits 8 bits instructions have 16 bit operands 2 Register Indirect Rn The register field of the instruction specifies a 16 bit general register containing the address of the operand in memory 3 Register In...

Page 33: ...e operand in memory The absolute address may be 8 bits long aa 8 or 16 bits long aa 16 The MOV B and bit manipulation instructions can use 8 bit absolute addresses The MOV B MOV W JMP and JSR instructions can use 16 bit absolute addresses For an 8 bit absolute address the upper 8 bits are assumed to be 1 H FF The address range is H FF00 to H FFFF 65280 to 65535 6 Immediate xx 8 or xx 16 The instru...

Page 34: ...egarded as 0 causing word access to be performed at the address preceding the specified address See 2 3 2 Memory Data Formats for further information 2 4 2 Effective Address Calculation Table 2 2 shows how effective addresses are calculated in each of the addressing modes Arithmetic and logic instructions use register direct addressing 1 The ADD B ADDX SUBX CMP B AND OR and XOR instructions can al...

Page 35: ...15 Register indirect with displacement d 16 Rn op rm rn 8 7 3 4 0 15 op rm 7 6 3 4 0 15 disp op rm 7 6 3 4 0 15 Register indirect with post increment Rn op rm 7 6 3 4 0 15 Register indirect with pre decrement Rn 2 3 4 Incremented or decremented by 1 if operand is byte size and by 2 if word size 0 15 disp 0 15 0 15 0 15 1 or 2 0 15 0 15 1 or 2 0 15 rm 3 0 rn 3 0 Contents 16 bits of register indicat...

Page 36: ...ss Calculation Method Effective Address EA 5 Absolute address aa 8 Operand is 1 or 2 byte immediate data aa 16 op 8 7 0 15 op 0 15 IMM op disp 7 0 15 Program counter relative d 8 PC 6 7 0 15 PC contents 0 15 0 15 abs H FF 8 7 0 15 0 15 abs op xx 16 op 8 7 0 15 IMM Immediate xx 8 8 Sign extension disp 24 ...

Page 37: ...ruction Format No Effective Address Calculation Method Effective Address EA 8 Memory indirect aa 8 op 8 7 0 15 Memory contents 16 bits 0 15 abs H 00 8 7 0 15 Notation rm rn op disp IMM abs Register field Operation field Displacement Immediate data Absolute address abs 25 ...

Page 38: ... manipulation BSET BCLR BNOT BTST BAND BIAND BOR 14 BIOR BXOR BIXOR BLD BILD BST BIST Branch Bcc 2 JMP BSR JSR RTS 5 System control RTE SLEEP LDC STC ANDC ORC XORC NOP 8 Block data transfer EEPMOV 1 Total 55 Notes 1 PUSH Rn is equivalent to MOV W Rn SP POP Rn is equivalent to MOV W SP Rn The same applies to the machine language 2 Bcc is a conditional branch instruction in which cc represents a con...

Page 39: ...lag of CCR Z Z zero flag of CCR V V overflow flag of CCR C C carry flag of CCR PC Program counter SP Stack pointer IMM Immediate data disp Displacement Addition Subtraction Multiplication Division AND logical OR logical Exclusive OR logical Move Logical negation logical complement 3 3 bit length 8 8 bit length 16 16 bit length Contents of operand indicated by effective address 27 ...

Page 40: ...ster The Rn Rn d 16 Rn aa 16 xx 16 Rn and Rn addressing modes are available for word data The aa 8 addressing mode is available for byte data only The R7 and R7 modes require word operands Do not specify byte size for these two modes POP W SP Rn Pops a 16 bit general register from the stack Equivalent to MOV W SP Rn PUSH W Rn SP Pushes a 16 bit general register onto the stack Equivalent to MOV W R...

Page 41: ... d 16 Rm Rn disp 15 0 8 7 op rm rn Rm Rn or Rn Rm 15 0 8 7 op rn abs aa 8 Rn 15 0 8 7 op rn aa 16 Rn abs 15 0 8 7 op rn IMM xx 8 Rn 15 0 8 7 op rn xx 16 Rn IMM 15 0 8 7 op rn PUSH POP Notation op rm rn disp abs IMM Operation field Register field Displacement Absolute address Immediate data SP Rn or Rn SP 1 1 1 29 ...

Page 42: ...or decrements a general register by 1 ADDS W Rd 1 Rd Rd 2 Rd SUBS Adds or subtracts 1 or 2 to or from a general register DAA B Rd decimal adjust Rd DAS Decimal adjusts adjusts to 4 bit BCD an addition or subtraction result in a general register by referring to the CCR MULXU B Rd Rs Rd Performs 8 bit 8 bit unsigned multiplication on data in two general registers providing a 16 bit result DIVXU B Rd...

Page 43: ...a general register and another general register or immediate data NOT B Rd Rd Obtains the one s complement logical complement of general register contents Notes Size Operand size B Byte 2 5 4 Shift Operations Table 2 7 describes the eight shift instructions Table 2 7 Shift Instructions Instruction Size Function SHAL B Rd shift Rd SHAR Performs an arithmetic shift operation on general register cont...

Page 44: ... 7 op rm rn ADD SUB CMP ADDX SUBX Rm Notation op rm rn IMM Operation field Register field Immediate data 15 0 8 7 op rn ADDS SUBS INC DEC DAA DAS NEG NOT 15 0 8 7 op rn MULXU DIVXU rm 15 0 8 7 rn IMM ADD ADDX SUBX CMP XX 8 op 15 0 8 7 op rn AND OR XOR Rm rm 15 0 8 7 rn IMM AND OR XOR xx 8 op 15 0 8 7 rn SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR op 32 ...

Page 45: ... general register BTST B bit No of EAd Z Tests a specified bit in a general register or memory and sets or clears the Z flag accordingly The bit number is specified by 3 bit immediate data or the lower three bits of a general register BAND B C bit No of EAd C ANDs the C flag with a specified bit in a general register or memory and stores the result in the C flag BIAND B C bit No of EAd C ANDs the ...

Page 46: ...Ad C Copies a specified bit in a general register or memory to the C flag BILD B bit No of EAd C Copies the inverse of a specified bit in a general register or memory to the C flag The bit number is specified by 3 bit immediate data BST B C bit No of EAd Copies the C flag to a specified bit in a general register or memory BIST B C bit No of EAd Copies the inverse of the C flag to a specified bit i...

Page 47: ...Rn immediate xx 3 rn 0 0 0 0 0 0 0 IMM 15 0 8 7 op 0 Operand Bit No register indirect Rn register direct Rm rn 0 0 0 0 0 0 0 rm op 15 0 8 7 op Operand Bit No absolute aa 8 immediate xx 3 abs 0 0 0 0 IMM op op 15 0 8 7 op Operand Bit No absolute aa 8 register direct Rm abs 0 0 0 0 rm op 15 0 8 7 op IMM rn Operand Bit No register direct Rn immediate xx 3 BAND BOR BXOR BLD BST 15 0 8 7 op 0 Operand B...

Page 48: ...r field Absolute address Immediate data 15 0 8 7 op IMM rn Operand Bit No register direct Rn immediate xx 3 BIAND BIOR BIXOR BILD BIST 15 0 8 7 op 0 Operand Bit No register indirect Rn immediate xx 3 rn 0 0 0 0 0 0 0 IMM op 15 0 8 7 op Operand Bit No absolute aa 8 immediate xx 3 abs 0 0 0 0 IMM op 36 ...

Page 49: ... true Always BRN BF Never false Never BHI High C Z 0 BLS Low or same C Z 1 BCC BHS Carry clear high or same C 0 BCS BLO Carry set low C 1 BNE Not equal Z 0 BEQ Equal Z 1 BVC Overflow clear V 0 BVS Overflow set V 1 BPL Plus N 0 BMI Minus N 1 BGE Greater or equal N V 0 BLT Less than N V 1 BGT Greater than Z N V 0 BLE Less or equal Z N V 1 JMP Branches unconditionally to a specified address BSR Branc...

Page 50: ...ondition field Register field Displacement Absolute address 15 0 8 7 op cc disp Bcc 15 0 8 7 op rm 0 JMP Rm 0 0 0 15 0 8 7 op JMP aa 16 abs 15 0 8 7 op abs JMP aa 8 15 0 8 7 op disp BSR 15 0 8 7 op rm 0 JSR Rm 0 0 0 15 0 8 7 op JSR aa 16 abs 15 0 8 7 op abs JSR aa 8 15 0 8 7 op RTS 38 ...

Page 51: ...odes for details LDC B Rs CCR IMM CCR Moves immediate data or general register contents to the condition code register STC B CCR Rd Copies the condition code register to a specified general register ANDC B CCR IMM CCR Logically ANDs the condition code register with immediate data ORC B CCR IMM CCR Logically ORs the condition code register with immediate data XORC B CCR IMM CCR Logically exclusive ...

Page 52: ...ck transfer instruction Transfers the number of data bytes specified by R4L from locations starting at the address indicated by R5 to locations starting at the address indicated by R6 After the transfer the next instruction is executed Certain precautions are required in using the EEPMOV instruction See 2 9 3 Notes on Use of the EEPMOV Instruction for details Notation op rn IMM Operation field Reg...

Page 53: ...Figure 2 10 Block Data Transfer Instruction Code Notation op Operation field 15 0 8 7 op op 41 ...

Page 54: ...s depending on whether access is to on chip memory or to on chip peripheral modules 2 6 1 Access to On Chip Memory RAM ROM Access to on chip memory takes place in two states The data bus width is 16 bits allowing access in byte or word size Figure 2 11 shows the on chip memory access cycle Figure 2 11 On Chip Memory Access Cycle T1 state Bus cycle T2 state Internal address bus Internal read signal...

Page 55: ...ta two instructions must be used Figures 2 12 and 2 13 show the on chip peripheral module access cycle Two state access to on chip peripheral modules Figure 2 12 On Chip Peripheral Module Access Cycle 2 State Access T1 state Bus cycle T2 state ø or ø Internal address bus Internal read signal Internal data bus read access Internal write signal Read data Address Write data Internal data bus write ac...

Page 56: ...3 On Chip Peripheral Module Access Cycle 3 State Access T1 state Bus cycle Internal address bus Internal read signal Internal data bus read access Internal write signal Read data Address Internal data bus write access T2 state T3 state Write data SUB ø or ø 44 ...

Page 57: ...dling state Active high speed mode Active medium speed mode Subactive mode Sleep high speed mode Standby mode Watch mode Subsleep mode Low power modes The CPU executes successive program instructions at high speed synchronized by the system clock The CPU executes successive program instructions at reduced speed synchronized by the system clock The CPU executes successive program instructions at re...

Page 58: ...eed and medium speed standby mode watch mode and subsleep mode See section 5 Power Down Modes for details on these modes 2 7 4 Exception Handling State The exception handling state is a transient state occurring when exception handling is started by a reset or interrupt and the CPU changes its normal processing flow In exception handling caused by an interrupt SP R7 is referenced and the PC and CC...

Page 59: ...H8 3865 and H8 3825 in figure 2 16 4 that of the H8 3866 and H8 3826 in figure 2 16 5 and that of the H8 3867 and H8 3827 in figure 2 16 6 Figure 2 16 1 H8 3862 and H8 3822 Memory Map H 0000 H 0029 H 002A H 3FFF H F740 H F75F H F780 H FB7F H FF90 H FFFF Interrupt vector area On chip ROM 16 kbytes 16384 bytes 1024 bytes On chip RAM Internal I O registers 112 bytes Not used Not used Not used LCD RAM...

Page 60: ...mory Map H 0000 H 0029 H 002A H 5FFF H F740 H F75F H F780 H FB7F H FF90 H FFFF Interrupt vector area On chip ROM 24 kbytes 24576 bytes 1024 bytes On chip RAM Internal I O registers 112 bytes Not used Not used Not used LCD RAM 32 bytes 48 ...

Page 61: ...mory Map H 0000 H 0029 H 002A H 7FFF H F740 H F75F H F780 H FF7F H FF90 H FFFF Interrupt vector area On chip ROM 32 kbytes 32768 bytes 2048 bytes On chip RAM Internal I O registers 112 bytes Not used Not used Not used LCD RAM 32 bytes 49 ...

Page 62: ...mory Map H 0000 H 0029 H 002A H 9FFF H F740 H F75F H F780 H FF7F H FF90 H FFFF Interrupt vector area On chip ROM 40 kbytes 40960 bytes 2048 bytes On chip RAM Internal I O registers 112 bytes Not used Not used Not used LCD RAM 32 bytes 50 ...

Page 63: ...mory Map H 0000 H 0029 H 002A H BFFF H F740 H F75F H F780 H FF7F H FF90 H FFFF Interrupt vector area On chip ROM 48 kbytes 49152 bytes 2048 bytes On chip RAM Not used Internal I O registers 112 bytes Not used Not used LCD RAM 32 bytes 51 ...

Page 64: ...mory Map H 0000 H 0029 H 002A H EDFF H F740 H F75F H F780 H FF7F H FF90 H FFFF Interrupt vector area On chip ROM 60 kbytes 60928 bytes 2048 bytes On chip RAM Internal I O registers 112 bytes Not used Not used Not used LCD RAM 32 bytes 52 ...

Page 65: ...Internal data transfer to or from on chip modules other than the ROM and RAM areas makes use of an 8 bit data width If word access is attempted to these areas the following results will occur Word access from CPU to I O register area Upper byte Will be written to I O register Lower byte Transferred data will be lost Word access from I O register to CPU Upper byte Will be written to upper part of C...

Page 66: ... H 7FFF H F740 H F75F H F780 H FF7F 2 H FF90 H FFFF Notes 1 2 1 The example of the H8 3864 and H8 3824 is shown here This address is H 3FFF in the H8 3862 and H8 3822 16 kbyte on chip ROM H 5FFF in the H8 3863 and H8 3823 24 kbyte on chip ROM H 9FFF in the H8 3865 and H8 3825 40 kbyte on chip ROM H BFFF in the H8 3866 and H8 3826 48 kbyte on chip ROM and H EDFF in the H8 3867 and H8 3827 60 kbyte ...

Page 67: ...er counter Figure 2 18 shows an example in which two timer registers share the same address When a bit manipulation instruction accesses the timer load register and timer counter of a reloadable timer since these two registers share the same address the following operations take place Order of Operation Operation 1 Read Timer counter data is read one byte 2 Modify The CPU modifies sets or resets t...

Page 68: ... The BSET instruction is executed designating port 3 C After executing BSET P37 P36 P35 P34 P33 P32 P31 P30 Input output Input Input Output Output Output Output Output Output Pin state Low High Low Low Low Low Low High level level level level level level level level PCR3 0 0 1 1 1 1 1 1 PDR3 0 1 0 0 0 0 0 1 D Explanation of how BSET operates When the BSET instruction is executed first the CPU read...

Page 69: ...t Output Output Output Output Pin state Low High Low Low Low Low Low Low level level level level level level level level PCR3 0 0 1 1 1 1 1 1 PDR3 1 0 0 0 0 0 0 0 RAM0 1 0 0 0 0 0 0 0 B BSET instruction executed The BSET instruction is executed designating the PDR3 work area RAM0 C After executing BSET The work area RAM0 value is written to PDR3 P37 P36 P35 P34 P33 P32 P31 P30 Input output Input I...

Page 70: ...ecuted designating PCR3 C After executing BCLR P37 P36 P35 P34 P33 P32 P31 P30 Input output Output Output Output Output Output Output Output Input Pin state Low High Low Low Low Low Low High level level level level level level level level PCR3 1 1 1 1 1 1 1 0 PDR3 1 0 0 0 0 0 0 0 D Explanation of how BCLR operates When the BCLR instruction is executed first the CPU reads PCR3 Since PCR3 is a write...

Page 71: ... 0 0 0 RAM0 0 0 1 1 1 1 1 1 B BCLR instruction executed The BCLR instruction is executed designating the PCR3 work area RAM0 C After executing BCLR The work area RAM0 value is written to PCR3 P37 P36 P35 P34 P33 P32 P31 P30 Input output Input Input Output Output Output Output Output Output Pin state Low High Low Low Low Low Low High level level level level level level level level PCR3 0 0 1 1 1 1 ...

Page 72: ...r 7 PDR7 H FFDA Port data register 8 PDR8 H FFDB Port data register A PDRA H FFDD Note Port data registers have the same addresses as input pins Table 2 13 Registers with Write Only Bits Register Name Abbreviation Address Port control register 1 PCR1 H FFE4 Port control register 3 PCR3 H FFE6 Port control register 4 PCR4 H FFE7 Port control register 5 PCR5 H FFE8 Port control register 6 PCR6 H FFE...

Page 73: ...ytes specified by R4L from the address specified by R5 to the address specified by R6 When setting R4L and R6 make sure that the final destination address R6 R4L does not exceed H FFFF The value in R6 must not change from H FFFF to H 0000 during execution of the instruction H FFFF Not allowed R6 R6 R4L R5 R5 R4L R6 R6 R4L R5 R5 R4L ...

Page 74: ...eption The internal state of the CPU and the registers of the on chip peripheral modules are initialized 3 2 2 Reset Sequence As soon as the RES pin goes low all processing is stopped and the chip enters the reset state To make sure the chip is reset properly observe the following precautions At power on Hold the RES pin low until the clock pulse generator output stabilizes Resetting during operat...

Page 75: ...input Figure 3 1 Reset Sequence Vector fetch ø Internal address bus Internal read signal Internal write signal Internal data bus 16 bit RES Internal processing Program initial instruction prefetch 1 Reset exception handling vector address H 0000 2 Program start address 3 First instruction of program 2 3 2 1 Reset cleared 64 ...

Page 76: ... W xx 16 SP 3 3 Interrupts 3 3 1 Overview The interrupt sources include 13 external interrupts IRQ4 to IRQ0 WKP7 to WKP0 and 23 internal interrupts from on chip peripheral modules Table 3 2 shows the interrupt sources their priorities and their vector addresses When more than one interrupt is requested the interrupt with the highest priority is processed The interrupts have the following features ...

Page 77: ...H 001B underflow Timer FL Timer FL compare match 14 H 001C to H 001D Timer FL overflow Timer FH Timer FH compare match 15 H 001E to H 001F Timer FH overflow Timer G Timer G input capture 16 H 0020 to H 0021 Timer G overflow SCI3 1 SCI3 1 transmit end 17 H 0022 to H 0023 SCI3 1 transmit data empty SCI3 1 receive data full SCI3 1 overrrun error SCI3 1 framing error SCI3 1 parity error SCI3 2 SCI3 2 ...

Page 78: ...ter WEGR R W H 00 H FF90 Note Write is enabled only for writing of 0 to clear a flag 1 IRQ edge select register IEGR IEGR is an 8 bit read write register used to designate whether pins IRQ4 to IRQ0 are set to rising edge sensing or falling edge sensing Bits 7 to 5 Reserved bits Bits 7 to 5 are reserved they are always read as 1 and cannot be modified Bit 4 IRQ4 edge select IEG4 Bit 4 selects the i...

Page 79: ...alling edge of IRQ2 pin input is detected initial value 1 Rising edge of IRQ2 pin input is detected Bit 1 IRQ1 edge select IEG1 Bit 3 selects the input sensing of the IRQ1 pin and TMIC pin Bit 1 IEG1 Description 0 Falling edge of IRQ1 and TMIC pin input is detected initial value 1 Rising edge of IRQ1 and TMIC pin input is detected Bit 0 IRQ0 edge select IEG0 Bit 0 selects the input sensing of pin ...

Page 80: ... 0 by a reset Bit 5 Wakeup interrupt enable IENWP Bit 5 enables or disables WKP7 to WKP0 interrupt requests Bit 5 IENWP Description 0 Disables WKP7 to WKP0 interrupt requests initial value 1 Enables WKP7 to WKP0 interrupt requests Bits 4 to 0 IRQ4 to IRQ0 interrupt enable IEN4 to IEN0 Bits 4 to 0 enable or disable IRQ4 to IRQ0 interrupt requests Bit n IENn Description 0 Disables interrupt requests...

Page 81: ... A D converter interrupt requests Bit 6 IENAD Description 0 Disables A D converter interrupt requests initial value 1 Enables A D converter interrupt requests Bit 5 Reserved bit Bit 5 is a readable writable reserved bit It is initialized to 0 by a reset Bit 4 Timer G interrupt enable IENTG Bit 4 enables or disables timer G input capture or overflow interrupt requests Bit 4 IENTG Description 0 Disa...

Page 82: ...bles timer FL interrupt requests Bit 1 Timer C interrupt enable IENTC Bit 1 enables or disables timer C overflow and underflow interrupt requests Bit 1 IENTC Description 0 Disables timer C interrupt requests initial value 1 Enables timer C interrupt requests Bit 0 Asynchronous event counter interrupt enable IENEC Bit 0 enables or disables asynchronous event counter interrupt requests Bit 0 IENEC D...

Page 83: ... value overflows from H FF to H 00 Bit 6 Reserved bit Bit 6 is a readable writable reserved bit It is initialized to 0 by a reset Bit 5 Reserved bit Bit 5 is reserved it is always read as 1 and cannot be modified Bits 4 to 0 IRQ4 to IRQ0 interrupt request flags IRRI4 to IRRI0 Bit n IRRIn Description 0 Clearing conditions initial value When IRRIn 1 it is cleared by writing 0 1 Setting conditions Wh...

Page 84: ... is cleared by writing 0 1 Setting conditions When a direct transfer is made by executing a SLEEP instruction while DTON 1 in SYSCR2 Bit 6 A D converter interrupt request flag IRRAD Bit 6 IRRAD Description 0 Clearing conditions initial value When IRRAD 1 it is cleared by writing 0 1 Setting conditions When A D conversion is completed and ADSF is cleared to 0 in ADSR Bit 5 Reserved bit Bit 5 is a r...

Page 85: ... cleared by writing 0 1 Setting conditions When TCFH and OCRFH match in 8 bit timer mode or when TCF TCFL TCFH and OCRF OCRFL OCRFH match in 16 bit timer mode Bit 2 Timer FL interrupt request flag IRRTFL Bit 2 IRRTFL Description 0 Clearing conditions initial value When IRRTFL 1 it is cleared by writing 0 1 Setting conditions When TCFL and OCRFL match in 8 bit timer mode Bit 1 Timer C interrupt req...

Page 86: ...r falling edge is input at that pin the corresponding flag in IWPR is set to 1 A flag is not cleared automatically when the corresponding interrupt is accepted Flags must be cleared by writing 0 Bits 7 to 0 Wakeup interrupt request flags IWPF7 to IWPF0 Bit n IWPFn Description 0 Clearing conditions initial value When IWPFn 1 it is cleared by writing 0 1 Setting conditions When pin WKPn is designate...

Page 87: ...en these pins are designated as pins WKP7 to WKP0 in port mode register 5 and a rising or falling edge is input the corresponding bit in IWPR is set to 1 requesting an interrupt Recognition of wakeup interrupt requests can be disabled by clearing the IENWP bit to 0 in IENR1 These interrupts can all be masked by setting the I bit to 1 in CCR When WKP7 to WKP0 interrupt exception handling is initiat...

Page 88: ...nterrupt exception handling is initiated the I bit is set to 1 in CCR Vector numbers 8 to 4 are assigned to interrupts IRQ4 to IRQ0 The order of priority is from IRQ0 high to IRQ4 low Table 3 2 gives details 3 3 4 Internal Interrupts There are 23 internal interrupts that can be requested by the on chip peripheral modules When a peripheral module requests an interrupt the corresponding bit in IRR1 ...

Page 89: ...e interrupt controller receives an interrupt request it sets the interrupt request flag From among the interrupts with interrupt request flags set to 1 the interrupt controller selects the interrupt request with the highest priority and holds the others pending Refer to table 3 2 for a list of interrupt priorities The interrupt controller checks the I bit of CCR If the I bit is 0 the selected inte...

Page 90: ...esponding to the accepted interrupt is generated and the interrupt handling routine located at the address indicated by the contents of the vector address is executed Notes 1 When disabling interrupts by clearing bits in an interrupt enable register or when clearing bits in an interrupt request register always do so while interrupts are masked I 1 2 If the above clear operations are performed whil...

Page 91: ...ents saved I 1 I 0 Program execution state No Yes Yes No Notation PC CCR I Program counter Condition code register I bit of CCR IEN0 1 No Yes IENDT 1 No Yes IRRDT 1 No Yes Branch to interrupt handling routine IRRI0 1 No Yes IEN1 1 No Yes IRRI1 1 No Yes IEN2 1 No Yes IRRI2 1 ...

Page 92: ...ion handling After completion of interrupt exception handling Notation PCH PCL CCR SP Upper 8 bits of program counter PC Lower 8 bits of program counter PC Condition code register Stack pointer Notes CCR CCR PCH PCL 1 2 PC shows the address of the first instruction to be executed upon return from the interrupt handling routine Register contents must always be saved and restored by word access star...

Page 93: ...on is not executed Address is saved as PC contents becoming return address 2 4 Instruction code not executed 3 Instruction prefetch address Instruction is not executed 5 SP 2 6 SP 4 7 CCR 8 Vector address 9 Starting address of interrupt handling routine contents of vector 10 First instruction of interrupt handling routine 3 9 8 6 5 4 1 7 10 Stack access Internal processing Instruction prefetch Int...

Page 94: ...ntil the first instruction of the interrupt handler is executed Table 3 4 Interrupt Wait States Item States Total Waiting time for completion of executing instruction 1 to 13 15 to 27 Saving of PC and CCR to stack 4 Vector fetch 2 Instruction fetch 4 Internal processing 4 Note Not including EEPMOV instruction 83 ...

Page 95: ...igure 3 6 Figure 3 6 Operation when Odd Address is Set in SP When CCR contents are saved to the stack during interrupt exception handling or restored when RTE is executed this also takes place in word size Both the upper and lower bytes of word data are saved to the stack on return the even address contents are restored to CCR while the odd address contents are ignored PC PC R1L PC SP SP SP H FEFC...

Page 96: ...it IEG3 0 When PMR1 bit IRQ3 is changed from 1 to 0 while pin IRQ3 is low and IEGR bit IEG3 1 IRRI2 When PMR1 bit IRQ2 is changed from 0 to 1 while pin IRQ2 is low and IEGR bit IEG2 0 When PMR1 bit IRQ2 is changed from 1 to 0 while pin IRQ2 is low and IEGR bit IEG2 1 IRRI1 When PMR1 bit IRQ1 is changed from 0 to 1 while pin IRQ1 is low and IEGR bit IEG1 0 When PMR1 bit IRQ1 is changed from 1 to 0 ...

Page 97: ...ion the flag will not be cleared An alternative method is to avoid the setting of interrupt request flags when pin functions are switched by keeping the pins at the high level so that the conditions in table 3 5 do not occur Figure 3 7 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure CCR I bit 1 Set port mode register bit Execute NOP instruction Interrupts masked Another po...

Page 98: ...he CPU and on chip peripheral modules are ø and øSUB Four of the clock signals have names ø is the system clock øSUB is the subclock øOSC is the oscillator clock and øW is the watch clock The clock signals available for use by peripheral modules are ø 2 ø 4 ø 8 ø 16 ø 32 ø 64 ø 128 ø 256 ø 512 ø 1024 ø 2048 ø 4096 ø 8192 øW øW 2 øW 4 øW 8 øW 16 øW 32 øW 64 and øW 128 The clock requirements differ ...

Page 99: ...to Crystal Oscillator Figure 4 3 shows the equivalent circuit of a crystal oscillator An oscillator having the characteristics given in table 4 1 should be used Figure 4 3 Equivalent Circuit of Crystal Oscillator Table 4 1 Crystal Oscillator Parameters Frequency MHz 1 4 193 RS max Ω 40 100 C0 pF 3 5 pF max 16 pF CS C0 RS OSC1 OSC2 LS 1 2 C1 C2 OSC OSC R 1 M 20 f Ω Rf Frequency 1 0 MHz 4 0 MHz Crys...

Page 100: ... lines close to the oscillator circuit since the oscillator may be adversely affected by induction currents See figure 4 5 The board should be designed so that the oscillator and load capacitors are located as close as possible to pins OSC1 and OSC2 Figure 4 5 Board Design of Oscillator Circuit OSC OSC C1 C2 Signal A Signal B 2 1 To be avoided 1 2 C1 C2 OSC OSC Rf R 1 M 20 f Ω Frequency 1 0 MHz 4 ...

Page 101: ...SC Duty cycle 45 to 55 Note The circuit parameters above are recommended by the crystal or ceramic oscillator manufacturer The circuit parameters are affected by the crystal or ceramic oscillator and floating capacitance when designing the board When using the oscillator consult with the crystal or ceramic oscillator manufacturer to determine the circuit parameters 1 2 OSC OSC External clock input...

Page 102: ... for the system clock in 4 2 Figure 4 7 Typical Connection to 32 768 kHz 38 4 kHz Crystal Oscillator Subclock Figure 4 8 shows the equivalent circuit of the 32 768 kHz 38 4 kHz crystal oscillator Figure 4 8 Equivalent Circuit of 32 768 kHz 38 4 kHz Crystal Oscillator CS C0 L RS X1 X2 C 1 5 pF typ R 14 k typ f 32 768 kHz 38 4kHz 0 S W Ω S X X C1 C2 1 2 C C 15 pF typ 1 2 Frequency 32 768 kHz 38 4 kH...

Page 103: ...in figure 4 9 Figure 4 9 Pin Connection when not Using Subclock 3 External clock input Connect the external clock to the X1 pin and leave the X2 pin open as shown in figure 4 10 Figure 4 10 Pin Connection when Inputting External Clock Frequency Subclock øw Duty 45 to 55 X1 VCC External clock input X2 Open X X 1 2 GND Open 92 ...

Page 104: ...escaler S also stops and is initialized to H 0000 The CPU cannot read or write prescaler S The output from prescaler S is shared by timer A timer C timer F timer G SCI3 1 SC3 2 the A D converter the LCD controller the watchdog timer and the 14 bit PWM The divider ratio can be set separately for each on chip peripheral function In active medium speed mode the clock input to prescaler S is øosc 16 ø...

Page 105: ...e examples shown in this section Oscillator circuit constants will differ depending on the oscillator element stray capacitance in its interconnecting circuit and other factors Suitable constants should be determined in consultation with the oscillator element manufacturer Design the circuit so that the oscillator element never receives voltages exceeding its maximum rating 94 ...

Page 106: ...eripheral functions are operable on the system clock Sleep medium speed mode The CPU halts On chip peripheral functions operate at a frequency of 1 64 1 32 1 16 or 1 8 of the system clock frequency Subsleep mode The CPU halts The time base function of timer A timer C timer G timer F WDT SCI3 1 SCI3 2 AEC and LCD controller driver are operable on the subclock Watch mode The CPU halts The time base ...

Page 107: ...mode in sections 5 2 through 5 8 Notes 1 2 Mode Transition Conditions 1 a b c d e f g h i J LSON MSON SSBY DTON 0 0 1 0 0 0 0 1 0 0 1 0 1 1 0 0 0 0 1 1 0 0 1 1 1 0 0 0 0 0 1 1 1 1 1 Don t care Mode Transition Conditions 2 1 Interrupt Sources Timer A Timer F Timer G interrupt IRQ0 interrupt WKP7 to WKP0 interrupts Timer A Timer C Timer F Timer G SCI3 1 SCI3 2 interrupt IRQ4 to IRQ0 interrupts WKP7 ...

Page 108: ...ions 8 counter Timer C Retained Functions Functions Retained Retained 2 Retained 2 WDT Functions Retained Retained 7 Timer G Functions Functions Functions Timer F Retained 9 Retained 9 Retained 9 SCI3 1 Reset Functions Functions Reset Retained 3 SCI3 2 PWM Retained Retained Retained Retained A D converter Retained Retained Retained Retained LCD Functions Functions Functions Retained Retained 4 Ret...

Page 109: ...ed to H 07 Bit 7 Software standby SSBY This bit designates transition to standby mode or watch mode Bit 7 SSBY Description 0 When a SLEEP instruction is executed in active mode a transition initial value is made to sleep mode When a SLEEP instruction is executed in subactive mode a transition is made to subsleep mode 1 When a SLEEP instruction is executed in active mode a transition is made to sta...

Page 110: ...072 states 1 0 1 Wait time 2 states External clock mode 1 1 0 Wait time 8 states 1 1 1 Wait time 16 states Note In the case that external clock is input set up the Standby timer select selection to External clock mode before Mode Transition Also do not set up to external clock mode in the case that it does not use external clock Bit 3 Low speed on flag LSON This bit chooses the system clock ø or s...

Page 111: ...ister for power down mode control Bits 7 to 5 Reserved bits These bits are reserved they are always read as 1 and cannot be modified Bit 4 Noise elimination sampling frequency select NESEL This bit selects the frequency at which the watch clock signal øW generated by the subclock pulse generator is sampled in relation to the oscillator clock øOSC generated by the system clock pulse generator When ...

Page 112: ...ve mode if SSBY 1 TMA3 1 and LSON 1 When a SLEEP instruction is executed in active medium speed mode a direct transition is made to active high speed mode if SSBY 0 MSON 0 and LSON 0 or to subactive mode if SSBY 1 TMA3 1 and LSON 1 When a SLEEP instruction is executed in subactive mode a direct transition is made to active high speed mode if SSBY 1 TMA3 1 LSON 0 and MSON 0 or to active medium spee...

Page 113: ... are retained Furthermore it sometimes acts with half state early timing at the time of transition to sleep medium speed mode 5 2 2 Clearing Sleep Mode Sleep mode is cleared by any interrupt timer A timer C timer F timer G asynchronous counter IRQ4 to IRQ0 WKP7 to WKP0 SCI3 1 SCI3 2 A D converter or or by input at the RES pin Clearing by interrupt When an interrupt is requested sleep mode is clear...

Page 114: ...at the RES pin Clearing by interrupt When an interrupt is requested the system clock pulse generator starts After the time set in bits STS2 to STS0 in SYSCR1 has elapsed a stable system clock signal is supplied to the entire chip standby mode is cleared and interrupt exception handling starts Operation resumes in active high speed mode if MSON 0 in SYSCR2 or active medium speed mode if MSON 1 Stan...

Page 115: ...ettling Time times are in ms STS2 STS1 STS0 Waiting Time 2 MHz 1 MHz 0 5 MHz 0 0 0 8 192 states 4 1 8 2 16 4 0 0 1 16 384 states 8 2 16 4 32 8 0 1 0 32 768 states 16 4 32 8 65 5 0 1 1 65 536 states 32 8 65 5 131 1 1 0 0 131 072 states 65 5 131 1 262 1 1 0 1 2 states 0 001 0 002 0 004 Use prohibited 1 1 0 8 states 0 004 0 008 0 016 1 1 1 16 states 0 008 0 016 0 032 When an external clock is used ST...

Page 116: ...tion is made to standby mode At the same time pins go to the high impedance state except pins for which the pull up MOS is designated as on Figure 5 2 shows the timing in this case Figure 5 2 Standby Mode Transition and Pin States SLEEP instruction fetch Internal data bus Fetch of next instruction Port output Pins High impedance Active high speed mode or active medium speed mode Standby mode SLEEP...

Page 117: ...t When watch mode is cleared by interrupt the mode to which a transition is made depends on the settings of LSON in SYSCR1 and MSON in SYSCR2 If both LSON and MSON are cleared to 0 transition is to active high speed mode if LSON 0 and MSON 1 transition is to active medium speed mode if LSON 1 transition is to subactive mode When the transition is to active mode after the time set in SYSCR1 bits ST...

Page 118: ...p the same states as before the transition 5 5 2 Clearing Subsleep Mode Subsleep mode is cleared by an interrupt timer A timer C timer F timer G asynchronous counter SCI3 2 SCI3 1 IRQ4 to IRQ0 WKP7 to WKP0 or by a low input at the RES pin Clearing by interrupt When an interrupt is requested subsleep mode is cleared and interrupt exception handling starts Subsleep mode is not cleared if the I bit o...

Page 119: ...e Mode Subactive mode is cleared by a SLEEP instruction or by a low input at the RES pin Clearing by SLEEP instruction If a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 and TMA3 bit in TMA is set to 1 subactive mode is cleared and watch mode is entered If a SLEEP instruction is executed while SSBY 0 and LSON 1 in SYSCR1 and TMA3 1 in TMA subsleep mode is entered Direct tr...

Page 120: ...tive medium speed mode is cleared by a SLEEP instruction Clearing by SLEEP instruction A transition to standby mode takes place if the SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 the LSON bit in SYSCR1 is cleared to 0 and the TMA3 bit in TMA is cleared to 0 The system goes to watch mode if the SSBY bit in SYSCR1 is set to 1 and bit TMA3 in TMA is set to 1 when a SLEEP in...

Page 121: ...s set to 1 and the DTON bit in SYSCR2 is set to 1 a transition is made to active medium speed mode via sleep mode Direct transfer from active medium speed mode to active high speed mode When a SLEEP instruction is executed in active medium speed mode while the SSBY and LSON bits in SYSCR1 are cleared to 0 the MSON bit in SYSCR2 is cleared to 0 and the DTON bit in SYSCR2 is set to 1 a transition is...

Page 122: ...S2 to STS0 has elapsed 5 8 2 Direct Transition Times 1 Time for direct transition from active high speed mode to active medium speed mode A direct transition from active high speed mode to active medium speed mode is performed by executing a SLEEP instruction in active high speed mode while bits SSBY and LSON are both cleared to 0 in SYSCR1 and bits MSON and DTON are both set to 1 in SYSCR2 The ti...

Page 123: ... Direct transition time 2 1 16tosc 14 2tosc 76tosc when ø 8 is selected as the CPU operating clock Notation tosc OSC clock cycle time tcyc System clock ø cycle time 3 Time for direct transition from subactive mode to active high speed mode A direct transition from subactive mode to active high speed mode is performed by executing a SLEEP instruction in subactive mode while bit SSBY is set to 1 and...

Page 124: ...its MSON and DTON are both set to 1 in SYSCR2 and bit TMA3 is set to 1 in TMA The time from execution of the SLEEP instruction to the end of interrupt exception handling the direct transition time is given by equation 4 below Direct transition time Number of SLEEP instruction execution states number of internal processing states tsubcyc before transition wait time set in STS2 to STS0 number of int...

Page 125: ...op register 1 CKSTPR1 or clock stop register 2 CKSTPR2 See table 5 5 Following a reset clock stop register 1 CKSTPR1 and clock stop register 2 CKSTPR2 are both initialized to H FF Table 5 5 Register Name Bit Name Operation CKSTPR1 TACKSTP 1 Timer A module standby mode is cleared 0 Timer A is set to module standby mode TCCKSTP 1 Timer C module standby mode is cleared 0 Timer C is set to module stan...

Page 126: ... mode is cleared 0 PWM is set to module standby mode WDCKSTP 1 Watchdog timer module standby mode is cleared 0 Watchdog timer is set to module standby mode AECKSTP 1 Asynchronous event counter module standby mode is cleared 0 Asynchronous event counter is set to module standby mode Note For details of module operation see the sections on the individual modules 115 ...

Page 127: ...e ROM is connected to the CPU by a 16 bit data bus allowing high speed two state access for both byte data and word data The H8 3867 and H8 3827 have a ZTAT version with 60 kbyte PROM 6 1 1 Block Diagram Figure 6 1 shows a block diagram of the on chip ROM Figure 6 1 ROM Block Diagram H8 3864 and H8 3824 H 7FFE H 7FFF Internal data bus upper 8 bits Internal data bus lower 8 bits Even numbered addre...

Page 128: ...ST High level PB4 AN4 Low level PB5 AN5 PB6 AN6 High level 6 2 2 Socket Adapter Pin Arrangement and Memory Map A standard PROM programmer can be used to program the PROM A socket adapter is required for conversion to 32 pins as listed in table 6 2 Figure 6 2 shows the pin to pin wiring of the socket adapter Figure 6 3 shows a memory map Table 6 2 Socket Adapter Package Socket Adapters Manufacturer...

Page 129: ...14 18 7 29 4 80 1 HN27C101 32 pin 1 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 22 24 31 32 16 RES P60 P61 P62 P63 P64 P65 P66 P67 P87 P86 P85 P84 P83 P82 P81 P80 P70 P43 P72 P73 P74 P75 P76 P14 P15 P77 P71 P13 VCC CVCC AVCC TEST X1 PB6 P11 P12 P16 VSS AVSS PB4 PB5 Pin VPP EO0 EO1 EO2 EO3 EO4 EO5 EO6 EO7 EA0 EA1 EA2 EA3 EA4 EA5 EA6 EA7 EA8 EA9 EA10 EA11 EA12 EA13 EA14 EA15 E...

Page 130: ...ot guaranteed if this address area is read in PROM mode There fore when programming with a PROM programmer be sure to specify addresses from H 0000 to H EDFF If programming is inadvertently performed from H EE00 onward it may not be possible to continue PROM programming and verification When programming H FF should be set as the data in this address area H EE00 to H 1FFFF Note 120 ...

Page 131: ... identical to those for the standard HN27C101 EPROM However page programming is not supported and so page programming mode must not be set A PROM programmer that only supports page programming mode cannot be used When selecting a PROM programmer ensure that it supports high speed high reliability byte by byte programming Also be sure to specify addresses from H 0000 to H EDFF 6 3 1 Writing and Ver...

Page 132: ... write verify mode V 6 0 V 0 25 V V 12 5 V 0 3 V CC PP Address 0 n 0 n 1 n PW Verify Write time t 3n ms OPW Last address Set read mode V 5 0 V 0 25 V V V CC PP CC Read all addresses End Error n 25 Address 1 address No Yes No Go Go Yes No No Go Go Write time t 0 2 ms 5 122 ...

Page 133: ...nit Condition Input high EO7 to EO0 EA16 to EA0 VIH 2 4 VCC 0 3 V level voltage OE CE PGM Input low EO7 to EO0 EA16 to EA0 VIL 0 3 0 8 V level voltage OE CE PGM Output high EO7 to EO0 VOH 2 4 V IOH 200 µA level voltage Output low EO7 to EO0 VOL 0 45 V IOL 0 8 mA level voltage Input leakage EO7 to EO0 EA16 to EA0 ILI 2 µA Vin 5 25 V current OE CE PGM 0 5 V VCC current ICC 40 mA VPP current IPP 40 m...

Page 134: ...s Programming pulse width tPW 0 19 0 20 0 21 ms PGM pulse width for overwrite tOPW 3 0 19 5 25 ms programming CE setup time tCES 2 µs VCC setup time tVCS 2 µs Data output delay time tOE 0 200 ns Notes 1 Input pulse level 0 45 V to 2 2 V Input rise time fall time 20 ns Timing reference levels Input 0 8 V 2 0 V Output 0 8 V 2 0 V 2 tDF is defined at the point at which the output is floating and the ...

Page 135: ...M Write Verify Timing Write Input data Output data Verify Address Data VPP VPP tAS tAH tDS tDH tDF tOE tOES tPW tOPW tVPS tVCS tCES VCC VCC CE PGM OE VCC 1 VCC Note topw is defined by the value shown in figure 6 4 High Speed High Reliability Programming Flowchart 125 ...

Page 136: ...ned If they are not the chip may be destroyed by excessive current flow Before programming be sure that the chip is properly mounted in the PROM programmer Avoid touching the socket adapter or chip while programming since this may cause contact faults and write errors Take care when setting the programming mode as page programming is not supported When programming with a PROM programmer be sure to...

Page 137: ...ning procedure Figure 6 6 Recommended Screening Procedure If a series of programming errors occurs while the same PROM programmer is in use stop programming and check the PROM programmer and socket adapter for defects Please inform Hitachi of any abnormal conditions noted during or after programming or in screening of program data after high temperature baking Program chip and verify programmed da...

Page 138: ... connected to the CPU by a 16 bit data bus allowing high speed 2 state access for both byte data and word data 7 1 1 Block Diagram Figure 7 1 shows a block diagram of the on chip RAM Figure 7 1 RAM Block Diagram H8 3864 and H8 3824 H FF7E H FF7F Internal data bus upper 8 bits Internal data bus lower 8 bits Even numbered address Odd numbered address H FF7E H F782 H F780 H F780 H F782 H F781 H F783 ...

Page 139: ...witching Port Description Pins Other Functions Registers Port 1 8 bit I O port P17 to P15 External interrupts 3 to 1 PMR1 MOS input pull up IRQ3 to IRQ1 Timer event interrupts TCRF option TMIF TMIC TMIF TMIC TMC P14 IRQ4 ADTRG External interrupt 4 and A D PMR1 AMR converter external trigger P13 TMIG Timer G input capture input PMR1 P12 P11 Timer F output compare PMR1 TMOFH TMOFL output P10 TMOW Ti...

Page 140: ...pull up SEG16 to SEG9 to SEG9 option Port 7 8 bit I O port P77 to P70 Segment output SEG24 LPCR SEG24 to SEG17 to SEG17 Port 8 8 bit I O port P87 SEG32 CL1 Segment output LPCR P86 SEG31 CL2 SEG32 to SEG25 P85 SEG30 DO Segment external expansion P84 SEG29 M latch clock CL1 P83 to P80 shift clock CL2 SEG28 to SEG25 display data DO alternation signal M Port A 4 bit I O port PA3 to PA0 Common output C...

Page 141: ...he port 1 register configuration Table 8 2 Port 1 Registers Name Abbrev R W Initial Value Address Port data register 1 PDR1 R W H 00 H FFD4 Port control register 1 PCR1 W H 00 H FFE4 Port pull up control register 1 PUCR1 R W H 00 H FFE0 Port mode register 1 PMR1 R W H 00 H FFC8 P1 IRQ TMIF P1 IRQ P1 IRQ TMIC P1 IRQ ADTRG P1 TMIG 7 6 5 4 3 3 2 1 4 Port 1 P1 TMOFH P1 TMOFL P1 TMOW 2 1 0 133 ...

Page 142: ...functions as an input pin or output pin Setting a PCR1 bit to 1 makes the corresponding pin an output pin while clearing the bit to 0 makes the pin an input pin The settings in PCR1 and in PDR1 are valid only when the corresponding pin is designated in PMR1 as a general I O pin Upon reset PCR1 is initialized to H 00 PCR1 is a write only register which is always read as all 1s Bit Initial value Rea...

Page 143: ... PMR1 is initialized to H 00 Bit 7 P17 IRQ3 TMIF pin function switch IRQ3 This bit selects whether pin P17 IRQ3 TMIF is used as P17 or as IRQ3 TMIF Bit 7 IRQ3 Description 0 Functions as P17 I O pin initial value 1 Functions as IRQ3 TMIF input pin Note Rising or falling edge sensing can be designated for IRQ3 TMIF For details on TMIF settings see 3 Timer Control Register F TCRF in 9 4 2 Bit Initial...

Page 144: ...C input pin Note Rising or falling edge sensing can be designated for IRQ1 TMIC For details of TMIC pin setting see 1 Timer mode register C TMC in 9 3 2 Bit 4 P14 IRQ4 ADTRG pin function switch IRQ4 This bit selects whether pin P14 IRQ4 ADTRG is used as P14 or as IRQ4 ADTRG Bit 4 IRQ4 Description 0 Functions as P14 I O pin initial value 1 Functions as IRQ4 ADTRG input pin Note For details of ADTRG...

Page 145: ...Bit 1 P11 TMOFL pin function switch TMOFL This bit selects whether pin P11 TMOFL is used as P11 or as TMOFL Bit 1 TMOFL Description 0 Functions as P11 I O pin initial value 1 Functions as TMOFL output pin Bit 0 P10 TMOW pin function switch TMOW This bit selects whether pin P10 TMOW is used as P10 or as TMOW Bit 0 TMOW Description 0 Functions as P10 I O pin initial value 1 Functions as TMOW output ...

Page 146: ... in PCR1 IRQ2 0 1 PCR16 0 1 Pin function P16 input pin P16 output pin IRQ2 input pin P15 IRQ1 The pin function depends on bit IRQ1 in PMR1 bits TMC2 to TMC0 in TMC and TMIC bit PCR15 in PCR1 IRQ1 0 1 PCR15 0 1 TMC2 to TMC0 Not 111 111 Pin function P15 input pin P15 output pin IRQ1 input pin IRQ1 TMIC input pin Note When this pin is used as the TMIC input pin clear bit IEN1 to 0 in IENR1 to disable...

Page 147: ... depends on bit TMOFH in PMR1 and bit PCR12 in PCR1 TMOFH 0 1 PCR12 0 1 Pin function P12 input pin P12 output pin TMOFH output pin P11 TMOFL The pin function depends on bit TMOFL in PMR1 and bit PCR11 in PCR1 TMOFL 0 1 PCR11 0 1 Pin function P11 input pin P11 output pin TMOFL output pin P10 TMOW The pin function depends on bit TMOW in PMR1 and bit PCR10 in PCR1 TMOW 0 1 PCR10 0 1 Pin function P10 ...

Page 148: ...te state state P14 IRQ4 ADTRG P13 TMIG P12 TMOFH P11 TMOFL P10 TMOW Note A high level signal is output when the MOS pull up is in the on state 8 2 5 MOS Input Pull Up Port 1 has a built in MOS input pull up function that can be controlled by software When a PCR1 bit is cleared to 0 setting the corresponding PUCR1 bit to 1 turns on the MOS input pull up for that pin The MOS input pull up function i...

Page 149: ...shows the port 3 register configuration Table 8 5 Port 3 Registers Name Abbrev R W Initial Value Address Port data register 3 PDR3 R W H 00 H FFD6 Port control register 3 PCR3 W H 00 H FFE6 Port pull up control register 3 PUCR3 R W H 00 H FFE1 Port mode register 3 PMR3 R W H 04 H FFCA P3 AEVL P3 AEVH P3 TXD 7 6 5 Port 3 31 P3 RXD P3 SCK P3 RESO 4 3 2 31 31 P3 UD P3 PWM 1 0 141 ...

Page 150: ...functions as an input pin or output pin Setting a PCR3 bit to 1 makes the corresponding pin an output pin while clearing the bit to 0 makes the pin an input pin The settings in PCR3 and in PDR3 are valid only when the corresponding pin is designated in PMR3 as a general I O pin Upon reset PCR3 is initialized to H 00 PCR3 is a write only register which is always read as all 1s Bit Initial value Rea...

Page 151: ...ized to H 04 Bit 7 P37 AEVL pin function switch AEVL This bit selects whether pin P37 AEVL is used as P37 or as AEVL Bit 7 AEVL Description 0 Functions as P37 I O pin initial value 1 Functions as AEVL input pin Bit 6 P36 AEVH pin function switch AEVH This bit selects whether pin P36 AEVH is used as P36 or as AEVH Bit 6 AEVH Description 0 Functions as P36 I O pin initial value 1 Functions as AEVH i...

Page 152: ...ription 0 Noise cancellation function not used initial value 1 Noise cancellation function used Bit 3 P43 IRQ0 pin function switch IRQ0 This bit selects whether pin P43 IRQ0 is used as P43 or as IRQ0 Bit 3 IRQ0 Description 0 Functions as P43 input pin initial value 1 Functions as IRQ0 input pin Bit 2 P32 RESO pin function switch RESO This bit selects whether pin P32 RESO is used as P32 or as RESO ...

Page 153: ...nctions as P30 I O pin initial value 1 Functions as PWM output pin 8 3 3 Pin Functions Table 8 9 shows the port 3 pin functions Table 8 9 Port 3 Pin Functions Pin Pin Functions and Selection Method P37 AEVL The pin function depends on bit SO1 in PMR3 and bit PCR32 in PCR3 AEVL 0 1 PCR37 0 1 Pin function P37 input pin P37 output pin AEVL input pin P36 AEVH The pin function depends on bit AEVH in PM...

Page 154: ...ds on bits CKE1 CKE0 and SMR31 in SCR3 1 and bit PCR33 in PCR3 CKE1 0 1 CKE0 0 1 COM31 0 1 PCR33 0 1 Pin function P33 input pin P33 output pin SCK31 SCK31 output pin input pin P32 RESO The pin function depends on bit RESO in PMR3 and bit PCR32 in PCR3 RESO 0 1 PCR32 0 1 Pin function P32 input pin P32 output pin RESO output pin P31 UD The pin function depends on bit UD in PMR3 and bit PCR31 in PCR3...

Page 155: ...e state P34 RXD31 P33 SCK31 P32 RESO RESO output P31 UD High P30 PWM impedance Note A high level signal is output when the MOS pull up is in the on state 8 3 5 MOS Input Pull Up Port 3 has a built in MOS input pull up function that can be controlled by software When a PCR3 bit is cleared to 0 setting the corresponding PUCR3 bit to 1 turns on the MOS pull up for that pin The MOS pull up function is...

Page 156: ... H F8 H FFD7 Port control register 4 PCR4 W H F8 H FFE7 1 Port data register 4 PDR4 PDR4 is an 8 bit register that stores data for port 4 pins P42 to P40 If port 4 is read while PCR4 bits are set to 1 the values stored in PDR4 are read regardless of the actual pin states If port 4 is read while PCR4 bits are cleared to 0 the pin states are read Upon reset PDR4 is initialized to H F8 Bit Initial va...

Page 157: ... all 1s 8 4 3 Pin Functions Table 8 9 shows the port 4 pin functions Table 8 9 Port 4 Pin Functions Pin Pin Functions and Selection Method P43 IRQ0 The pin function depends on bit IRQ0 in PMR3 IRQ0 0 1 Pin function P43 input pin IRQ0 input pin P42 TXD32 The pin function depends on bit TE in SCR3 2 bit SPC32 in SPCR and bit PCR42 in PCR4 SPC32 0 1 TE 0 1 PCR42 0 1 Pin function P42 input pin P42 out...

Page 158: ... PCR40 0 1 Pin function P40 input pin P40 output pin SCK32 SCK32 output pin input pin 8 4 4 Pin States Table 8 10 shows the port 4 pin states in each operating mode Table 8 10 Port 4 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active P43 IRQ0 High Retains Retains High Retains Functional Functional P42 TXD32 impedance previous previous impedance previous P41 RXD32 state state state...

Page 159: ... 5 register configuration Table 8 11 Port 5 Registers Name Abbrev R W Initial Value Address Port data register 5 PDR5 R W H 00 H FFD8 Port control register 5 PCR5 W H 00 H FFE8 Port pull up control register 5 PUCR5 R W H 00 H FFE2 Port mode register 5 PMR5 R W H 00 H FFCC P57 WKP7 SEG8 P56 WKP6 SEG7 P55 WKP5 SEG6 P54 WKP4 SEG5 P53 WKP3 SEG4 P52 WKP2 SEG3 P51 WKP1 SEG2 P50 WKP0 SEG1 Port 5 151 ...

Page 160: ...tput by PMR5 and bits SGS3 to SGS0 in LPCR Upon reset PCR5 is initialized to H 00 PCR5 is a write only register which is always read as all 1s 3 Port pull up control register 5 PUCR5 PUCR5 controls whether the MOS pull up of each of port 5 pins P57 to P50 is on or off When a PCR5 bit is cleared to 0 setting the corresponding PUCR5 bit to 1 turns on the MOS pull up for the corresponding pin while c...

Page 161: ...n When pin P5n WKPn SEGn 1 is not used as SEGn 1 these bits select whether the pin is used as P5n or WKPn Bit n WKPn Description 0 Functions as P5n I O pin initial value 1 Functions as WKPn input pin n 7 to 0 Note For use as SEGn 1 see 13 2 1 LCD Port Control Register LPCR Bit Initial value Read Write 7 WKP7 0 R W 6 WKP6 0 R W 5 WKP5 0 R W 4 WKP4 0 R W 3 WKP3 0 R W 0 WKP0 0 R W 2 WKP2 0 R W 1 WKP1...

Page 162: ...in Pin Functions and Selection Method P57 WKP7 The pin function depends on bit WKPn in PMR5 bit PCR5n in PCR5 and bits SEG8 to SGS3 to SGS0 in LPCR P50 WKP0 n 7 to 0 SEG1 SGS3 to SGS0 0 1 WKPn 0 1 PCR5n 0 1 Pin function P5n input pin P5n output pin WKPn SEGn 1 input pin output pin Don t care 154 ...

Page 163: ...pedance previous WKP0 SEG1 state state state Note A high level signal is output when the MOS pull up is in the on state 8 5 5 MOS Input Pull Up Port 5 has a built in MOS input pull up function that can be controlled by software When a PCR5 bit is cleared to 0 setting the corresponding PUCR5 bit to 1 turns on the MOS pull up for that pin The MOS pull up function is in the off state after a reset PC...

Page 164: ...ation and Description Table 8 14 shows the port 6 register configuration Table 8 14 Port 6 Registers Name Abbrev R W Initial Value Address Port data register 6 PDR6 R W H 00 H FFD9 Port control register 6 PCR6 W H 00 H FFE9 Port pull up control register 6 PUCR6 R W H 00 H FFE3 P67 SEG16 P66 SEG15 P65 SEG14 P64 SEG13 P63 SEG12 P62 SEG11 P61 SEG10 P60 SEG9 Port 6 156 ...

Page 165: ...rpose input output by bits SGS3 to SGS0 in LPCR Upon reset PCR6 is initialized to H 00 PCR6 is a write only register which always reads all 1s 3 Port pull up control register 6 PUCR6 PUCR6 controls whether the MOS pull up of each of the port 6 pins P67 to P60 is on or off When a PCR6 bit is cleared to 0 setting the corresponding PUCR6 bit to 1 turns on the MOS pull up for the corresponding pin whi...

Page 166: ...Port 6 Pin States Pin Reset Sleep Subsleep Standby Watch Subactive Active P67 SEG16 High Retains Retains High Retains Functional Functional to impedance previous previous impedance previous P60 SEG9 state state state Note A high level signal is output when the MOS pull up is in the on state 8 6 5 MOS Input Pull Up Port 6 has a built in MOS pull up function that can be controlled by software When a...

Page 167: ...Register Configuration and Description Table 8 17 shows the port 7 register configuration Table 8 17 Port 7 Registers Name Abbrev R W Initial Value Address Port data register 7 PDR7 R W H 00 H FFDA Port control register 7 PCR7 W H 00 H FFEA P77 SEG24 P76 SEG23 P75 SEG22 P74 SEG21 P73 SEG20 Port 7 P72 SEG19 P71 SEG18 P70 SEG17 159 ...

Page 168: ... as an input pin or output pin Setting a PCR7 bit to 1 makes the corresponding pin an output pin while clearing the bit to 0 makes the pin an input pin PCR7 and PDR7 settings are valid when the corresponding pins are designated for general purpose input output by bits SGS3 to SGS0 in LPCR Upon reset PCR7 is initialized to H 00 PCR7 is a write only register which always reads as all 1s Bit Initial ...

Page 169: ...G17 n 7 to 0 SEGS3 to SEGS0 00 01 1 PCR7n 0 1 Pin function P7n input pin P7n output pin SEGn 17 output pin Don t care 8 7 4 Pin States Table 8 19 shows the port 7 pin states in each operating mode Table 8 19 Port 7 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active P77 SEG24 High Retains Retains High Retains Functional Functional to impedance previous previous impedance previous P...

Page 170: ...er Configuration and Description Table 8 20 shows the port 8 register configuration Table 8 20 Port 8 Registers Name Abbrev R W Initial Value Address Port data register 8 PDR8 R W H 00 H FFDB Port control register 8 PCR8 W H 00 H FFEB P87 SEG32 CL1 P86 SEG31 CL2 P85 SEG30 DO P84 SEG29 M P83 SEG28 Port 8 P82 SEG27 P81 SEG26 P80 SEG25 162 ...

Page 171: ...s as an input or output pin Setting a PCR8 bit to 1 makes the corresponding pin an output pin while clearing the bit to 0 makes the pin an input pin PCR8 and PDR8 settings are valid when the corresponding pins are designated for general purpose input output by bits SGS3 to SGS0 in LPCR Upon reset PCR8 is initialized to H 00 PCR8 is a write only register which is always read as all 1s Bit Initial v...

Page 172: ...86 input pin P86 output pin SEG31 output pin CL2 output pin P85 SEG30 The pin function depends on bit PCR85 in PCR8 and bits SGX and SGS3 to SGS0 DO in LPCR SEGS3 to SEGS0 000 001 01 1 SGX 0 0 1 PCR95 0 1 Pin function P85 input pin P85 output pin SEG30 output pin D0 output pin P84 SEG29 The pin function depends on bit PCR84 in PCR8 and bits SGX and SGS3 to SGS0 M in LPCR SEGS3 to SEGS0 000 001 01 ...

Page 173: ...le 8 22 Port 8 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active P87 SEG32 CL1 High Retains Retains High Retains Functional Functional P86 SEG31 CL2 impedance previous previous impedance previous P85 SEG30 DO state state state P84 SEG29 M P83 SEG28 to P80 SEG25 165 ...

Page 174: ...er A PDRA R W H F0 H FFDD Port control register A PCRA W H F0 H FFED 1 Port data register A PDRA PDRA is an 8 bit register that stores data for port A pins PA3 to PA0 If port A is read while PCRA bits are set to 1 the values stored in PDRA are read regardless of the actual pin states If port A is read while PCRA bits are cleared to 0 the pin states are read Bit Initial value Read Write 7 1 6 1 5 1...

Page 175: ...esponding pin an output pin while clearing the bit to 0 makes the pin an input pin PCRA and PDRA settings are valid when the corresponding pins are designated for general purpose input output by LPCR Upon reset PCRA is initialized to H F0 PCRA is a write only register which always reads all 1s Bit Initial value Read Write 7 1 6 1 5 1 4 1 3 PCRA 0 R W 0 PCRA 0 R W 2 PCRA 0 R W 1 PCRA 0 R W 3 2 1 0 ...

Page 176: ...n PA1 COM2 The pin function depends on bit PCRA1 in PCRA and bits SGS3 to SGS0 SEGS3 to SEGS0 0000 0000 Not 0000 PCRA1 0 1 Pin function PA1 input pin PA1 output pin COM2 output pin PA0 COM1 The pin function depends on bit PCRA0 in PCRA and bits SGS3 to SGS0 SEGS3 to SEGS0 0000 Not 0000 PCRA0 0 1 Pin function PA0 input pin PA0 output pin COM1 output pin Don t care 8 9 4 Pin States Table 8 25 shows ...

Page 177: ...gister Name Abbrev R W Address Port data register B PDRB R H FFDE Port Data Register B PDRB Reading PDRB always gives the pin states However if a port B pin is selected as an analog input channel for the A D converter by AMR bits CH3 to CH0 that pin reads 0 regardless of the input voltage Bit Read Write 7 PB R 6 PB R 5 PB R 4 PB R 3 PB R 0 PB R 2 PB R 1 PB R 3 2 1 0 7 6 5 4 PB7 AN7 PB6 AN6 PB5 AN5...

Page 178: ...on function Table 8 27 Register Configuration Name Abbreviation R W Address Serial port control register SPCR R W H FF91 Serial Port Control Register SPCR SPCR is an 8 bit readable writable register that performs RXD31 RXD32 TXD31 and TXD32 pin input output data inversion switching SPCR is initialized to H C0 by a reset Bit Initial value Read Write 7 1 6 1 5 SPC32 0 R W 4 SPC31 0 R W 3 SCINV3 0 R ...

Page 179: ...INV1 Description 0 TXD31 output data is not inverted initial value 1 TXD31 output data is inverted Bit 2 RXD32 pin input data inversion switch Bit 2 specifies whether or not RXD32 pin input data is to be inverted Bit 2 SCINV2 Description 0 RXD32 input data is not inverted initial value 1 RXD32 input data is inverted Bit 3 TXD32 pin output data inversion switch Bit 3 specifies whether or not TXD32 ...

Page 180: ...tion 0 Functions as P42 I O pin initial value 1 Functions as TXD32 output pin Note Set the TE bit in SCR3 after setting this bit to 1 Bits 7 and 6 Reserved bits Bits 7 and 6 are reserved they are always read as 1 and cannot be modified 8 11 3 Note on Modification of Serial Port Control Register When a serial port control register is modified the data being input or output up to that point is inver...

Page 181: ...o ø 32 TMOW øw øw 4 to øw 32 9 choices Timer C 8 bit timer ø 4 to ø 8192 øw 4 TMIC Up count Interval function 7 choices down count Event counting controllable by function software or Up count down hardware count selectable Timer F 16 bit timer ø 4 to ø 32 øw 4 TMIF TMOFL Event counting 4 choices TMOFH function Also usable as two independent 8 bit timers Output compare output function Timer G 8 bit...

Page 182: ...ons cont Event Waveform Name Functions Internal Clock Input Pin Output Pin Remarks Asynchro 16 bit counter AEVL nous Also usable as two AEVH event independent 8 bit counter counters Counts events asynchronous to ø and øw 174 ...

Page 183: ...oice of eight internal clock sources ø 8192 ø 4096 ø 2048 ø 512 ø 256 ø 128 ø 32 ø 8 Choice of four overflow periods 1 s 0 5 s 0 25 s 31 25 ms when timer A is used as a clock time base using a 32 768 kHz crystal oscillator An interrupt is requested when the counter overflows Any of nine clock signals can be output at the TMOW pin 32 768 kHz divided by 32 16 8 or 4 1 kHz 2 kHz 4 kHz 8 kHz or 38 4 k...

Page 184: ... by timer A output circuit ø PSW Internal data bus PSS Notation TMOW 1 4 TMA CWORS TCA øW 32 øW 16 øW 8 øW 4 ø 32 ø 16 ø 8 ø 4 ø 128 W ø 8192 ø 4096 ø 2048 ø 512 ø 256 ø 128 ø 32 ø 8 IRRTA 8 64 128 256 ø 4 W TMA TCA IRRTA PSW PSS CWOSR Note Can be selected only when the prescaler W output øW 128 is used as the TCA input clock Timer mode register A Timer counter A Timer A overflow interrupt request...

Page 185: ...FB1 Clock stop register 1 CKSTPR1 R W H FF H FFFA Subclock output select register CWOSR R W H FE H FF92 9 2 2 Register Descriptions 1 Timer mode register A TMA TMA is an 8 bit read write register for selecting the prescaler input clock and output clock Upon reset TMA is initialized to H 10 Bit Initial value Read Write 7 TMA7 0 R W 6 TMA6 0 R W 5 TMA5 0 R W 4 1 3 TMA3 0 R W 0 TMA0 0 R W 2 TMA2 0 R ...

Page 186: ...2 768 kHz or 38 4 kHz signal divided by 32 16 8 or 4 can be output in active mode sleep mode and subactive mode øw is output in all modes except the reset state CWOSR TMA Bit 7 Bit 6 Bit 5 CWOS TMA7 TMA6 TMA5 Clock Output 0 0 0 0 ø 32 initial value 1 ø 16 1 0 ø 8 1 ø 4 1 0 0 øw 32 1 øw 16 1 0 øw 8 1 øw 4 1 øw Don t care Bit 4 Reserved bit Bit 4 is reserved it is always read as 1 and cannot be modi...

Page 187: ...t 0 Prescaler and Divider Ratio TMA3 TMA2 TMA1 TMA0 or Overflow Period Function 0 0 0 0 PSS ø 8192 initial value Interval timer 1 PSS ø 4096 1 0 PSS ø 2048 1 PSS ø 512 1 0 0 PSS ø 256 1 PSS ø 128 1 0 PSS ø 32 1 PSS ø 8 1 0 0 0 PSW 1 s Clock time 1 PSW 0 5 s base 1 0 PSW 0 25 s when using 1 PSW 0 03125 s 32 768 kHz 1 0 0 PSW and TCA are reset 1 1 0 1 179 ...

Page 188: ...8 bit read write register that performs module standby mode control for peripheral modules Only the bit relating to timer A is described here For details of the other bits see the sections on the relevant modules Bit 0 Timer A module standby mode control TACKSTP Bit 0 controls setting and clearing of module standby mode for timer A TACKSTP Description 0 Timer A is set to module standby mode 1 Time...

Page 189: ...on reset TCA is cleared to H 00 and bit TMA3 is cleared to 0 so up counting and interval timing resume immediately The clock input to timer A is selected by bits TMA2 to TMA0 in TMA any of eight internal clock signals output by prescaler S can be selected After the count value in TCA reaches H FF the next clock signal input causes timer A to overflow setting bit IRRTA to 1 in interrupt request reg...

Page 190: ... signal divided by 32 16 8 or 4 can be output in active mode sleep mode watch mode subactive mode and subsleep mode The 32 768 kHz or 38 4 kHz clock is output in all modes except the reset state 9 2 4 Timer A Operation States Table 9 4 summarizes the timer A operation states Table 9 4 Timer A Operation States Sub Sub Module Operation Mode Reset Active Sleep Watch active sleep Standby Standby TCA I...

Page 191: ...192 ø 2048 ø 512 ø 64 ø 16 ø 4 øw 4 or an external clock can be used to count external events An interrupt is requested when the counter overflows Up down counter switching is possible by hardware or software Subactive mode and subsleep mode operation is possible when øw 4 is selected as the internal clock or when an external clock is selected Use of module standby mode enables this module to be p...

Page 192: ... of timer C Figure 9 2 Block Diagram of Timer C UD ø TMIC øW 4 PSS TMC Internal data bus TCC TLC IRRTC Notation TMC TCC TLC IRRTC PSS Timer mode register C Timer counter C Timer load register C Timer C overflow interrupt request flag Prescaler S 184 ...

Page 193: ... Registers Name Abbrev R W Initial Value Address Timer mode register C TMC R W H 18 H FFB4 Timer counter C TCC R H 00 H FFB5 Timer load register C TLC W H 00 H FFB5 Clock stop register 1 CKSTPR1 R W H FF H FFFA 9 3 2 Register Descriptions 1 Timer mode register C TMC TMC is an 8 bit read write register for selecting the auto reload function and input clock and performing up down counter control Upo...

Page 194: ...re Bits 4 and 3 Reserved bits Bits 4 and 3 are reserved they are always read as 1 and cannot be modified Bits 2 to 0 Clock select TMC2 to TMC0 Bits 2 to 0 select the clock input to TCC For external event counting either the rising or falling edge can be selected Bit 2 Bit 1 Bit 0 TMC2 TMC1 TMC0 Description 0 0 0 Internal clock ø 8192 initial value 0 0 1 Internal clock ø 2048 0 1 0 Internal clock ø...

Page 195: ...ister C TMC TCC values can be read by the CPU at any time When TCC overflows from H FF to H 00 or to the value set in TLC or underflows from H 00 to H FF or to the value set in TLC the IRRTC bit in IRR2 is set to 1 TCC is allocated to the same address as TLC Upon reset TCC is initialized to H 00 Bit Initial value Read Write 7 TCC7 0 R 6 TCC6 0 R 5 TCC5 0 R 4 TCC4 0 R 3 TCC3 0 R 0 TCC0 0 R 2 TCC2 0...

Page 196: ...er 1 CKSTPR1 CKSTPR1 is an 8 bit read write register that performs module standby mode control for peripheral modules Only the bit relating to timer C is described here For details of the other bits see the sections on the relevant modules Bit 1 Timer C module standby mode control TCCKSTP Bit 1 controls setting and clearing of module standby mode for timer C TCCKSTP Description 0 Timer C is set to...

Page 197: ...MIC The selection is made by bits TMC2 to TMC0 in TMC TCC up down count control can be performed either by software or hardware The selection is made by bits TMC6 and TMC5 in TMC After the count value in TCC reaches H FF H 00 the next clock input causes timer C to overflow underflow setting bit IRRTC to 1 in IRR2 If IENTC 1 in interrupt enable register 2 IENR2 a CPU interrupt is requested At overf...

Page 198: ...e are the same as in interval mode In auto reload mode TMC7 1 when a new value is set in TLC the TLC value is also set in TCC 3 Event counter operation Timer C can operate as an event counter counting rising or falling edges of an external event signal input at pin TMIC External event counting is selected by setting bits TMC2 to TMC0 in timer mode register C to all 1s 111 When timer C is used to c...

Page 199: ...cted as the TCC internal clock in active mode or sleep mode since the system clock and internal clock are mutually asynchronous synchronization is maintained by a synchronization circuit This results in a maximum count cycle error of 1 ø s When the counter is operated in subactive mode or subsleep mode either select øw 4 as the internal clock or select an external clock The counter will not operat...

Page 200: ...t sources one compare match one overflow Can operate as two independent 8 bit timers timer FH and timer FL in 8 bit mode Timer FL Timer FH 8 Bit Timer 8 Bit Timer Event Counter Internal clock Choice of 4 ø 32 ø 16 ø 4 øw 4 Event input TMIF pin Toggle output One compare match signal One compare match signal output to TMOFH pin output to TMOFL pin initial value settable initial value settable Counte...

Page 201: ...FL TCFH OCRFH TCSRF Comparator Comparator Match IRRTFH IRRTFL Notation TCRF TCSRF TCFH TCFL OCRFH OCRFL IRRTFH IRRTFL PSS Timer control register F Timer control status register F 8 bit timer counter FH 8 bit timer counter FL Output compare register FH Output compare register FL Timer FH interrupt request flag Timer FL interrupt request flag Prescaler S Internal data bus ...

Page 202: ...le output pin 4 Register configuration Table 9 9 shows the register configuration of timer F Table 9 9 Timer F Registers Name Abbrev R W Initial Value Address Timer control register F TCRF W H 00 H FFB6 Timer control status register F TCSRF R W H 00 H FFB7 8 bit timer counter FH TCFH R W H 00 H FFB8 8 bit timer counter FL TCFL R W H 00 H FFB9 Output compare register FH OCRFH R W H FF H FFBA Output...

Page 203: ...TCF operates as a 16 bit counter The TCF input clock is selected by bits CKSL2 to CKSL0 in TCRF TCF can be cleared in the event of a compare match by means of CCLRH in TCSRF When TCF overflows from H FFFF to H 0000 OVFH is set to 1 in TCSRF If OVIEH in TCSRF is 1 at this time IRRTFH is set to 1 in IRR2 and if IENTFH in IENR2 is 1 an interrupt request is sent to the CPU b 8 bit mode TCFL TCFH When ...

Page 204: ... are constantly compared with TCF and when both values match CMFH is set to 1 in TCSRF At the same time IRRTFH is set to 1 in IRR2 If IENTFH in IENR2 is 1 at this time an interrupt request is sent to the CPU Toggle output can be provided from the TMOFH pin by means of compare matches and the output level can be set high or low by means of TOLH in TCRF b 8 bit mode OCRFH OCRFL When CKSH2 is set to ...

Page 205: ...tten Bit 7 TOLH Description 0 Low level initial value 1 High level Bits 6 to 4 Clock select H CKSH2 to CKSH0 Bits 6 to 4 select the clock input to TCFH from among four internal clock sources or TCFL overflow Bit 6 Bit 5 Bit 4 CKSH2 CKSH1 CKSH0 Description 0 0 0 16 bit mode counting on TCFL overflow signal initial value 0 0 1 0 1 0 0 1 1 Use prohibited 1 0 0 Internal clock counting on ø 32 1 0 1 In...

Page 206: ...tion 0 0 0 Counting on external event TMIF rising initial value 0 0 1 falling edge 0 1 0 0 1 1 Use prohibited 1 0 0 Internal clock counting on ø 32 1 0 1 Internal clock counting on ø 16 1 1 0 Internal clock counting on ø 4 1 1 1 Internal clock counting on øw 4 Note External event edge selection is set by IEG3 in the IRQ edge select register IEGR For details see 1 IRQ edge select register IEGR in s...

Page 207: ...t by hardware and cleared by software It cannot be set by software Bit 7 OVFH Description 0 Clearing conditions initial value After reading OVFH 1 cleared by writing 0 to OVFH 1 Setting conditions Set when TCFH overflows from H FF to H 00 Bit 6 Compare match flag H CMFH Bit 6 is a status flag indicating that TCFH has matched OCRFH This flag is set by hardware and cleared by software It cannot be s...

Page 208: ...CRFH match Bit 4 CCLRH Description 0 16 bit mode TCF clearing by compare match is disabled 8 bit mode TCFH clearing by compare match is disabled initial value 1 16 bit mode TCF clearing by compare match is enabled 8 bit mode TCFH clearing by compare match is enabled Bit 3 Timer overflow flag L OVFL Bit 3 is a status flag indicating that TCFL has overflowed from H FF to H 00 This flag is set by har...

Page 209: ...hen the TCFL value matches the OCRFL value Bit 1 Timer overflow interrupt enable L OVIEL Bit 1 selects enabling or disabling of interrupt generation when TCFL overflows Bit 1 OVIEL Description 0 TCFL overflow interrupt request is disabled initial value 1 TCFL overflow interrupt request is enabled Bit 0 Counter clear L CCLRL Bit 0 selects whether TCFL is cleared when TCFL and OCRFL match Bit 0 CCLR...

Page 210: ...e the sections on the relevant modules Bit 2 Timer F module standby mode control TFCKSTP Bit 2 controls setting and clearing of module standby mode for timer F TFCKSTP Description 0 Timer F is set to module standby mode 1 Timer F module standby mode is cleared initial value TFCKSTP TCCKSTP TACKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W Bit...

Page 211: ...wo consecutive byte size MOV instructions and the upper byte must be accessed before the lower byte Data will not be transferred correctly if only the upper byte or only the lower byte is accessed In 8 bit mode there are no restrictions on the order of access 1 Write access Write access to the upper byte results in transfer of the upper byte write data to TEMP Next write access to the lower byte r...

Page 212: ...which H AA55 is written to TCF Figure 9 4 Write Access to TCR CPU TCF Write to upper byte CPU H AA TEMP H AA TCFH TCFL Bus interface Module data bus Write to lower byte CPU H 55 TEMP H AA TCFH H AA TCFL H 55 Bus interface Module data bus ...

Page 213: ... upper byte is read the upper byte data is transferred directly to the CPU When the lower byte is read the lower byte data is transferred directly to the CPU Figure 9 5 shows an example in which TCF is read when it contains H AAFF Figure 9 5 Read Access to TCF TCF CPU Read upper byte CPU H AA TEMP H FF TCFH H AA TCFL H FF Bus interface Module data bus Read lower byte CPU H FF TEMP H FF TCFH AB TCF...

Page 214: ...selected from four internal clocks output by prescaler S or an external clock by means of bits CKSL2 to CKSL0 in TCRF OCRF contents are constantly compared with TCF and when both values match CMFH is set to 1 in TCSRF If IENTFH in IENR2 is 1 at this time an interrupt request is sent to the CPU and at the same time TMOFH pin output is toggled If CCLRH in TCSRF is 1 TCF is cleared TMOFH pin output c...

Page 215: ... one of four internal clock sources ø 32 ø 16 ø 4 or øw 4 created by dividing the system clock ø or øw b External event operation External event input is selected by clearing CKSL2 to 0 in TCRF TCF can increment on either the rising or falling edge of external event input External event edge selection is set by IEG3 in the interrupt controller s IEGR register An external event pulse width of at le...

Page 216: ...g TCF can be cleared by a compare match with OCRF 5 Timer overflow flag OVF set timing OVF is set to 1 when TCF overflows from H FFFF to H 0000 6 Compare match flag set timing The compare match flag CMFH or CMFL is set to 1 when the TCF and OCRF values match The compare match signal is generated in the last state during which the values match when TCF ø TMIF when IEG3 1 Count input clock TCF OCRF ...

Page 217: ... Halted OCRF Reset Functions Held Held Functions Held Held Held TCRF Reset Functions Held Held Functions Held Held Held TCSRF Reset Functions Held Held Functions Held Held Held Note When øw 4 is selected as the TCF internal clock in active mode or sleep mode since the system clock and internal clock are mutually asynchronous synchronization is maintained by a synchronization circuit This results i...

Page 218: ... flag CMFL is set if the setting conditions for the lower 8 bits are satisfied When TCF overflows OVFH is set OVFL is set if the setting conditions are satisfied when the lower 8 bits overflow If a TCFL write and overflow signal output occur simultaneously the overflow signal is not output 2 8 bit timer mode a TCFH OCRFH In toggle output TMOFH pin output is toggled when a compare match occurs If a...

Page 219: ...d the counter value match a compare match signal will be generated at that point As the compare match signal is output in synchronization with the TCFL clock a compare match will not result in compare match signal generation if the clock is stopped If a TCFL write and overflow signal output occur simultaneously the overflow signal is not output ...

Page 220: ...functions for rising and falling edges Level detection at counter overflow It is possible to detect whether overflow occurred when the input capture input signal was high or when it was low Selection of whether or not the counter value is to be cleared at the input capture input signal rising edge falling edge or both edges Two interrupt sources one input capture one overflow The input capture inp...

Page 221: ...S TMG ICRGF TCG ICRGR Noise canceler Edge detector Level detector IRRTG ø øw 4 TMIG NCS Notation TMG TCG ICRGF ICRGR IRRTG NCS PSS Timer mode register G Timer counter G Input capture register GF Input capture register GR Timer G interrupt request flag Noise canceler select Prescaler S Internal data bus ...

Page 222: ...ure input pin 4 Register configuration Table 9 12 shows the register configuration of timer G Table 9 12 Timer G Registers Name Abbrev R W Initial Value Address Timer control register G TMG R W H 00 H FFBC Timer counter G TCG H 00 Input capture register GF ICRGF R H 00 H FFBD Input capture register GR ICRGR R H 00 H FFBE Clock stop register 1 CKSTPR1 R W H FF H FFFA ...

Page 223: ...he CPU It is initialized to H 00 upon reset Note An input capture signal may be generated when TMIG is modified 2 Input capture register GF ICRGF ICRGF is an 8 bit read only register When a falling edge of the input capture input signal is detected the current TCG value is transferred to ICRGF If IIEGS in TMG is 1 at this time IRRTG is set to 1 in IRR2 and if IENTG in IENR2 is 1 an interrupt reque...

Page 224: ...ICRGR is initialized to H 00 upon reset 4 Timer mode register G TMG TMG is an 8 bit read write register that performs TCG clock selection from four internal clock sources counter clear selection and edge selection for the input capture input signal interrupt request controls enabling of overflow interrupt requests and also contains the overflow flags TMG is initialized to H 00 upon reset OVFH CCLR...

Page 225: ...Bit 6 is a status flag indicating that TCG has overflowed from H FF to H 00 when the input capture input signal is low or in interval operation This flag is set by hardware and cleared by software It cannot be set by software Bit 6 OVFL Description 0 Clearing conditions initial value After reading OVFL 1 cleared by writing 0 to OVFL 1 Setting conditions Set when TCG overflows from H FF to H 00 Bit...

Page 226: ...alling edge or both edges of the input capture input signal Bit 3 Bit 2 CCLR1 CCLR0 Description 0 0 TCG clearing is disabled initial value 0 1 TCG cleared by falling edge of input capture input signal 1 0 TCG cleared by rising edge of input capture input signal 1 1 TCG cleared by both edges of input capture input signal Bits 1 and 0 Clock select CKS1 CKS0 Bits 1 and 0 select the clock input to TCG...

Page 227: ...e the sections on the relevant modules Bit 3 Timer G module standby mode control TGCKSTP Bit 3 controls setting and clearing of module standby mode for timer G TGCKSTP Description 0 Timer G is set to module standby mode 1 Timer G module standby mode is cleared initial value TFCKSTP TCCKSTP TACKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W Bit...

Page 228: ...data is judged to be correct when all the latch outputs match If all the outputs do not match the previous value is retained After a reset the noise canceler output is initialized when the falling edge of the input capture input signal has been sampled five times Therefore after making a setting for use of the noise cancellation function a pulse with at least five times the width of the sampling c...

Page 229: ...t of less than five times the width of the sampling clock at the input capture input pin is eliminated as noise Figure 9 9 Noise Canceler Timing Example Input capture input signal Sampling clock Noise canceler output Eliminated as noise ...

Page 230: ...GR ICRGF When the edge selected by IIEGS in TMG is input IRRTG is set to 1 in IRR2 and if the IENTG bit in IENR2 is 1 at this time an interrupt request is sent to the CPU For details of the interrupt see 3 3 Interrupts TCG can be cleared by a rising edge falling edge or both edges of the input capture signal according to the setting of bits CCLR1 and CCLR0 in TMG If TCG overflows when the input ca...

Page 231: ...ernal clock sources ø 64 ø 32 ø 2 or øw 4 created by dividing the system clock ø or watch clock øw 3 Input capture input timing a Without noise cancellation function For input capture input dedicated input capture functions are provided for rising and falling edges Figure 9 10 shows the timing for rising falling edge input capture input Figure 9 10 Input Capture Input Timing without Noise Cancella...

Page 232: ... by input capture input Figure 9 12 shows the timing of input capture by input capture input Figure 9 10 Timing of Input Capture by Input Capture Input Input capture signal TCG N 1 N N H XX N 1 Input capture register Input capture input signal Sampling clock Noise canceler output Input capture signal R ...

Page 233: ...ons Functions Halted Halted halted halted halted Interval Reset Functions Functions Functions Functions Functions Halted Halted halted halted halted ICRGF Reset Functions Functions Functions Functions Functions Held Held halted halted halted ICRGR Reset Functions Functions Functions Functions Functions Held Held halted halted halted TMG Reset Functions Held Held Functions Held Held Held Note When ...

Page 234: ...nother internal clock is selected and when another sub clock øw 8 øw 4 is selected TCG and noise canceler do not operate 9 5 5 Application Notes 1 Internal clock switching and TCG operation Depending on the timing TCG may be incremented by a switch between difference internal clock sources Table 9 14 shows the relation between internal clock switchover timing by write to bits CKS1 and CKS0 and TCG...

Page 235: ...low level 2 Goes from low level to high level 3 Goes from high level to low level TCG N N 1 N 2 Clock before switching Clock before switching Count clock Write to CKS1 and CKS0 Clock before switching Clock before switching Count clock TCG N N 1 N 2 Write to CKS1 and CKS0 Clock before switching Clock after switching Count clock TCG N N 1 Write to CKS1 and CKS0 ...

Page 236: ...ch the input capture function or the input capture input noise canceler function Switching input capture input pin function Note that when the pin function is switched by modifying TMIG in port mode register 1 PMR1 which performs input capture input pin control an edge will be regarded as having been input at the pin even though no valid edge has actually been input Input capture input signal inpu...

Page 237: ...input capture input noise canceler TMIG should first be cleared to 0 Note that if NCS is modified without first clearing TMIG an edge will be regarded as having been input at the pin even though no valid edge has actually been input Input capture input signal input edges and the conditions for their occurrence are summarized in table 9 16 Table 9 16 Input Capture Input Signal Input Edges Due to No...

Page 238: ... the IIEGS bit in TMG Figure 9 14 Port Mode Register Manipulation and Interrupt Enable Flag Clearing Procedure 9 5 6 Timer G Application Example Using timer G it is possible to measure the high and low widths of the input capture input signal as absolute values For this purpose CCLR1 and CCLR0 should both be set to 1 in TMG Figure 9 15 shows an example of the operation in this case Set I bit to 1 ...

Page 239: ...231 Figure 9 15 Timer G Application Example Counter cleared TCG H FF H 00 Input capture input signal Input capture register GF Input capture register GR ...

Page 240: ...w 32 A reset signal is generated when the counter overflows The overflow period can be set from from 1 to 256 times 8192 ø or 32 øw from approximately 4 ms to 1000 ms when ø 2 00 MHz Use of module standby mode enables this module to be placed in standby mode independently when not used 2 Block diagram Figure 9 16 shows a block diagram of the watchdog timer Figure 9 16 Block Diagram of Watchdog Tim...

Page 241: ...bit read write register that controls write access to TCW and TCSRW itself controls watchdog timer operations and indicates operating status Bit 7 Bit 6 write inhibit B6WI Bit 7 controls the writing of data to bit 6 in TCSRW Bit 7 B6WI Description 0 Bit 6 is write enabled 1 Bit 6 is write protected initial value This bit is always read as 1 Data written to this bit is not stored Bit Initial value ...

Page 242: ...alue This bit is always read as 1 Data written to this bit is not stored Bit 4 Timer control status register W write enable TCSRWE Bit 4 controls the writing of data to TCSRW bits 2 and 0 Bit 4 TCSRWE Description 0 Data cannot be written to bits 2 and 0 initial value 1 Data can be written to bits 2 and 0 Bit 3 Bit 2 write inhibit B2WI Bit 3 controls the writing of data to bit 2 in TCSRW Bit 3 B2WI...

Page 243: ... 1 controls the writing of data to bit 0 in TCSRW Bit 1 B0WI Description 0 Bit 0 is write enabled 1 Bit 0 is write protected initial value This bit is always read as 1 Data written to this bit is not stored Bit 0 Watchdog timer reset WRST Bit 0 indicates that TCW has overflowed generating an internal reset signal The internal reset signal generated by the overflow resets the entire chip WRST is cl...

Page 244: ...nd clearing of module standby mode for the watchdog timer WDCKSTP Description 0 Watchdog timer is set to module standby mode 1 Watchdog timer module standby mode is cleared initial value Note WDCKSTP is valid when the WDON bit is cleared to 0 in timer control status register W TCSRW If WDCKSTP is set to 0 while WDON is set to 1 during watchdog timer operation 0 will be set in WDCKSTP but the watch...

Page 245: ... cleared to 0 and øw 32 when set to 1 When TCSRWE 1 in TCSRW if 0 is written in B2WI and 1 is simultaneously written in WDON TCW starts counting up When the TCW count reaches H FF the next clock input causes the watchdog timer to overflow and an internal reset signal is generated one reference clock ø or øSUB cycle later The internal reset signal is output for 512 clock cycles of the øOSC clock It...

Page 246: ...Mode Reset Active Sleep Watch active sleep Standby Standby TCW Reset Functions Functions Halted Functions Halted Halted Halted Halted TCSRW Reset Functions Functions Retained Functions Retained Retained Retained Halted Note Functions when øw 32 is selected as the input clock H F8 TCW overflow Start H F8 written in TCW H F8 written in TCW Reset Internal reset signal 512 øOSC clock cycles H FF H 00 ...

Page 247: ...ously without regard to the operation of base clocks ø and øSUB The counter has a 16 bit configuration enabling it to count up to 65536 216 events Can also be used as two independent 8 bit event counter channels Counter resetting and halting of the count up function controllable by software Automatic interrupt generation on detection of event counter overflow Use of module standby mode enables thi...

Page 248: ...ram of Asynchronous Event Counter ECCSR ECH ECL IRREC Internal data bus OVL OVH CK CK AEVL AEVH Event counter control status register Event counter H Event counter L Asynchronous event input H Asynchronous event input L Event counter overflow interrupt request flag Notation ECCSR ECH ECL AEVH AEVL IRREC 240 ...

Page 249: ... FF96 Event counter L ECL R H 00 H FF97 Clock stop register 2 CKSTP2 R W H FF H FFFB 9 7 2 Register Descriptions 1 Event counter control status register ECCSR ECCSR is an 8 bit read write register that controls counter overflow detection counter resetting and halting of the count up function ECCSR is initialized to H 00 upon reset Bit 7 Counter overflow flag H OVH Bit 7 is a status flag indicating...

Page 250: ...wed initial value Clearing conditions After reading OVL 1 cleared by writing 0 to OVL 1 ECL has overflowed Setting conditions Set when ECL overflows from H FF to H 00 while CH2 is set to 1 Bit 5 Reserved bit Bit 5 is reserved it can be read and written and is initialized to 0 upon reset Bit 4 Channel select CH2 Bit 4 selects whether ECH and ECL are used as a single channel 16 bit event counter or ...

Page 251: ... disabled initial value ECH value is held 1 ECH event clock input is enabled Bit 2 Count up enable L CUEL Bit 3 enables event clock input to ECL When 1 is written to this bit event clock input is enabled and increments the counter When 0 is written to this bit event clock input is disabled and the ECL value is held Bit 2 CUEL Description 0 ECL event clock input is disabled initial value ECL value ...

Page 252: ...ignal from lower 8 bit counter ECL can be selected as the input clock source by bit CH2 ECH can be cleared to H 00 by software and is also initialized to H 00 upon reset 3 Event counter L ECL ECL is an 8 bit read only up counter that operates either as an independent 8 bit event counter or as the lower 8 bit up counter of a 16 bit event counter configured in combination with ECH The event clock fr...

Page 253: ...ons on the relevant modules Bit 3 Asynchronous event counter module standby mode control AECKSTP Bit 3 controls setting and clearing of module standby mode for the asynchronous event counter AECKSTP Description 0 Asynchronous event counter is set to module standby mode 1 Asynchronous event counter module standby mode is cleared initial value WDCKSTP PWCKSTP LDCKSTP AECKSTP 7 6 5 4 3 2 1 0 1 1 1 1 ...

Page 254: ...ce is asynchronous event input from the AEVL pin When the next clock is input after the count value reaches H FF in both ECH and ECL ECH and ECL overflow from H FFFF to H 0000 the OVH flag is set to 1 in ECCSR the ECH and ECL count values each return to H 00 and counting up is restarted When overflow occurs the IRREC bit is set to 1 in IRR2 If the IENEC bit in IENR2 is 1 at this time an interrupt ...

Page 255: ...lue returns to H 00 and counting up is restarted When overflow occurs the IRREC bit is set to 1 in IRR2 If the IENEC bit in IENR2 is 1 at this time an interrupt request is sent to the CPU 9 7 4 Asynchronous Event Counter Operation Modes Asynchronous event counter operation modes are shown in table 9 21 Table 9 21 Asynchronous Event Counter Operation Modes Operation Module Mode Reset Active Sleep W...

Page 256: ...f the clock are at least 83 ns The duty cycle is immaterial Maximum AEVH AEVL Pin Mode Input Clock Frequency 16 bit mode Internal step down circuit 8 bit mode Active high speed sleep high speed not used VCC 4 5 to 5 5 V 6 MHz VCC 3 0 to 5 5 V 4 MHz VCC 2 6 to 5 5 V 3 2 MHz VCC 2 2 to 5 5 V 2 MHz Other than above 1 MHz Internal step down circuit used VCC 2 2 to 5 5 V 2 MHz Other than above 1 MHz 8 ...

Page 257: ...onous mode for serial data communication Asynchronous mode Serial data communication is performed asynchronously with synchronization provided character by character In this mode serial data can be exchanged with standard asynchronous communication LSIs such as a Universal Asynchronous Receiver Transmitter UART or Asynchronous Communication Interface Adapter ACIA A multiprocessor communication fun...

Page 258: ... and reception units are provided enabling transmission and reception to be carried out simultaneously The transmission and reception units are both double buffered allowing continuous transmission and reception On chip baud rate generator allowing any desired bit rate to be selected Choice of an internal or external clock as the transmit receive clock source Six interrupt sources transmit end tra...

Page 259: ...ta bus Notation RSR RDR TSR TDR SMR SCR3 SSR BRR BRC SPCR Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register 3 Serial status register Bit rate register Bit rate counter Serial port control register Interrupt request TEI TXI RXI ERI 3x Internal clock ø 64 ø 16 øw 2 ø External clock BRC Baud rate generator 251 ...

Page 260: ...egister 3 SCR3 R W H 00 H FFAA FF9A Transmit data register TDR R W H FF H FFAB FF9B Serial data register SSR R W H 84 H FFAC FF9C Receive data register RDR R H 00 H FFAD FF9D Transmit shift register TSR Protected Receive shift register RSR Protected Bit rate counter BRC Protected Clock stop register 1 CKSTPR1 R W H FF H FFFA Serial port control register SPCR R W H C0 H FF91 10 2 Register Descripti...

Page 261: ...e 10 2 3 Transmit shift register TSR TSR is a register used to transmit serial data Transmit data is first transferred from TDR to TSR and serial data transmission is carried out by sending the data to the TXD3x pin in order starting from the LSB bit 0 When one byte of data is transmitted the next byte of transmit data is transferred to TDR and transmission started automatically Data transfer from...

Page 262: ...an 8 bit register used to set the serial data transfer format and to select the clock source for the baud rate generator SMR can be read or written by the CPU at any time SMR is initialized to H 00 upon reset and in standby module standby or watch mode Bit 7 Communication mode COM Bit 7 selects whether SCI3 operates in asynchronous mode or synchronous mode Bit 7 COM Description 0 Asynchronous mode...

Page 263: ...ore it is sent and the received parity bit is checked against the parity designated by bit PM 2 For the case where 5 bit data is selected see table 10 11 Bit 4 Parity mode PM Bit 4 selects whether even or odd parity is to be used for parity addition and checking The PM bit setting is only valid in asynchronous mode when bit PE is set to 1 enabling parity bit addition and checking The PM bit settin...

Page 264: ...n function is disabled the parity settings in the PE and PM bits are invalid The MP bit setting is only valid in asynchronous mode When synchronous mode is selected the MP bit should be set to 0 For details on the multiprocessor communication function see 10 1 6 Multiprocessor Communication Function Bit 2 MP Description 0 Multiprocessor communication function disabled initial value 1 Multiprocesso...

Page 265: ... interrupt request TXI disabled initial value 1 Transmit data empty interrupt request TXI enabled Bit 6 Receive interrupt enable RIE Bit 6 selects enabling or disabling of the receive data full interrupt request RXI and the receive error interrupt request ERI when receive data is transferred from the receive shift register RSR to the receive data register RDR and bit RDRF in the serial status regi...

Page 266: ...cted in synchronous mode Be sure to carry out serial mode register SMR settings to decide the reception format before setting bit RE to 1 Bit 3 Multiprocessor interrupt enable MPIE Bit 3 selects enabling or disabling of the multiprocessor interrupt request The MPIE bit setting is only valid when asynchronous mode is selected and reception is carried out with bit MP in SMR set to 1 The MPIE bit set...

Page 267: ... input pin The CKE0 bit setting is only valid in case of internal clock operation CKE1 0 in asynchronous mode In synchronous mode or when external clock operation is used CKE1 1 bit CKE0 should be cleared to 0 After setting bits CKE1 and CKE0 set the operating mode in the serial mode register SMR For details on clock source selection see table 10 4 in 10 1 3 Operation Bit 1 Bit 0 Description CKE1 ...

Page 268: ...standby module standby or watch mode Bit 7 Transmit data register empty TDRE Bit 7 indicates that transmit data has been transferred from TDR to TSR Bit 7 TDRE Description 0 Transmit data written in TDR has not been transferred to TSR Clearing conditions After reading TDRE 1 cleared by writing 0 to TDRE When data is written to TDR by an instruction 1 Transmit data has not been written to TDR or tr...

Page 269: ...ompleted while bit RDRF is still set to 1 an overrun error OER will result and the receive data will be lost Bit 5 Overrun error OER Bit 5 indicates that an overrun error has occurred during reception Bit 5 OER Description 0 Reception in progress or completed 1 initial value Clearing conditions After reading OER 1 cleared by writing 0 to OER 1 An overrun error has occurred during reception 2 Setti...

Page 270: ...n cannot be continued with bit FER set to 1 In synchronous mode neither transmission nor reception is possible when bit FER is set to 1 Bit 3 Parity error PER Bit 3 indicates that a parity error has occurred during reception with parity added in asynchronous mode Bit 3 PER Description 0 Reception in progress or completed 1 initial value Clearing conditions After reading PER 1 cleared by writing 0 ...

Page 271: ...g multiprocessor format reception in asynchronous mode Bit 1 is a read only bit and cannot be modified Bit 1 MPBR Description 0 Data in which the multiprocessor bit is 0 has been received initial value 1 Data in which the multiprocessor bit is 1 has been received Note When bit RE is cleared to 0 in SCR3 with the multiprocessor format bit MPBR is not affected and retains its previous state Bit 0 Mu...

Page 272: ...le 10 3 Examples of BRR Settings for Various Bit Rates Asynchronous Mode 1 OSC 32 8 kHz 38 4 kHz 2 MHz 2 4576 MHz 4 MHz B Bit Rate Error Error Error Error Error bit s n N n N n N n N n N 110 Cannot be used 2 21 0 83 150 as error exceeds 0 3 0 2 12 0 16 3 3 0 2 25 0 16 200 3 0 2 0 0 155 0 16 3 2 0 250 0 124 0 0 153 0 26 0 249 0 300 0 1 0 0 103 0 16 3 1 0 2 12 0 16 600 0 0 0 0 51 0 16 3 0 0 0 103 0 ...

Page 273: ...error in table 10 3 is the value obtained from the following equation rounded to two decimal places Error B rate obtained from n N OSC R bit rate in left hand column in table 10 3 100 R bit rate in left hand column in table 10 3 Table 10 4 Relation between n and Clock SMR Setting n Clock CKS1 CKS0 0 ø 0 0 0 øw 2 1 øw 2 0 1 2 ø 16 1 0 3 ø 64 1 1 Notes 1 ø w 2 clock in active medium speed high speed...

Page 274: ... Table 10 6 shows examples of BRR settings in synchronous mode The values shown are for active high speed mode Table 10 6 Examples of BRR Settings for Various Bit Rates Synchronous Mode OSC B Bit Rate 38 4 kHz 2 MHz 4 MHz bit s n N Error n N Error n N Error 200 0 23 0 250 2 124 0 300 2 0 0 500 1k 0 249 0 2 5k 0 99 0 0 199 0 5k 0 49 0 0 99 0 10k 0 24 0 0 49 0 25k 0 9 0 0 19 0 50k 0 4 0 0 9 0 100k 0...

Page 275: ...umber n 0 2 or 3 The relation between n and the clock is shown in table 10 7 Table 10 7 Relation between n and Clock SMR Setting n Clock CKS1 CKS0 0 ø 0 0 0 øw 2 1 øw 2 0 1 2 ø 16 1 0 3 ø 64 1 1 Notes 1 ø w 2 clock in active medium speed high speed mode and sleep mode 2 ø w clock in subactive mode and subsleep mode 3 In subactive or subsleep mode SCI3 can be operated when CPU clock is øw 2 only 26...

Page 276: ...0 SCI3 1 is set to module standby mode 1 SCI3 1 module standby mode is cleared initial value Note All SCI31 register is initialized in module standby mode Bit 5 SCI3 2 module standby mode control S32CKSTP Bit 5 controls setting and clearing of module standby mode for SCI32 S32CKSTP Description 0 SCI3 2 is set to module standby mode 1 SCI3 2 module standby mode is cleared initial value Note All SCI...

Page 277: ... RXD31 input data is inverted Bit 1 TXD31 pin output data inversion switch Bit 1 specifies whether or not TXD31 pin output data is to be inverted Bit 1 SCINV1 Description 0 TXD31 output data is not inverted initial value 1 TXD31 output data is inverted Bit 2 RXD32 pin input data inversion switch Bit 2 specifies whether or not RXD32 pin input data is to be inverted Bit 2 SCINV2 Description 0 RXD32 ...

Page 278: ...s TXD31 Bit 4 SPC31 Description 0 Functions as P35 I O pin initial value 1 Functions as TXD31 output pin Note Set the TE bit in SCR3 after setting this bit to 1 Bit 5 P42 TXD32 pin function switch SPC32 This bit selects whether pin P42 TXD32 is used as P42 or as TXD32 Bit 5 SPC32 Description 0 Functions as P42 I O pin initial value 1 Functions as TXD32 output pin Note Set the TE bit in SCR3 after ...

Page 279: ...data transfer format and the character length Framing error FER parity error PER overrun error OER and break detection during reception Choice of internal or external clock as the clock source When internal clock is selected SCI3 operates on the baud rate generator clock and a clock with the same frequency as the bit rate can be output When external clock is selected A clock with a frequency 16 ti...

Page 280: ... 1 2 bits 1 0 0 7 bit data Yes 1 bit 1 2 bits 1 0 5 bit data No Yes 1 bit 1 2 bits 1 0 Synchronous 8 bit data No No No mode Don t care Table 10 9 SMR and SCR3 Settings and Clock Source Selection SMR SCR3 bit 7 bit 1 bit 0 Transmit Receive Clock COM CKE1 CKE0 Mode Clock Source SCK3x Pin Function 0 0 0 Asynchronous Internal I O port SCK3x pin not used 1 mode Outputs clock with same frequency as bit ...

Page 281: ...ext RSR data is completed See figure 10 2 a TXI TDRE When TSR is found to be empty The TXI interrupt routine writes the next TIE on completion of the previous transmit data to TDR and clears bit TDRE transmission and the transmit data to 0 Continuous transmission can be placed in TDR is transferred to TSR performed by repeating the above bit TDRE is set to 1 If bit TIE is set operations until the ...

Page 282: ...ess TEND 0 TXD3x pin TDR TSR reception completed TEND 1 TEI request when TEIE 1 TXD3x pin TDR next transmit data TSR transmission in progress TDRE 0 TXD3x pin TDR TSR transmission completed transfer TDRE 1 TXI request when TIE 1 TXD3x pin RDR RSR reception in progress RDRF 0 RXD3x pin RDR RSR reception completed transfer RDRF 1 RXI request when RIE 1 RXD3x pin 274 ...

Page 283: ...onous Communication In asynchronous communication the communication line is normally in the mark state high level SCI3 monitors the communication line and when it detects a space low level identifies this as a start bit and begins serial data communication One transfer data character consists of a start bit low level followed by transmit receive data LSB first format starting from the least signif...

Page 284: ...0 0 0 1 1 1 1 PE MP STOP 2 3 4 5 8 bit data Serial Data Transfer Format and Frame Length SMR STOP S 6 7 8 9 10 11 12 8 bit data S 7 bit data STOP STOP S STOP 7 bit data S STOP STOP 5 bit data S STOP 5 bit data S STOP STOP 8 bit data P S STOP 8 bit data P S STOP STOP 8 bit data MPB S STOP 8 bit data MPB S STOP STOP 7 bit data P STOP S STOP 7 bit data STOP S 5 bit data STOP P P P S 5 bit data STOP S...

Page 285: ...igure 10 4 Phase Relationship between Output Clock and Transfer Data Asynchronous Mode 8 bit data parity 2 stop bits 3 Data transfer operations SCI3 initialization Before data is transferred on SCI3 bits TE and RE in SCR3 must first be cleared to 0 and then SCI3 must be initialized as follows Note If the operation mode or data transfer format is changed bits TE and RE must first be cleared to 0 Wh...

Page 286: ... mode the clock is output immediately after setting bits CKE1 and CKE0 If clock output is selected for reception in synchronous mode the clock is output immediately after bits CKE1 CKE0 and RE are set to 1 Set the data transfer format in the serial mode register SMR Write the value corresponding to the transfer rate in BRR This operation is not necessary when an external clock is selected Wait for...

Page 287: ...1 No Yes Yes Yes No Break output Read the serial status register SSR and check that bit TDRE is set to 1 then write transmit data to the transmit data register TDR When data is written to TDR bit TDRE is cleared to 0 automatically After the TE bit is set to 1 one frame of 1s is output then transmission is possible When continuing data transmission be sure to read TDRE 1 to confirm that a write can...

Page 288: ...p bit has been sent starts transmission of the next frame If bit TDRE is set to 1 bit TEND in SSR bit is set to 1the mark state in which 1s are transmitted is established after the stop bit has been sent If bit TEIE in SCR3 is set to 1 at this time a TEI request is made Figure 10 12 shows an example of the operation when transmitting in asynchronous mode Figure 10 7 Example of Operation when Trans...

Page 289: ... 1 Yes Continue data reception No No Yes Receive error processing A Read bits OER PER and FER in the serial status register SSR to determine if there is an error If a receive error has occurred execute receive error processing Read SSR and check that bit RDRF is set to 1 If it is read the receive data in RDR When the RDR data is read bit RDRF is cleared to 0 automatically When continuing data rece...

Page 290: ...rrun error processing Framing error processing A Parity error processing If a receive error has occurred read bits OER PER and FER in SSR to identify the error and after carrying out the necessary error processing ensure that bits OER PER and FER are all cleared to 0 Reception cannot be resumed if any of these bits is set to 1 In the case of a framing error a break can be detected by reading the v...

Page 291: ...stored in RDR If bit RIE is set to 1 in SCR3 an RXI interrupt is requested If the error checks identify a receive error bit OER PER or FER is set to 1 depending on the kind of error Bit RDRF retains its state prior to receiving the data If bit RIE is set to 1 in SCR3 an ERI interrupt is requested Table 10 12 shows the conditions for detecting a receive error and receive data processing Note No fur...

Page 292: ...eception units allowing full duplex communication with a shared clock As the transmission and reception units are both double buffered data can be written during transmission and read during reception making possible continuous transmission and reception 1 frame Start bit Start bit Receive data Receive data Parity bit Stop bit Parity bit Stop bit Mark state idle state 1 frame 0 1 D0 D1 D7 0 1 1 0 ...

Page 293: ...rmat uses a fixed 8 bit data length Parity and multiprocessor bits cannot be added 2 Clock Either an internal clock generated by the baud rate generator or an external clock input at the SCK3x pin can be selected as the SCI3 serial clock The selection is made by means of bit COM in SMR and bits CKE1 and CKE0 in SCR3 See table 10 9 for details on clock source selection When SCI3 operates on an inte...

Page 294: ... 2 Write transmit data to TDR Read bit TEND in SSR Clear bit TE to 0 in SCR3 No TDRE 1 Yes Continue data transmission No TEND 1 Yes Yes No Read the serial status register SSR and check that bit TDRE is set to 1 then write transmit data to the transmit data register TDR When data is written to TDR bit TDRE is cleared to 0 automatically the clock is output and data transmission is started When clock...

Page 295: ...a from TDR to TSR and starts transmission of the next frame If bit TDRE is set to 1 SCI3 sets bit TEND to 1 in SSR and after sending the MSB bit 7 retains the MSB state If bit TEIE in SCR3 is set to 1 at this time a TEI request is made After transmission ends the SCK pin is fixed at the high level Note Transmission is not possible if an error flag OER FER or PER that indicates the data reception s...

Page 296: ...g Start overrun error processing Read bit OER in the serial status register SSR to determine if there is an error If an overrun error has occurred execute overrun error processing Read SSR and check that bit RDRF is set to 1 If it is read the receive data in RDR When the RDR data is read bit RDRF is cleared to 0 automatically When continuing data reception finish reading of bit RDRF and RDR before...

Page 297: ... set to 1 Bit RDRF remains set to 1 If bit RIE is set to 1 in SCR3 an ERI interrupt is requested See table 10 12 for the conditions for detecting a receive error and receive data processing Note No further receive operations are possible while a receive error flag is set Bits OER FER PER and RDRF must therefore be cleared to 0 before resuming reception Figure 10 14 shows an example of the operatio...

Page 298: ...mit data to the transmit data register TDR When data is written to TDR bit TDRE is cleared to 0 automatically Read SSR and check that bit RDRF is set to 1 If it is read the receive data in RDR When the RDR data is read bit RDRF is cleared to 0 automatically When continuing data transmission reception finish reading of bit RDRF and RDR before receiving the MSB bit 7 of the current frame Before rece...

Page 299: ...is assigned its own ID code The serial communication cycle consists of two cycles an ID transmission cycle in which the receiver is specified and a data transmission cycle in which the transfer data is sent to the specified receiver These two cycles are differentiated by means of the multiprocessor bit 1 indicating an ID transmission cycle and 0 a data transmission cycle The sender first sends tra...

Page 300: ...munication see 10 1 4 Operation in Synchronous Mode Multiprocessor transmitting Figure 10 17 shows an example of a flowchart for multiprocessor data transmission This procedure should be followed for multiprocessor data transmission after initializing SCI3 Sender Serial data Receiver A ID 01 ID 02 Receiver B H 01 ID transmission cycle specifying the receiver Data transmission cycle sending data to...

Page 301: ...ial status register SSR and check that bit TDRE is set to 1 then set bit MPBT in SSR to 0 or 1 and write transmit data to the transmit data register TDR When data is written to TDR bit TDRE is cleared to 0 automatically When continuing data transmission be sure to read TDRE 1 to confirm that a write can be performed before writing data to TDR When data is written to TDR bit TDRE is cleared to 0 au...

Page 302: ... to 1 the mark state in which 1s are transmitted is established after the stop bit has been sent If bit TEIE in SCR3 is set to 1 at this time a TEI request is made Figure 10 18 shows an example of the operation when transmitting using the multiprocessor format Figure 10 18 Example of Operation when Transmitting using Multiprocessor Format 8 bit data multiprocessor bit 1 stop bit Multiprocessor rec...

Page 303: ...or If a receive error has occurred execute receive error processing Read SSR and check that bit RDRF is set to 1 If it is read the receive data in RDR and compare it with this receiver s own ID If the ID is not this receiver s set bit MPIE to 1 again When the RDR data is read bit RDRF is cleared to 0 automatically Read SSR and check that bit RDRF is set to 1 then read the data in RDR If a receive ...

Page 304: ...re 10 20 shows an example of the operation when receiving using the multiprocessor format Start receive error processing End of receive error processing Clear bits OER and FER to 0 in SSR Yes OER 1 Yes Yes FER 1 Break No No No Overrun error processing Framing error processing A ...

Page 305: ...request RDR retains previous state RDR data read When data is not this receiver s ID bit MPIE is set to 1 again 1 frame Start bit Start bit Receive data ID2 Receive data Data2 MPB MPB Stop bit Stop bit Mark state idle state 1 frame 0 1 D0 D1 D7 1 1 1 1 0 a When data does not match this receiver s ID b When data matches this receiver s ID D0 D1 D7 ID2 Data2 ID1 0 Serial data MPIE RDRF LSI operation...

Page 306: ...l value of bit TDRE in SSR is 1 Therefore if the transmit data empty interrupt request TXI is enabled by setting bit TIE to 1 in SCR3 before transmit data is transferred to TDR a TXI interrupt will be requested even if the transmit data is not ready Also the initial value of bit TEND in SSR is 1 Therefore if the transmit end interrupt request TEI is enabled by setting bit TEIE to 1 in SCR3 before ...

Page 307: ...eration when a number of receive errors occur simultaneously If a number of receive errors are detected simultaneously the status flags in SSR will be set to the states shown in table 10 14 If an overrun error is detected data transfer from RSR to RDR will not be performed and the receive data will be lost Table 10 14 SSR Status Flag States and Receive Data Transfer SSR Status Flags Receive Data T...

Page 308: ...tions as an I O port and 1 is output To detect a break clear bit TE to 0 after setting PCR 1 and PDR 0 When bit TE is cleared to 0 the transmission unit is initialized regardless of the current transmission state the TXD3x pin functions as an I O port and 0 is output from the TXD3x pin 5 Receive error flags and transmit operation synchronous mode only When a receive error flag OER PER or FER is se...

Page 309: ...e value of clock frequency deviation Substituting 0 for F absolute value of clock frequency deviation and 0 5 for D clock duty in equation 1 a receive margin of 46 875 is given by equation 2 When D 0 5 and F 0 M 0 5 1 2 16 100 46 875 Equation 2 However this is only a computed value and a margin of 20 to 30 should be allowed when carrying out system design 0 7 15 0 7 15 0 Internal basic clock Recei...

Page 310: ...ween RDR Read Timing and Data In this case only a single RDR read operation not two or more should be performed after first checking that bit RDRF is set to 1 If two or more reads are performed the data read the first time should be transferred to RAM etc and the RAM contents used Also ensure that there is sufficient margin in an RDR read operation before reception of the next frame is completed T...

Page 311: ...ould be left 1 The above prevents SCK3 from being used as a general input output pin To avoid an intermediate level of voltage from being applied to SCK3 the line connected to SCK3 should be pulled up to the VCC level via a resistor or supplied with output from an external device b When an SCK3 function is switched from clock output to general input output When stopping data transfer i Issue one i...

Page 312: ...version periods can be chosen 131 072 ø with a minimum modulation width of 8 ø PWCR1 1 PWCR0 1 65 536 ø with a minimum modulation width of 4 ø PWCR1 1 PWCR0 0 32 768 ø with a minimum modulation width of 2 ø PWCR1 0 PWCR0 1 16 384 ø with a minimum modulation width of 1 ø PWCR1 0 PWCR0 0 Pulse division method for less ripple Use of module standby mode enables this module to be placed in standby mode...

Page 313: ...on Table 11 2 shows the register configuration of the 14 bit PWM Table 11 2 Register Configuration Name Abbrev R W Initial Value Address PWM control register PWCR W H FC H FFD0 PWM data register U PWDRU W H C0 H FFD1 PWM data register L PWDRL W H 00 H FFD2 Clock stop register 2 CKSTPR2 R W H FF H FFFB Internal data bus PWDRL PWDRU PWCR PWM waveform generator ø 2 ø 4 ø 8 ø 16 Notation PWDRL PWDRU P...

Page 314: ...lways read as 1 Bit 1 Bit 0 PWCR1 PWCR0 Description 0 0 The input clock is ø 2 tø 2 ø initial value The conversion period is 16 384 ø with a minimum modulation width of 1 ø 0 1 The input clock is ø 4 tø 4 ø The conversion period is 32 768 ø with a minimum modulation width of 2 ø 1 0 The input clock is ø 8 tø 8 ø The conversion period is 65 536 ø with a minimum modulation width of 4 ø 1 1 The input...

Page 315: ... PWDRL are write only registers If they are read all bits are read as 1 Upon reset PWDRU and PWDRL are initialized to H C000 11 2 3 Clock Stop Register 2 CKSTPR2 CKSTPR2 is an 8 bit read write register that performs module standby mode control for peripheral modules Only the bit relating to the PWM is described here For details of the other bits see the sections on the relevant modules WDCKSTP PWC...

Page 316: ... module standby mode control PWCKSTP Bit 1 controls setting and clearing of module standby mode for the PWM PWCKSTP Description 0 PWM is set to module standby mode 1 PWM module standby mode is cleared initial value ...

Page 317: ...nversion period consists of 64 pulses as shown in figure 11 2 The total of the high level pulse widths during this period TH corresponds to the data in PWDRU and PWDRL This relation can be represented as follows TH data value in PWDRU and PWDRL 64 tø 2 where tø is the PWM input clock period 2 ø PWCR H 0 4 ø PWCR H 1 8 ø PWCR H 2 or 16 ø PWCR H 3 Example Settings in order to obtain a conversion per...

Page 318: ...dule Mode Reset Active Sleep Watch Subactive Subsleep Standby Standby PWCR Reset Functions Functions Held Held Held Held Held PWDRU Reset Functions Functions Held Held Held Held Held PWDRL Reset Functions Functions Held Held Held Held Held 1 conversion period tf1 tf2 tf63 tf64 tH1 tH2 tH3 tH63 tH64 T t t t t t t H H1 H2 H3 H64 t f1 f2 f3 tf84 311 ...

Page 319: ...ed on completion of A D conversion A D conversion can be started by external trigger input Use of module standby mode enables this module to be placed in standby mode independently when not used 12 1 2 Block Diagram Figure 12 1 shows a block diagram of the A D converter Figure 12 1 Block Diagram of the A D Converter Internal data bus AMR ADSR ADRRH ADRRL Control logic Com parator AN AN AN AN AN AN...

Page 320: ...annel 3 Analog input 4 AN4 Input Analog input channel 4 Analog input 5 AN5 Input Analog input channel 5 Analog input 6 AN6 Input Analog input channel 6 Analog input 7 AN7 Input Analog input channel 7 External trigger input ADTRG Input External trigger input for starting A D conversion 12 1 4 Register Configuration Table 12 2 shows the A D converter register configuration Table 12 2 Register Config...

Page 321: ...n 8 bit read write register for specifying the A D conversion speed external trigger option and the analog input pins Upon reset AMR is initialized to H 30 Bit 7 Clock select CKS Bit 7 sets the A D conversion speed Bit 7 Conversion Time CKS Conversion Period ø 1 MHz ø 5 MHz 0 62 ø initial value 62 µs 31 µs 1 31 ø 31 µs 15 5 µs Note Operation is not guaranteed if the conversion time is less than 15...

Page 322: ...by bit INTEG4 of IEGR See 1 Interrupt edge select register IEGR in 3 3 2 for details Bits 5 and 4 Reserved bits Bits 5 and 4 are reserved they are always read as 1 and cannot be modified Bits 3 to 0 Channel select CH3 to CH0 Bits 3 to 0 select the analog input channel The channel selection should be made while bit ADSF is cleared to 0 Bit 3 Bit 2 Bit 1 Bit 0 CH3 CH2 CH1 CH0 Analog Input Channel 0 ...

Page 323: ...n initial value Write Stops A D conversion 1 Read Indicates A D conversion in progress Write Starts A D conversion Bits 6 to 0 Reserved bits Bits 6 to 0 are reserved they are always read as 1 and cannot be modified 12 2 4 Clock Stop Register 1 CKSTPR1 CKSTPR1 is an 8 bit read write register that performs module standby mode control for peripheral modules Only the bit relating to the A D converter ...

Page 324: ... controls setting and clearing of module standby mode for the A D converter ADCKSTP Description 0 A D converter is set to module standby mode 1 A D converter module standby mode is cleared initial value 318 ...

Page 325: ...ime or input channel needs to be changed in the A D mode register AMR during A D conversion bit ADSF should first be cleared to 0 stopping the conversion operation in order to avoid malfunction 12 3 2 Start of A D Conversion by External Trigger Input The A D converter can be made to start A D conversion by input of an external trigger signal External trigger input is enabled at pin ADTRG when bit ...

Page 326: ...Typical Use An example of how the A D converter can be used is given below using channel 1 pin AN1 as the analog input channel Figure 12 3 shows the operation timing 1 Bits CH3 to CH0 of the A D mode register AMR are set to 0101 making pin AN1 the analog input channel A D interrupts are enabled by setting bit IENAD to 1 and A D conversion is started by setting bit ADSF to 1 2 When A D conversion i...

Page 327: ...dle A D conversion 2 Idle Interrupt IRRAD IENAD ADSF Channel 1 AN 1 operation state ADRRH ADRRL Set Set Set Read conversion result Read conversion result A D conversion result 1 A D conversion result 2 A D conversion starts Note indicates instruction execution by software 321 ...

Page 328: ...e for Using A D Converter Polling by Software Start Set A D conversion speed and input channel Perform A D conversion End Yes No Disable A D conversion end interrupt Start A D conversion ADSF 0 No Yes Read ADSR Read ADRRH ADRRL data 322 ...

Page 329: ...al input signal at an adjacent pin during A D conversion may adversely affect conversion accuracy When A D conversion is started after clearing module standby mode wait for 10 ø clock cycles before starting Start Set A D conversion speed and input channels Enable A D conversion end interrupt Start A D conversion A D conversion end interrupt Yes No End Yes No Clear bit IRRAD to 0 in IRR2 Read ADRRH...

Page 330: ... LCD RAM capacity 8 bits 32 bytes 256 bits Word access to LCD RAM All eight segment output pins can be used individually as port pins Common output pins not used because of the duty cycle can be used for common double buffering parallel connection Display possible in operating modes other than standby mode Choice of 11 frame frequencies Built in power supply split resistance supplying LCD drive po...

Page 331: ...CR LCR LCR2 Display timing generator LCD RAM 32 bytes Internal data bus 32 bit shift register LCD drive power supply built in step up constant voltage circuit Segment driver Common data latch Common driver M V1 V2 V3 VSS COM1 COM4 SEG32 CL1 SEG31 CL2 SEG30 DO SEG29 M SEG28 SEG1 Notation LPCR LCD port control register LCR LCD control register LCR2 LCD control register 2 V0 ...

Page 332: ...ut Display data shift clock multiplexed as SEG31 M Output LCD alternation signal multiplexed as SEG29 DO Output Serial display data multiplexed as SEG30 LCD power supply pins V0 V1 V2 V3 Used when a bypass capacitor is connected externally and when an external power supply circuit is used 13 1 4 Register Configuration Table 13 2 shows the register configuration of the LCD controller driver Table 1...

Page 333: ...elect 1 and 0 DTS1 DTS0 common function select CMX The combination of DTS1 and DTS0 selects static 1 2 1 3 or 1 4 duty CMX specifies whether or not the same waveform is to be output from multiple pins to increase the common drive power when not all common pins are used because of the duty setting Bit Initial value Read Write 7 DTS1 0 R W 6 DTS0 0 R W 5 CMX 0 R W 4 SGX 0 R W 3 SGS3 0 R W 0 SGS0 0 R...

Page 334: ...and COM2 outputs the same waveform as COM1 1 0 0 1 3 duty COM3 to COM1 Do not use COM4 1 COM4 to COM1 Do not use COM4 1 1 0 1 4 duty COM4 to COM1 1 Bit 4 Expansion signal select SGX Bit 4 selects whether the SEG32 CL1 SEG31 CL2 SEG30 DO and SEG29 M pins are used as segment pins SEG32 to SEG29 or as segment external expansion pins CL1 CL2 DO M Bit 4 SGX Description 0 Pins SEG32 to SEG29 Initial val...

Page 335: ...t 0 SEG32 to SEG24 to SEG16 to SEG8 to SGX SGS3 SGS2 SGS1 SGS0 SEG25 SEG17 SEG9 SEG1 Notes 0 0 0 0 0 Port Port Port Port Initial value 0 0 0 1 Port Port Port Port 0 0 1 SEG Port Port Port 0 1 0 SEG SEG Port Port 0 1 1 SEG SEG SEG Port 1 SEG SEG SEG SEG 1 0 0 0 0 Port Port Port Port Setting prohibited Don t care Note SEG32 to SEG29 are external expansion pins ...

Page 336: ...ared to 0 or in standby mode the LCD drive power supply is turned off regardless of the setting of this bit Bit 6 PSW Description 0 LCD drive power supply off initial value 1 LCD drive power supply on Bit 5 Display function activate ACT Bit 5 specifies whether or not the LCD controller driver is used Clearing this bit to 0 halts operation of the LCD controller driver The LCD drive power supply is ...

Page 337: ...f the clocks from ø 2 to ø 256 is selected If LCD display is required in these modes øw øw 2 or øw 4 must be selected as the operating clock Bit 3 Bit 2 Bit 1 Bit 0 Frame Frequency 2 CKS3 CKS2 CKS1 CKS0 Operating Clock ø 2 MHz ø 250 kHz 1 0 0 0 øw 128 Hz 3 initial value 0 0 1 øw 2 64 Hz 3 0 1 øw 4 32 Hz 3 1 0 0 0 ø 2 244 Hz 1 0 0 1 ø 4 977 Hz 122 Hz 1 0 1 0 ø 8 488 Hz 61 Hz 1 0 1 1 ø 16 244 Hz 30 ...

Page 338: ...itial value 1 Drive using B waveform Bits 6 and 5 Reserved bits Bits 6 and 5 are reserved they are always read as 1 and cannot be modified Bit 4 Drive power supply select step up constant voltage 5 V power supply control SUPS Applies to the H8 3867 Series only When VCC is selected as the drive power supply the step up constant voltage 5 V power supply simultaneously stops operating when 5 V is sel...

Page 339: ...ply split resistance is connected to the power supply circuit When a 0 duty cycle is selected the power supply split resistance is permanently disconnected from the power supply circuit so power should be supplied to pins V1 V2 and V3 by an external circuit Figure 13 2 shows the waveform of the charge discharge pulses The duty cycle is Tc Tw Figure 13 2 Example of A Waveform with 1 2 Duty and 1 2 ...

Page 340: ...e the sections on the relevant modules Bit 0 LCD controller driver module standby mode control LDCKSTP Bit 0 controls setting and clearing of module standby mode for the LCD controller driver Bit 0 LDCKSTP Description 0 LCD controller driver is set to module standby mode 1 LCD controller driver module standby mode is cleared initial value Bit Initial value Read Write 7 1 6 1 5 1 4 1 3 AECKSTP 1 R ...

Page 341: ...e panel refer to section 13 3 7 Boosting the LCD Drive Power Supply When static or 1 2 duty is selected the common output drive capability can be increased Set CMX to 1 when selecting the duty cycle In this mode with a static duty cycle pins COM4 to COM1 output the same waveform and with 1 2 duty the COM1 waveform is output from pins COM2 and COM1 and the COM2 waveform is output from pins COM4 and...

Page 342: ...s used for the LCD drive power supply connect the external power supply to the V1 pin and short the V0 pin to VCC externally as shown in figure 13 4 b Figure 13 4 Examples of LCD Power Supply Pin Connections e Low power consumption LCD drive system Use of a low power consumption LCD drive system enables the power consumption required for LCD drive to be optimized For details see 13 3 5 Low Power C...

Page 343: ...ed in accordance with the LCD panel specification For the clock selection method in watch mode subactive mode and subsleep mode see 13 3 6 Operation in Power Down Modes d A or B waveform selection Either the A or B waveform can be selected as the LCD waveform to be used by means of LCDAB e LCD drive power supply selection When the on chip power supply circuit is used the power supply to be used ca...

Page 344: ...13 9 to 13 12 After setting the registers required for display data is written to the part corresponding to the duty using the same kind of instruction as for ordinary RAM and display is started automatically when turned on Word or byte access instructions can be used for RAM setting Figure 13 5 LCD RAM Map when Not Using Segment External Expansion 1 4 Duty bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ...

Page 345: ... when Not Using Segment External Expansion 1 3 Duty bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SEG2 SEG2 SEG2 SEG1 SEG1 SEG1 H F740 H F74F SEG32 SEG32 SEG32 SEG31 SEG31 SEG31 COM3 COM2 COM1 COM3 COM2 COM1 Space not used for display ...

Page 346: ...ternal Expansion 1 2 Duty bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SEG4 SEG4 SEG3 SEG3 SEG2 SEG2 SEG1 SEG1 SEG32 H F740 H F747 H F74F SEG32 SEG31 SEG31 SEG30 SEG30 SEG29 SEG29 COM2 COM1 COM2 COM1 COM2 COM1 COM2 COM1 Display space Space not used for display ...

Page 347: ...rnal Expansion Static Mode bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG32 H F740 H F743 H F74F SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1 Space not used for display Display space ...

Page 348: ... Expansion SGX 1 SGS3 to SGS0 0000 1 4 Duty bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SEG2 SEG2 SEG2 SEG2 SEG1 SEG1 SEG1 SEG1 SEG64 H F740 H F75F SEG64 SEG64 SEG64 SEG63 SEG63 SEG63 SEG63 COM4 COM3 COM2 COM1 COM4 COM3 COM1 COM1 Expansion driver display space ...

Page 349: ...nal Expansion SGX 1 SGS3 to SGS0 0000 1 3 Duty Space not used for display bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SEG2 SEG2 SEG2 SEG1 SEG1 SEG1 H F740 H F75F SEG64 SEG64 SEG64 SEG63 SEG63 SEG63 COM3 COM2 COM1 COM3 COM1 COM1 Expansion driver display space ...

Page 350: ...pansion SGX 1 SGS3 to SGS0 0000 1 2 Duty bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SEG4 SEG4 SEG3 SEG3 SEG2 SEG2 SEG1 SEG1 SEG128 H F740 H F75F SEG128 SEG127 SEG127 SEG126 SEG126 SEG125 SEG125 COM2 COM1 COM2 COM1 COM2 COM1 COM2 COM1 Expansion driver display space ...

Page 351: ...xpansion SGX 1 SGS3 to SGS0 0000 Static bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG256 H F740 H F75F SEG255 SEG254 SEG253 SEG252 SEG251 SEG250 SEG249 COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1 Expansion driver display space ...

Page 352: ...ither of these voltages is used directly as the LCD drive power supply the V0 and V1 pins should be shorted Also connecting a variable resistance R between the V0 and V1 pins makes it possible to adjust the voltage applied to the V1 pin and so to provide luminance adjustment for the LCD panel Figure 13 13 LCD Drive Power Supply Unit Power supply selector Step up constant voltage power supply Appli...

Page 353: ...ct current flows constantly from the built in resistance s VCC to VSS As this current does not depend on the current dissipation of the LCD panel if an LCD panel with a small current dissipation is used a wasteful amount of power will be consumed The H8 3864 Series is equipped with a function to minimize this waste of power Use of this function makes it possible to achieve the optimum power supply...

Page 354: ...tedly charged and discharged in the cycle shown in figure 13 14 maintaining the potentials and continuously driving the LCD panel 5 As can be seen from the above description the capacitances and charging discharging periods of the capacitors are determined by the current dissipation of the LCD panel used The charging discharging periods can be selected with bits CDS3 to CDS0 6 The actual capacitor...

Page 355: ...VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS a Waveform with 1 4 duty 1 frame M Data COM1 COM2 COM3 SEGn V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS 1 frame M Data COM1 COM2 SEGn V1 V2 V3 VSS V1 V2 V3 VSS 1 frame M Data COM1 SEGn V1 VSS V1 VSS b Waveform with 1 3 duty c Waveform with 1 2 duty d Waveform with static output ...

Page 356: ...th static output 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame b Waveform with 1 3 duty M Data COM3 SEGn COM1 V1 V2 V3 VSS COM2 V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS a Waveform with 1 4 duty M Data COM1 COM2 COM3 COM4 SEGn V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame V1 V2 V3 VSS ...

Page 357: ...re is a possibility that a direct current will be applied to the LCD panel in this case it is essential to ensure that øw øw 2 or øw 4 is selected In active medium speed mode the system clock is switched and therefore CKS3 to CKS0 must be modified to ensure that the frame frequency does not change Table 13 4 Power Down Modes and Display Operation Module Mode Reset Active Sleep Watch Subactive Subs...

Page 358: ... or use an external power supply circuit If the power supply capacity is insufficient when VCC is used as the power supply the power supply impedance must be reduced This can be done by connecting bypass capacitors of around 0 1 to 0 3 µF to pins V1 to V3 as shown in figure 13 17 or by adding a split resistance externally Figure 13 17 Connection of External Split Resistance H8 3864 Series VCC VSS ...

Page 359: ...by a combination of the data and the M pin output but these combinations differ from those in the HD66100 Table 13 3 shows the output levels of the LCD drive power supply and figures 13 15 and 13 16 show the common and segment waveforms for each duty cycle When ACT is cleared to 0 operation stops with CL2 0 CL1 0 M 0 and DO at the data value 1 or 0 being output at that instant In standby mode the ...

Page 360: ... DO SEG29 M H8 3867 Series chip a 1 3 bias 1 4 or 1 3 duty VCC V1 V4 V3 V2 GND VEE SHL CL1 CL2 DI M HD66100 VCC V0 V1 V4 V3 VSS SEG32 CL1 SEG31 CL2 SEG30 DO SEG29 M H8 3867 Series chip b 1 2 duty VCC V1 V4 V3 V2 GND VEE SHL CL1 CL2 DI M HD66100 VCC V0 V1 V4 V3 VSS SEG32 CL1 SEG31 CL2 SEG30 DO SEG29 M H8 3867 Series chip c Static mode ...

Page 361: ...wer supply to the VCC pin and connect a capacitance of approximately 0 1 µF between CVCC and VSS as shown in figure 14 1 The internal step down circuit is made effective simply by adding this external circuit Notes 1 In the external circuit interface the external power supply voltage connected to VCC and the GND potential connected to VSS are the reference levels For example for port input output ...

Page 362: ...14 2 The external power supply is then input directly to the internal power supply Note The permissible range for the power supply voltage is 1 8 V to 5 5 V Operation cannot be guaranteed if a voltage outside this range less than 1 8 V or more than 5 5 V is input Figure 14 2 Power Supply Connection when Internal Step Down Circuit Is Not Used CVCC VSS Internal logic Step down circuit Internal power...

Page 363: ...ltage AVCC 0 3 to 7 0 V Programming voltage VPP 0 3 to 13 0 V Input voltage Ports other than Port B Vin 0 3 to VCC 0 3 V Port B AVin 0 3 to AVCC 0 3 V Operating temperature Topr 20 to 75 C Storage temperature Tstg 55 to 125 C Note Permanent damage may occur to the chip if maximum ratings are exceeded Normal operation should be under the conditions specified in Electrical Characteristics Exceeding ...

Page 364: ...es 1 Power supply voltage and oscillator frequency range 38 4 1 8 3 0 5 5 VCC V f W kHz All operating modes 32 768 4 5 6 0 2 0 3 2 4 0 0 4 1 0 1 8 2 2 3 0 2 6 4 5 5 5 VCC V VCC V fosc MHz fosc MHz Active high speed mode Sleep high speed mode Internal power supply step down circuit not used 1 0 2 0 0 4 1 8 2 2 5 5 Active high speed mode Sleep high speed mode Internal power supply step down circuit ...

Page 365: ... D converter and PWM Sleep medium speed mode except A D converter and PWM Internal power supply step down circuit not used Active high speed mode Sleep high speed mode except CPU Internal power supply step down circuit not used Active high speed mode Sleep high speed mode except CPU Internal power supply step down circuit used Active medium speed mode except A D converter and PWM Sleep medium spee...

Page 366: ... MHz 1 0 0 5 0 2 1 8 3 0 4 5 5 5 AVCC V ø MHz 4 5 Active high speed mode Sleep high speed mode Internal power supply step down circuit not used Active medium speed mode Sleep medium speed mode Internal power supply step down circuit not used Active high speed mode Sleep high speed mode Internal power supply step down circuit used 362 ...

Page 367: ...P0 to WKP7 IRQ0 to IRQ4 AEVL AEVH TMIC TMIF TMIG 0 9 VCC VCC 0 3 Except the above SCK31 SCK32 ADTRG RXD31 RXD32 0 7 VCC VCC 0 3 V VCC 4 0 to 5 5 V UD 0 8 VCC VCC 0 3 Except the above OSC1 0 8 VCC VCC 0 3 V VCC 4 0 to 5 5 V 0 9 VCC VCC 0 3 Except the above X1 0 9 VCC VCC 0 3 V VCC 1 8 V to 5 5 V P10 to P17 0 7 VCC VCC 0 3 V VCC 4 0 V to 5 5 V P30 to P37 P40 to P43 P50 to P57 P60 to P67 0 8 VCC VCC ...

Page 368: ... WKP0 to WKP7 IRQ0 to IRQ4 AEVL AEVH TMIC TMIF TMIG 0 3 0 1 VCC Except the above SCK31 SCK32 ADTRG RXD31 RXD32 0 3 0 3 VCC V VCC 4 0 to 5 5 V UD 0 3 0 2 VCC Except the above OSC1 0 3 0 2 When internal step down circuit is used 0 3 0 2 VCC V VCC 4 0 to 5 5 V 0 3 0 1 VCC Except the above X1 0 3 0 1 VCC V VCC 1 8 V to 5 5 V P10 to P17 0 3 0 3 VCC V VCC 4 0 V to 5 5 V P30 to P37 P40 to P43 P50 to P57 ...

Page 369: ...A3 Output VOL P10 to P17 0 6 V VCC 4 0 V to 5 5 V low P40 to P42 IOL 1 6 mA voltage 0 5 IOL 0 4 mA P50 to P57 0 5 IOL 0 4 mA P60 to P67 P70 to P77 P80 to P87 PA0 to PA3 P30 to P37 1 5 VCC 4 0 V to 5 5 V IOL 10 mA 0 6 VCC 4 0 V to 5 5 V IOL 1 6 mA 0 5 IOL 0 4 mA Input output IIL RES P43 20 0 µA VIN 0 5 V to 2 leakage 1 0 VCC 0 5 V 1 current OSC1 X1 1 0 µA VIN 0 5 V to P10 to P17 VCC 0 5 V P30 to P3...

Page 370: ...Ta 25 C PB0 to PB7 RES 80 0 2 15 0 1 P43 50 0 2 15 0 1 PB0 to PB7 15 0 Active IOPE1 VCC 0 7 1 0 mA Active high 3 mode speed mode 4 current VCC 5 V fOSC 5 dissipation 2MHz IOPE2 VCC 0 3 0 5 mA Active medium 3 speed mode 4 VCC 5 V fOSC 5 2MHz Divided by 128 Sleep ISLEEP VCC 0 4 0 6 mA VCC 5 V fOSC 3 mode 2MHz 4 current 5 dissipation Subactive ISUB VCC 15 30 µA VCC 2 7 V 3 mode LCD on 4 current 32 kH...

Page 371: ...he Mask ROM products 2 Applies to the HD6473867 and HD6473827 3 Pin states during current measurement Other LCD Power Mode RES Pin Internal State Pins Supply Oscillator Pins Active high speed VCC Operates VCC Halted System clock oscillator mode IOPE1 crystal Active medium Subclock oscillator speed mode IOPE2 Pin X1 GND Sleep mode VCC Only timers operate VCC Halted Subactive mode VCC Operates VCC H...

Page 372: ...ins 2 0 mA VCC 4 0V to 5 5V output low except port 3 current Port 3 10 0 VCC 4 0V to 5 5V per pin All output pins 0 5 Allowable IOL Output pins 40 0 mA VCC 4 0V to 5 5V output low except port 3 current total Port 3 80 0 VCC 4 0V to 5 5V All output pins 20 0 Allowable IOH All output pins 2 0 mA VCC 4 0V to 5 5V output high current per pin 0 2 Except the above Allowable IOH All output pins 15 0 mA V...

Page 373: ... V to 5 5 V 0 4 1 Except the above OSC clock øOSC tOSC OSC1 OSC2 167 2500 ns VCC 4 5 V to 5 5 V Figure 15 1 cycle time 250 2500 VCC 3 0 V to 5 5 V 2 313 2500 VCC 2 6 V to 5 5 V 500 2500 VCC 2 2 V to 5 5 V Figure 15 1 1000 2500 Except the above System clock ø tcyc 2 128 tOSC cycle time 244 1 µs Subclock oscillation fW X1 X2 32 768 kHz frequency or 38 4 Watch clock øW tW X1 X2 30 5 µs Figure 15 1 cy...

Page 374: ... 15 1 400 Except the above X1 15 26 µs or 13 02 External clock rise tCPr OSC1 20 ns VCC 4 5 V to 5 5 V Figure 15 1 time 30 VCC 2 6 V to 5 5 V 2 55 Except the above Figure 15 1 X1 55 0 ns External clock fall tCPf OSC1 20 ns VCC 4 5 V to 5 5 V Figure 15 1 time 30 VCC 2 6 V to 5 5 V 2 55 Except the above Figure 15 1 X1 55 0 ns Pin RES low width tREL RES 10 tcyc Figure 15 2 Input pin high width tIH IR...

Page 375: ...e 15 5 cycle Synchronous 6 or tsubcyc Input clock pulse width tSCKW 0 4 0 6 tscyc Figure 15 5 Transmit data delay time tTXD 1 tcyc VCC 4 0 V to 5 5 V Figure 15 6 synchronous 1 or tsubcycExcept the above Receive data setup time tRXS 200 0 ns VCC 4 0 V to 5 5 V Figure 15 6 1 synchronous 400 0 Except the above Figure 15 6 Receive data hold time tRXH 200 0 ns VCC 4 0 V to 5 5 V Figure 15 6 1 synchrono...

Page 376: ...ance Allowable RAIN 10 0 kΩ signal source impedance Resolution 10 bit data length Nonlinearity 2 5 LSB AVCC 3 0 V to 5 5 V 4 error VCC 3 0 V to 5 5 V 5 5 AVCC 2 0 V to 5 5 V VCC 2 0 V to 5 5 V 7 5 Except the above 5 Quantization 0 5 LSB error Absolute 3 0 LSB AVCC 3 0 V to 5 5 V 4 accuracy VCC 3 0 V to 5 5 V 6 0 AVCC 2 0 V to 5 5 V VCC 2 0 V to 5 5 V 8 0 Except the above 5 Conversion 15 5 155 µs A...

Page 377: ...d VSS to each segment pin or common pin 2 The output voltage in step up constant voltage power supply operation unloaded 3 When the liquid crystal display voltage is supplied from an external power source ensure that the following relationship is maintained V1 V2 V3 VSS Table 15 7 AC Characteristics for External Segment Expansion VCC 1 8 V to 5 5 V VSS 0 0 V Ta 20 C to 75 C including subactive mod...

Page 378: ...to 15 6 show timing diagrams Figure 15 1 Clock Input Timing Figure 15 2 RES Low Width Figure 15 3 Input Timing VIH VIL tIL IRQ0 to IRQ4 WKP0 to WKP7 ADTRG TMIC TMIF TMIG AEVL AEVH tIH RES VIL tREL t tw OSC VIH VIL tCPH tCPL tCPr OSC1 x1 tCPf ...

Page 379: ...Figure 15 4 UD Pin Minimum Modulation Width Timing Figure 15 5 SCK3 Input Clock Timing tscyc 31 tSCKW SCK 32 SCK VIL VIH tUDL UD tUDH 375 ...

Page 380: ...g 32 tscyc tTXD tRXS tRXH VOH V or V IH OH V or V IL OL VOL OH OL SCK 31 SCK TXD31 TXD32 transmit data RXD31 RXD32 receive data Note Output timing reference levels Output high Output low Load conditions are shown in figure 15 8 V 1 2Vcc 0 2 V V 0 8 V 376 ...

Page 381: ...Figure 15 7 Segment Expansion Signal Timing CL1 CL2 DO M tSU tCT tDH tCWL tCWH tCWH tCSU tCT tCSU tDM VCC 0 5V VCC 0 5V 0 4V 0 4V 0 4V VCC 0 5V 0 4V 377 ...

Page 382: ... Circuit Figure 15 9 Resonator Equivalent Circuit CS CO Frequency MHz RS max CO max 1 40 Ω 3 5 pF 4 193 100 Ω 16 pF RS max CO max 0 4 8 6 Ω 326 pF 4 8 8 Ω 36 pF Crystal Resonator Parameter RS OSC2 OSC1 LS Frequency MHz Ceramic Resonator Parameters VCC 2 4 kΩ 12 kΩ 30 pF Output pin 378 ...

Page 383: ...flow flag in CCR C C carry flag in CCR PC Program counter SP Stack pointer xx 3 8 16 Immediate data 3 8 or 16 bits d 8 16 Displacement 8 or 16 bits aa 8 16 Absolute address 8 or 16 bits Addition Subtraction Multiplication Division Logical AND Logical OR Exclusive logical OR Move Logical complement Condition Code Notation Symbol Modified according to the instruction result Not fixed value not guara...

Page 384: ... 0 6 Rs8 Rd16 MOV B Rs aa 8 B Rs8 aa 8 2 0 4 MOV B Rs aa 16 B Rs8 aa 16 4 0 6 MOV W xx 16 Rd W xx 16 Rd 4 0 4 MOV W Rs Rd W Rs16 Rd16 2 0 2 MOV W Rs Rd W Rs16 Rd16 2 0 4 MOV W d 16 Rs Rd W d 16 Rs16 Rd16 4 0 6 MOV W Rs Rd W Rs16 Rd16 2 0 6 Rs16 2 Rs16 MOV W aa 16 Rd W aa 16 Rd16 4 0 6 MOV W Rs Rd W Rs16 Rd16 2 0 4 MOV W Rs d 16 Rd W Rs16 d 16 Rd16 4 0 6 MOV W Rs Rd W Rd16 2 Rd16 2 0 6 Rs16 Rd16 MO...

Page 385: ... decimal adjust Rd8 2 3 2 SUB B Rs Rd B Rd8 Rs8 Rd8 2 2 SUB W Rs Rd W Rd16 Rs16 Rd16 2 1 2 SUBX B xx 8 Rd B Rd8 xx 8 C Rd8 2 2 2 SUBX B Rs Rd B Rd8 Rs8 C Rd8 2 2 2 SUBS W 1 Rd W Rd16 1 Rd16 2 2 SUBS W 2 Rd W Rd16 2 Rd16 2 2 DEC B Rd B Rd8 1 Rd8 2 2 DAS B Rd B Rd8 decimal adjust Rd8 2 2 NEG B Rd B 0 Rd Rd 2 2 CMP B xx 8 Rd B Rd8 xx 8 2 2 CMP B Rs Rd B Rd8 Rs8 2 2 CMP W Rs Rd W Rd16 Rs16 2 1 2 381 x...

Page 386: ... Rd8 xx 8 Rd8 2 0 2 OR B Rs Rd B Rd8 Rs8 Rd8 2 0 2 XOR B xx 8 Rd B Rd8 xx 8 Rd8 2 0 2 XOR B Rs Rd B Rd8 Rs8 Rd8 2 0 2 NOT B Rd B Rd Rd 2 0 2 SHAL B Rd B 2 2 SHAR B Rd B 2 0 2 SHLL B Rd B 2 0 2 SHLR B Rd B 2 0 0 2 ROTXL B Rd B 2 0 2 ROTXR B Rd B 2 0 2 382 b7 b0 0 C C b7 b0 b7 b0 0 C b7 b0 0 C C b7 b0 C b7 b0 xx 8 16 Rn Rn d 16 Rn Rn Rn aa 8 16 d 8 PC aa Implied No of States Addressing Mode Instruct...

Page 387: ...d16 0 4 8 BCLR xx 3 aa 8 B xx 3 of aa 8 0 4 8 BCLR Rn Rd B Rn8 of Rd8 0 2 2 BCLR Rn Rd B Rn8 of Rd16 0 4 8 BCLR Rn aa 8 B Rn8 of aa 8 0 4 8 BNOT xx 3 Rd B xx 3 of Rd8 2 2 xx 3 of Rd8 BNOT xx 3 Rd B xx 3 of Rd16 4 8 xx 3 of Rd16 BNOT xx 3 aa 8 B xx 3 of aa 8 4 8 xx 3 of aa 8 BNOT Rn Rd B Rn8 of Rd8 2 2 Rn8 of Rd8 BNOT Rn Rd B Rn8 of Rd16 4 8 Rn8 of Rd16 BNOT Rn aa 8 B Rn8 of aa 8 4 8 Rn8 of aa 8 38...

Page 388: ... 3 Rd B C xx 3 of Rd16 4 8 BST xx 3 aa 8 B C xx 3 of aa 8 4 8 BIST xx 3 Rd B C xx 3 of Rd8 2 2 BIST xx 3 Rd B C xx 3 of Rd16 4 8 BIST xx 3 aa 8 B C xx 3 of aa 8 4 8 BAND xx 3 Rd B C xx 3 of Rd8 C 2 2 BAND xx 3 Rd B C xx 3 of Rd16 C 4 6 BAND xx 3 aa 8 B C xx 3 of aa 8 C 4 6 BIAND xx 3 Rd B C xx 3 of Rd8 C 2 2 BIAND xx 3 Rd B C xx 3 of Rd16 C 4 6 BIAND xx 3 aa 8 B C xx 3 of aa 8 C 4 6 BOR xx 3 Rd B ...

Page 389: ...PC 2 2 4 BHI d 8 C Z 0 2 4 BLS d 8 C Z 1 2 4 BCC d 8 BHS d 8 C 0 2 4 BCS d 8 BLO d 8 C 1 2 4 BNE d 8 Z 0 2 4 BEQ d 8 Z 1 2 4 BVC d 8 V 0 2 4 BVS d 8 V 1 2 4 BPL d 8 N 0 2 4 BMI d 8 N 1 2 4 BGE d 8 N V 0 2 4 BLT d 8 N V 1 2 4 BGT d 8 Z N V 0 2 4 BLE d 8 Z N V 1 2 4 JMP Rn PC Rn16 2 4 JMP aa 16 PC aa 16 4 6 JMP aa 8 PC aa 8 2 8 BSR d 8 SP 2 SP 2 6 PC SP PC PC d 8 385 xx 8 16 Rn Rn d 16 Rn Rn Rn aa 8...

Page 390: ...peat R5 R6 R5 1 R5 R6 1 R6 R4L 1 R4L Until R4L 0 else next Notes 1 Set to 1 when there is a carry or borrow from bit 11 otherwise cleared to 0 2 If the result is zero the previous value of the flag is retained otherwise the flag is cleared to 0 3 Set to 1 if decimal adjustment produces a carry otherwise retains value prior to arithmetic operation 4 The number of states required for execution is 4n...

Page 391: ... the operation codes contained in the first byte of the instruction code bits 15 to 8 of the first instruction word Instruction when first bit of byte 2 bit 7 of first instruction word is 0 Instruction when first bit of byte 2 bit 7 of first instruction word is 1 387 ...

Page 392: ...S XORC XOR BCS BSR BOR BIOR BXOR BIXOR BAND BIAND ANDC AND BNE RTE LDC BEQ NOT NEG BLD BILD BST BIST ADD SUB BVC BVS MOV INC DEC BPL JMP ADDS SUBS BMI EEPMOV MOV CMP BGE BLT ADDX SUBX BGT JSR DAA DAS BLE MOV ADD ADDX CMP SUBX OR XOR AND MOV MOV Note Bit manipulation instructions The PUSH and POP instructions are identical in machine language to MOV instructions Table A 2 Operation Code Map 388 ...

Page 393: ...of an instruction can be calculated from these two tables as follows Execution states I SI J SJ K SK L SL M SM N SN Examples When instruction is fetched from on chip ROM and an on chip RAM is accessed BSET 0 FF00 From table A 4 I L 2 J K M N 0 From table A 3 SI 2 SL 2 Number of states required for execution 2 2 2 2 8 When instruction is fetched from on chip ROM branch address is read from on chip ...

Page 394: ...ruction cycle On Chip Memory On Chip Peripheral Module Instruction fetch SI 2 Branch address read SJ Stack operation SK Byte data access SL 2 or 3 Word data access SM Internal operation SN 1 Note Depends on which on chip module is accessed See 2 9 1 Notes on Data Access for details 390 ...

Page 395: ...DS W 1 Rd 1 ADDS W 2 Rd 1 ADDX ADDX B xx 8 Rd 1 ADDX B Rs Rd 1 AND AND B xx 8 Rd 1 AND B Rs Rd 1 ANDC ANDC xx 8 CCR 1 BAND BAND xx 3 Rd 1 BAND xx 3 Rd 2 1 BAND xx 3 aa 8 2 1 Bcc BRA d 8 BT d 8 2 BRN d 8 BF d 8 2 BHI d 8 2 BLS d 8 2 BCC d 8 BHS d 8 2 BCS d 8 BLO d 8 2 BNE d 8 2 BEQ d 8 2 BVC d 8 2 BVS d 8 2 BPL d 8 2 BMI d 8 2 BGE d 8 2 BLT d 8 2 BGT d 8 2 BLE d 8 2 BCLR BCLR xx 3 Rd 1 BCLR xx 3 Rd...

Page 396: ...d 1 BILD xx 3 Rd 2 1 BILD xx 3 aa 8 2 1 BIOR BIOR xx 3 Rd 1 BIOR xx 3 Rd 2 1 BIOR xx 3 aa 8 2 1 BIST BIST xx 3 Rd 1 BIST xx 3 Rd 2 2 BIST xx 3 aa 8 2 2 BIXOR BIXOR xx 3 Rd 1 BIXOR xx 3 Rd 2 1 BIXOR xx 3 aa 8 2 1 BLD BLD xx 3 Rd 1 BLD xx 3 Rd 2 1 BLD xx 3 aa 8 2 1 BNOT BNOT xx 3 Rd 1 BNOT xx 3 Rd 2 2 BNOT xx 3 aa 8 2 2 BNOT Rn Rd 1 BNOT Rn Rd 2 2 BNOT Rn aa 8 2 2 BOR BOR xx 3 Rd 1 BOR xx 3 Rd 2 1 B...

Page 397: ... 8 2 1 BTST Rn Rd 1 BTST Rn Rd 2 1 BTST Rn aa 8 2 1 BXOR BXOR xx 3 Rd 1 BXOR xx 3 Rd 2 1 BXOR xx 3 aa 8 2 1 CMP CMP B xx 8 Rd 1 CMP B Rs Rd 1 CMP W Rs Rd 1 DAA DAA B Rd 1 DAS DAS B Rd 1 DEC DEC B Rd 1 DIVXU DIVXU B Rs Rd 1 12 EEPMOV EEPMOV 2 2n 2 1 INC INC B Rd 1 JMP JMP Rn 2 JMP aa 16 2 2 JMP aa 8 2 1 2 JSR JSR Rn 2 1 JSR aa 16 2 1 2 JSR aa 8 2 1 1 LDC LDC xx 8 CCR 1 LDC Rs CCR 1 MOV MOV B xx 8 R...

Page 398: ...Rd 1 1 MOV B Rs d 16 Rd 2 1 MOV B Rs Rd 1 1 2 MOV B Rs aa 8 1 1 MOV B Rs aa 16 2 1 MOV W xx 16 Rd 2 MOV W Rs Rd 1 MOV W Rs Rd 1 1 MOV W d 16 Rs Rd 2 1 MOV W Rs Rd 1 1 2 MOV W aa 16 Rd 2 1 MOV W Rs Rd 1 1 MOV W Rs d 16 Rd 2 1 MOV W Rs Rd 1 1 2 MOV W Rs aa 16 2 1 MULXU MULXU B Rs Rd 1 12 NEG NEG B Rd 1 NOP NOP 1 NOT NOT B Rd 1 OR OR B xx 8 Rd 1 OR B Rs Rd 1 ORC ORC xx 8 CCR 1 ROTL ROTL B Rd 1 ROTR R...

Page 399: ...cess Operation Instruction Mnemonic I J K L M N SHAL SHAL B Rd 1 SHAR SHAR B Rd 1 SHLL SHLL B Rd 1 SHLR SHLR B Rd 1 SLEEP SLEEP 1 STC STC CCR Rd 1 SUB SUB B Rs Rd 1 SUB W Rs Rd 1 SUBS SUBS W 1 Rd 1 SUBS W 2 Rd 1 POP POP Rd 1 1 2 PUSH PUSH Rs 1 1 2 SUBX SUBX B xx 8 Rd 1 SUBX B Rs Rd 1 XOR XOR B xx 8 Rd 1 XOR B Rs Rd 1 XORC XORC xx 8 CCR 1 395 ...

Page 400: ...RR313 BRR312 BRR311 BRR310 H 9A SCR31 TIE31 RIE31 TE31 RE31 MPIE31 TEIE31 CKE31 CKE310 H 9B TDR31 TDR317 TDR316 TDR315 TDR314 TDR313 TDR312 TDR311 TDR310 H 9C SSR31 TDRE31 RDRF31 OER31 FER31 PER31 TEND31 MPBR31 MPBT31 H 9D RDR31 RDR317 RDR316 RDR315 RDR314 RDR313 RDR312 RDR311 RDR310 H 9E H 9F H A0 H A1 H A2 H A3 H A4 H A5 H A6 H A7 H A8 SMR32 COM32 CHR32 PE32 PM32 STOP32 MP32 CKS321 CKS320 SCI32 ...

Page 401: ...RFL6 OCRFL5 OCRFL4 OCRFL3 OCRFL2 OCRFL1 OCRFL0 H BC TMG OVFH OVFL OVIE IIEGS CCLR1 CCLR0 CKS1 CKS0 Timer G H BD ICRGF ICRGF7 ICRGF6 ICRGF5 ICRGF4 ICRGF3 ICRGF2 ICRGF1 ICRGFO H BE ICRGR ICRGR7 ICRGR6 ICRGR5 ICRGR4 ICRGR3 ICRGR2 ICRGR1 ICRGRO H BF H C0 LPCR DTS1 DTS0 CMX SGX SGS3 SGS2 SGS1 SGS0 LCD H C1 LCR PSW ACT DISP CKS3 CKS2 CKS1 CKS0 controller H C2 LCR2 LCDAB SUPS CDS3 CDS2 CDS1 CDS0 driver H...

Page 402: ... PUCR6 PUCR67 PUCR66 PUCR65 PUCR64 PUCR63 PUCR62 PUCR61 PUCR60 H E4 PCR1 PCR17 PCR16 PCR15 PCR14 PCR13 PCR12 PCR11 PCR10 H E5 H E6 PCR3 PCR37 PCR36 PCR35 PCR34 PCR33 PCR32 PCR31 PCR30 H E7 PCR4 PCR42 PCR41 PCR40 H E8 PCR5 PCR57 PCR56 PCR55 PCR54 PCR53 PCR52 PCR51 PCR50 H E9 PCR6 PCR67 PCR66 PCR65 PCR64 PCR63 PCR62 PCR61 PCR60 H EA PCR7 PCR77 PCR76 PCR75 PCR74 PCR73 PCR72 PCR71 PCR70 H EB PCR8 PCR8...

Page 403: ...Bit 2 Bit 1 Bit 0 Name H F9 IWPR IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0 System H FA CKSTPR1 S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP control H FB CKSTPR2 AECKSTP WDCKSTP PWCKSTP LDCKSTP H FC H FD H FE H FF Legend SCI Serial Communication Interface 399 ...

Page 404: ...TMC5 0 R W 3 1 0 TMC0 0 R W 2 TMC2 0 R W 1 TMC1 0 R W 4 1 Clock select 0 Internal clock Internal clock 0 0 1 Internal clock Internal clock 1 0 1 1 0 0 1 1 0 1 Internal clock Internal clock Internal clock External event TMIC ø 8192 ø 2048 ø 512 ø 64 ø 16 ø 4 ø 4 Rising or falling edge W Counter up down control TCC is an up counter TCC is a down counter 0 0 1 TCC up down control is determined by inp...

Page 405: ... input data inversion switch 0 RXD32 input data is not inverted 1 RXD32 input data is inverted TXD32 pin output data inversion switch 0 TXD32 output data is not inverted 1 TXD32 output data is inverted P35TXD31 pin function switch 0 Functions as P35 I O pin 1 Functions as TXD31 output pin P42 TXD32pin function switch 0 Function as P42 I O pin 1 Function as TXD32 output pin 3 SCINV3 0 R W Bit Initi...

Page 406: ...R Subclock Output Select Register H 92 Timer A Bit Initial value Read Write 7 1 R 6 1 R 5 1 R 0 CWOS 0 R W 2 1 R 1 1 R 4 1 R TMOW pin clock select 0 Clock output from TMA is output 1 øW is output 3 1 R 402 ...

Page 407: ...unction is enabled Count up enable L 0 ECL event clock input is disabled ECL value is held 1 ECL event clock input is enabled Count up enable H 0 ECH event clock input is disabled ECH value is held 1 ECH event clock input is enabled Channel select 0 ECH and ECL are used together as a single channel 16 bit event counter 1 ECH and ECL are used as two independent 8 bit event counter channels Counter ...

Page 408: ...ter L H 97 AEC Bit Initial value Read Write 7 ECL7 0 R 6 ECL6 0 R 5 ECL5 0 R 0 ECL0 0 R 2 ECL2 0 R 1 ECL1 0 R 4 ECL4 0 R 3 ECL3 0 R Bit Initial value Read Write 7 ECH7 0 R 6 ECH6 0 R 5 ECH5 0 R 0 ECH0 0 R 2 ECH2 0 R 1 ECH1 0 R 4 ECH4 0 R 3 ECH3 0 R ...

Page 409: ...ultiprocessor mode 0 Multiprocessor communication function disabled 1 Multiprocessor communication function enabled Stop bit length 0 1 stop bit 1 2 stop bits Parity mode 0 Even parity 1 Odd parity Parity enable 0 Parity bit addition and checking disabled 1 Parity bit addition and checking enabled Character length 0 8 bit data 5 bit data 1 7 bit data 5 bit data Communication mode 0 Asynchronous mo...

Page 410: ...BRR31 Bit rate register31 H 99 SCI31 Bit Initial value Read Write 7 BRR317 1 R W 6 BRR316 1 R W 5 BRR315 1 R W 4 BRR314 1 R W 3 BRR313 1 R W 0 BRR310 1 R W 2 BRR312 1 R W 1 BRR311 1 R W 406 ...

Page 411: ...eceived Transmit enable 0 Transmit operation disabled TXD pin is transmit data pin 1 Transmit operation enabled TXD pin is transmit data pin Receive enable 0 Receive operation disabled RXD pin is I O port 1 Receive operation enabled RXD pin is receive data pin Transmit end interrupt enable Clock enable 0 Bit 1 CKE311 0 0 1 1 Bit 0 CKE310 0 1 0 1 Communication Mode Asynchronous Synchronous Asynchro...

Page 412: ...nsmit data register 31 H 9B SCI31 Bit Initial value Read Write 7 TDR317 1 R W 6 TDR316 1 R W 5 TDR315 1 R W 4 TDR314 1 R W 3 TDR313 1 R W 0 TDR310 1 R W 2 TDR312 1 R W 1 TDR311 1 R W Data for transfer to TSR 408 ...

Page 413: ...r reading PER31 1 cleared by writing 0 to PER31 1 A parity error has occurred during reception Setting conditions Framing error 0 Reception in progress or completed normally Clearing conditions After reading FER31 1 cleared by writing 0 to FER31 1 A framing error has occurred during reception Setting conditions When the stop bit at the end of the receive data is checked for a value of 1 at complet...

Page 414: ...RDR31 Receive data register 31 H F9D SCI31 Bit Initial value Read Write 7 RDR317 0 R 6 RDR316 0 R 5 RDR315 0 R 4 RDR314 0 R 3 RDR313 0 R 0 RDR310 0 R 2 RDR312 0 R 1 RDR311 0 R 410 ...

Page 415: ...ultiprocessor mode 0 Multiprocessor communication function disabled 1 Multiprocessor communication function enabled Stop bit length 0 1 stop bit 1 2 stop bits Parity mode 0 Even parity 1 Odd parity Parity enable 0 Parity bit addition and checking disabled 1 Parity bit addition and checking enabled Character length 0 8 bit data 5 bit data 1 7 bit data 5 bit data Communication mode 0 Asynchronous mo...

Page 416: ...BRR32 Bit rate register 32 H A9 SCI32 Bit Initial value Read Write 7 BRR327 1 R W 6 BRR326 1 R W 5 BRR325 1 R W 4 BRR324 1 R W 3 BRR323 1 R W 0 BRR3120 1 R W 2 BRR322 1 R W 1 BRR321 1 R W 412 ...

Page 417: ...eceived Transmit enable 0 Transmit operation disabled TXD pin is transmit data pin 1 Transmit operation enabled TXD pin is transmit data pin Receive enable 0 Receive operation disabled RXD pin is I O port 1 Receive operation enabled RXD pin is receive data pin Transmit end interrupt enable Clock enable 0 Bit 1 CKE321 0 0 1 1 Bit 0 CKE320 0 1 0 1 Communication Mode Asynchronous Synchronous Asynchro...

Page 418: ...nsmit data register 32 H AB SCI32 Bit Initial value Read Write 7 TDR327 1 R W 6 TDR326 1 R W 5 TDR325 1 R W 4 TDR324 1 R W 3 TDR323 1 R W 0 TDR320 1 R W 2 TDR322 1 R W 1 TDR321 1 R W Data for transfer to TSR 414 ...

Page 419: ...er reading PER32 1 cleared by writing 0 to PER32 1 A parity error has occurred during reception Setting conditions Framing error 0 Reception in progress or completed normally Clearing conditions After reading FER32 1 cleared by writing 0 to FER32 1 A framing error has occurred during reception Setting conditions When the stop bit at the end of the receive data is checked for a value of 1 at comple...

Page 420: ... 0 1 1 PSS PSS PSS PSS 1 0 1 0 0 1 1 1 PSW PSW PSW PSW 0 0 1 0 0 1 1 PSW and TCA are reset 1 0 1 0 0 1 1 Prescaler and Divider Ratio or Overflow Period ø 8192 ø 4096 ø 2048 ø 512 ø 256 ø 128 ø 32 ø 8 1 s 0 5 s 0 25 s 0 03125 s Interval timer Time base when using 32 768 kHz Function 0 0 1 ø 8 ø 4 1 0 1 1 0 0 1 1 0 1 ø 32 W ø 16 W ø 8 W ø 4 W 3 TMA3 0 R W Bit Initial value Read Write 7 RDR327 0 R 6 ...

Page 421: ...TCA Timer counter A H B1 Timer A Bit Initial value Read Write 7 TCA7 0 R 6 TCA6 0 R 5 TCA5 0 R 4 TCA4 0 R 3 TCA3 0 R 0 TCA0 0 R 2 TCA2 0 R 1 TCA1 0 R Count value 417 ...

Page 422: ...nabled Bit 0 is write protected 1 Watchdog timer on 0 Watchdog timer operation is disabled Watchdog timer operation is enabled 1 Bit 2 write inhibit 0 Bit 2 is write enabled Bit 2 is write protected 1 Timer control status register W write enable 0 Data cannot be written to bits 2 and 0 Data can be written to bits 2 and 0 1 Bit 4 write inhibit 0 Bit 4 is write enabled Bit 4 is write protected 1 Tim...

Page 423: ...l clock Internal clock Internal clock External event TMIC Counting on rising or falling edge Don t care ø 8192 ø 2048 ø 512 ø 64 ø 16 ø 4 øw 4 0 Interval timer function selected 1 Auto reload function selected Counter up down control 0 TCC is an up counter 1 TCC is a down counter Hardware control of TCC up down operation by UD pin input UD pin input high Down counter UD pin input low Up counter 0 ...

Page 424: ...t Initial value Read Write 7 TLC7 0 R W 6 TLC6 0 R W 5 TLC5 0 R W 4 TLC4 0 R W 3 TLC3 0 R W 0 TLC0 0 R W 2 TLC2 0 R W 1 TLC1 0 R W Reload value Bit Initial value Read Write 7 TCC7 0 R 6 TCC6 0 R 5 TCC5 0 R 4 TCC4 0 R 3 TCC3 0 R 0 TCC0 0 R 2 TCC2 0 R 1 TCC1 0 R Count value 420 ...

Page 425: ...ising falling edge Internal clock ø 32 Internal clock ø 16 Internal clock ø 4 Internal clock øw 4 1 1 1 1 0 0 1 1 0 1 0 1 Toggle output level L 0 Low level 1 High level Toggle output level H 0 Low level 1 High level 3 TOLL 0 W Clock select H 0 overflow signal Internal clock ø 32 Internal clock ø 16 Internal clock ø 4 Internal clock øw 4 16 bit mode counting on TCFL Don t care 1 1 1 1 0 0 1 1 0 1 0...

Page 426: ...g 0 to CMFL 1 Setting conditions Set when the TCFL value matches the OCRFL value Timer overflow flag L 0 Clearing conditions After reading OVFL 1 cleared by writing 0 to OVFL 1 Setting conditions Set when TCFL overflows from H FF to H 00 Counter clear H 0 16 bit mode TCF clearing by compare match is disabled 8 bit mode TCFH clearing by compare match is disabled 1 16 bit mode TCF clearing by compar...

Page 427: ... W 2 OCRFL2 1 R W 1 OCRFL1 1 R W Bit Initial value Read Write 7 OCRFH7 1 R W 6 OCRFH6 1 R W 5 OCRFH5 1 R W 4 OCRFH4 1 R W 3 OCRFH3 1 R W 0 OCRFH0 1 R W 2 OCRFH2 1 R W 1 OCRFH1 1 R W Bit Initial value Read Write 7 TCFL7 0 R W 6 TCFL6 0 R W 5 TCFL5 0 R W 4 TCFL4 0 R W 3 TCFL3 0 R W 0 TCFL0 0 R W 2 TCFL2 0 R W 1 TCFL1 0 R W Count value Bit Initial value Read Write 7 TCFH7 0 R W 6 TCFH6 0 R W 5 TCFH5 ...

Page 428: ...rrupt request is enabled 0 1 0 Clearing conditions After reading OVFH 1 cleared by writing 0 to OVFH 1 Setting conditions Set when TCG overflows from H FF to H 00 Note Bits 7 and 6 can only be written with 0 for flag clearing Timer overflow flag L 0 Clearing conditions After reading OVFL 1 cleared by writing 0 to OVFL 1 Setting conditions Set when TCG overflows from H FF to H 00 Input capture inte...

Page 429: ...ts when the setting of SGS3 to SGS0 is 0000 or 0001 SEG20 to SEG17 Port Port Port Port SEG SEG Port SEG16 to SEG13 Port Port Port Port SEG SEG Port SEG12 to SEG9 Port Port Port Port Port SEG Port SEG8 to SEG5 Port Port Port Port Port SEG Port Notes Initial value SEG4 to SEG1 Duty select common function select Bit 7 DTS1 0 0 1 1 Bit 6 DTS0 0 1 0 1 Bit 5 CMX 0 1 0 1 0 1 0 1 Duty Cycle Static 1 2 dut...

Page 430: ...ect Operating Clock Bit 1 Bit 2 Bit 3 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Bit 1 CKS1 CKS2 CKS3 CKS0 øw øw øw 2 ø 2 ø 4 ø 8 ø 16 ø 32 ø 64 ø 128 ø 256 Display function activate LCD controller driver operation halted LCD controller driver operates Don t care 0 1 0 LCD drive power supply off 1 LCD drive power supply on Display data control 0 Blank data is d...

Page 431: ...ing control Charge discharge pulse duty cycle select Duty Cycle Bit 1 Bit 2 Bit 3 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 1 8 2 8 3 8 4 8 5 8 6 8 0 1 16 1 32 Bit 1 CDS1 CDS2 CDS3 CDS0 Don t care 0 Drive using A waveform 1 Drive using B waveform 5 V regulator control 0 Applies to the H8 3867 Series 1 5 V regulator halted 5 V regulator operates 427 ...

Page 432: ...External trigger select 0 Disables start of A D conversion by external trigger 1 Enables start of A D conversion by rising or falling edge of external trigger at pin ADTRG 5 1 4 AN5 AN6 AN7 1 0 0 1 1 0 1 AN0 AN1 AN2 AN3 Clock select 62 ø Bit 7 0 Conversion Period CKS 31 ø 1 62 µs ø 1 MHz 31 µs 31 µs ø 2 MHz 15 5µs Conversion Time Note Operation is not guaranteed with a conversion time of less than...

Page 433: ... completion of A D conversion Stops A D conversion Indicates A D conversion in progress Starts A D conversion Bit Initial value Read Write ADRRH 7 ADR9 Not fixed R W 6 ADR8 Not fixed R W 5 ADR7 Not fixed R W 3 ADR5 Not fixed R W 0 ADR2 Not fixed R W 2 ADR4 Not fixed R W 1 ADR3 Not fixed R W 4 ADR6 Not fixed R W A D conversion result Bit Initial value Read Write ADRRL 7 ADR1 Not fixed R 6 ADR0 Not ...

Page 434: ...13 TMIG pin function switch 0 Functions as P13 I O pin 1 Functions as TMIG input pin P14 IRQ4 ADTRG pin function switch 0 Functions as P14 I O pin 1 Functions as IRQ4 ADTRG input pin P15 IRQ1 TMIC pin function switch 0 Functions as P15 I O pin 1 Functions as IRQ1 TMIC input pin P11 TMOFL pin function switch 0 Functions as P11 I O pin 1 Functions as TMOFL output pin P16 IRQ2 pin function switch 0 F...

Page 435: ...n 1 Functions as RESO I O pin P43 IRQ0 pin function switch 0 Functions as P43 I O pin 1 Functions as IRQ0 input pin Watchdog timer switch 0 ø8192 1 P31 UD pin function switch 0 Functions as P31 I O pin 1 Functions as UD input pin TMIG noise canceler select 0 Noise cancellation function not used 1 Noise cancellation function used P36 AEVH pin function switch 0 Functions as P36 I O pin Functions as ...

Page 436: ...rsion period is 16 384 ø with a minimum modulation width of 1 ø The input clock is ø 4 tø 4 ø The conversion period is 32 768 ø with a minimum modulation width of 2 ø 1 The input clock is ø 8 tø 8 ø The conversion period is 65 536 ø with a minimum modulation width of 4 ø The input clock is ø 16 tø 16 ø The conversion period is 131 072 ø with a minimum modulation width of 8 ø Note tø Period of PWM ...

Page 437: ... 5 6 7 1 Bit Initial value Read Write 7 P1 0 R W 6 P1 0 R W 5 P1 0 R W 4 P1 0 R W 3 P1 0 R W 0 P1 0 R W 2 P1 0 R W 1 P1 0 R W 7 6 5 4 3 2 1 0 Bit Initial value Read Write 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 0 0 W 2 0 W 1 0 W Lower 8 bits of data for generating PWM waveform PWDRL5 PWDRL4 PWDRL3 PWDRL0 PWDRL2 PWDRL1 PWDRL6 PWDRL7 Bit Initial value Read Write 7 1 6 1 5 0 W 4 0 W 3 0 W 0 0 W 2 0 W 1 0 W Upp...

Page 438: ... R W 3 0 2 1 4 5 6 7 Bit Initial value Read Write 7 P7 0 R W 6 P7 0 R W 5 P7 0 R W 4 P7 0 R W 3 P7 0 R W 0 P7 0 R W 2 P7 0 R W 1 P7 0 R W 3 2 1 0 4 5 6 7 Bit Initial value Read Write 7 P6 0 R W 6 P6 0 R W 5 P6 0 R W 4 P6 0 R W 3 P6 0 R W 0 P6 0 R W 2 P6 0 R W 1 P6 0 R W 3 0 2 1 4 5 6 7 Bit Initial value Read Write 7 P5 0 R W 6 P5 0 R W 5 P5 0 R W 4 P5 0 R W 3 P5 0 R W 0 P5 0 R W 2 P5 0 R W 1 P5 0 ...

Page 439: ...PUCR5 0 R W 1 PUCR5 0 R W 3 0 2 1 4 5 6 7 Bit Initial value Read Write 7 PUCR3 0 R W 6 PUCR3 0 R W 5 PUCR3 0 R W 4 PUCR3 0 R W 3 PUCR3 0 R W 0 PUCR3 0 R W 2 PUCR3 0 R W 1 PUCR3 0 R W 0 2 3 4 5 6 7 1 Bit Initial value Read Write 7 PUCR1 0 R W 6 PUCR1 0 R W 5 PUCR1 0 R W 4 PUCR1 0 R W 3 PUCR1 0 R W 0 PUCR1 0 R W 2 PUCR1 0 R W 1 PUCR1 0 R W 0 4 3 2 1 5 6 7 Bit Initial value Read Write 7 PB R 6 PB R 5...

Page 440: ...1 Bit Initial value Read Write 7 PCR3 0 W 6 PCR3 0 W 5 PCR3 0 W 4 PCR3 0 W 3 PCR3 0 W 0 PCR3 0 W 2 PCR3 0 W 1 PCR3 0 W Port 3 input output select 0 Input pin 1 Output pin 0 2 3 4 5 6 7 1 Bit Initial value Read Write 7 PCR1 0 W 6 PCR1 0 W 5 PCR1 0 W 4 PCR1 0 W 3 PCR1 0 W 0 PCR1 0 W 2 PCR1 0 W 1 PCR1 0 W Port 1 input output select 0 Input pin 1 Output pin 7 6 5 4 3 2 1 0 Bit Initial value Read Write...

Page 441: ... 0 W Port 7 input output select 0 Input pin 1 Output pin 7 6 5 4 3 2 1 0 Bit Initial value Read Write 7 PCR6 0 W 6 PCR6 0 W 5 PCR6 0 W 4 PCR6 0 W 3 PCR6 0 W 0 PCR6 0 W 2 PCR6 0 W 1 PCR6 0 W Port 6 input output select 0 Input pin 1 Output pin 7 6 5 4 3 0 2 1 Bit Initial value Read Write 7 PCR5 0 W 6 PCR5 0 W 5 PCR5 0 W 4 PCR5 0 W 3 PCR5 0 W 0 PCR5 0 W 2 PCR5 0 W 1 PCR5 0 W Port 5 input output selec...

Page 442: ... 7 0 6 0 5 0 4 0 3 PCRA 0 R W 0 PCRA 0 R W 2 PCRA 0 R W 1 PCRA 0 R W 0 1 2 3 Port A input output select 0 Input pin 1 Output pin Bit Initial value Read Write 7 PCR8 0 W 6 PCR8 0 W 5 PCR8 0 W 4 PCR8 0 W 3 PCR8 0 W 0 PCR8 0 W 2 PCR8 0 W 1 PCR8 0 W Port 8 input output select 0 Input pin 1 Output pin 7 6 5 4 3 0 2 1 438 ...

Page 443: ...it time 65 536 states 1 0 1 Active medium speed mode clock select ø 16 ø 32 0 1 0 0 1 1 ø 64 ø 128 1 1 0 0 1 0 1 Wait time 131 072 states Wait time 2 states Wait time 8 states Wait time 16 states Low speed on flag 0 The CPU operates on the system clock ø 1 The CPU operates on the subclock ø SUB When a SLEEP instruction is executed in subactive mode a transition is made to subsleep mode When a SLEE...

Page 444: ...nsition is made to active medium speed mode if SSBY 0 MSON 1 and LSON 0 or to subactive mode if SSBY 1 TMA3 1 and LSON 1 When a SLEEP instruction is executed in active medium speed mode a direct transition is made to active high speed mode if SSBY 0 MSON 0 and LSON 0 or to subactive mode if SSBY 1 TMA3 1 and LSON 1 When a SLEEP instruction is executed in subactive mode a direct transition is made ...

Page 445: ...RQ1 edge select 0 Falling edge of IRQ1 TMIC pin input is detected Rising edge of IRQ1 TMIC pin input is detected 1 IRQ2 edge select 0 Falling edge of IRQ2 pin input is detected Rising edge of IRQ2 pin input is detected 1 IRQ3 edge select 0 Falling edge of IRQ3 TMIF pin input is detected Rising edge of IRQ3 TMIF pin input is detected 1 IRQ4 edge select 0 Falling edge of IRQ4 pin and ADTRG pin is de...

Page 446: ...W 1 IEN1 0 R W 5 IENWP 0 R W IRQ4 to IRQ0 interrupt enable 0 Disables IRQ4 to IRQ0 interrupt requests Enables IRQ4 to IRQ0 interrupt requests 1 Wakeup interrupt enable 0 Disables WKP7 to WKP0 interrupt requests Enables WKP7 to WKP0 interrupt requests 1 Timer A interrupt enable 0 Disables timer A interrupt requests Enables timer A interrupt requests 1 442 ...

Page 447: ...t requests 1 Enables timer FL interrupt requests Timer FH interrupt enable 0 Disables timer FH interrupt requests 1 Enables timer FH interrupt requests Timer G interrupt enable 0 Disables timer G interrupt requests 1 Enables timer G interrupt requests A D converter interrupt enable 0 Disables A D converter interrupt requests 1 Enables A D converter interrupt requests Timer C interrupt enable 0 Dis...

Page 448: ...learing conditions When IRRIn 1 it is cleared by writing 0 n 4 to 0 Note Bits 7 and 4 to 0 can only be written with 0 for flag clearing 1 Setting conditions When pin IRQn is designated for interrupt input and the designated signal edge is input Timer A interrupt request flag 0 Clearing conditions When IRRTA 1 it is cleared by writing 0 1 Setting conditions When the timer A counter value overflows ...

Page 449: ...red by writing 0 1 Setting conditions When a SLEEP instruction is executed while DTON is set to 1 and a direct transition is made Timer FH interrupt request flag 0 Clearing conditions When IRRTFH 1 it is cleared by writing 0 1 Setting conditions When counter FH and output compare register FH match in 8 bit timer mode or when 16 bit counters FL and FH and output compare registers FL and FH match in...

Page 450: ...3 0 R W 0 IWPF0 0 R W 2 IWPF2 0 R W 1 IWPF1 0 R W 4 IWPF4 0 R W 0 Clearing conditions When IWPFn 1 it is cleared by writing 0 n 7 to 0 Note All bits can only be written with 0 for flag clearing Wakeup interrupt request register 1 Setting conditions When pin WKPn is designated for wakeup input and a falling edge is input at that pin 446 ...

Page 451: ...tandby mode Timer G module standby mode is cleared 1 A D converter module standby mode control 0 A D converter is set to module standby mode A D converter module standby mode is cleared 1 Timer C module standby mode control 0 Timer C is set to module standby mode Timer C module standby mode is cleared 1 0 Timer A is set to module standby mode Timer A module standby mode is cleared 1 SCI3 2 module ...

Page 452: ...WDT is set to module standby mode WDT module standby mode is cleared 1 Asynchronous event counter module standby mode control 0 Asynchronous event counter is set to module standby mode Asynchronous event counter module standby mode is cleared 1 PWM module standby mode control 0 PWM is set to module standby mode PWM module standby mode is cleared 1 0 LCD is set to module standby mode LCD module sta...

Page 453: ...ort 1 Block Diagram Pins P17 to P14 VCC VCC VSS PUCR1n PMR1n PDR1n PCR1n IRQn 4 SBY low level during reset and in standby mode Internal data bus PDR1 PCR1 PMR1 PUCR1 n 7 to 4 Port data register 1 Port control register 1 Port mode register 1 Port pull up control register 1 P1n 449 ...

Page 454: ...Figure C 1 b Port 1 Block Diagram Pin P13 VCC VCC SBY VSS PUCR13 PMR13 PDR13 PCR13 Timer G module TMIG Internal data bus P13 450 ...

Page 455: ...in P12 P11 VCC VCC VSS PUCR1n PMR1n PDR1n PCR1n SBY Internal data bus PDR1 PCR1 PMR1 PUCR1 n 2 1 Port data register 1 Port control register 1 Port mode register 1 Port pull up control register 1 TMOFH P12 TMOFL P11 Timer F module P1n 451 ...

Page 456: ...ck Diagram Pin P10 VCC VCC VSS PUCR10 PMR10 PDR10 PCR10 SBY Internal data bus PDR1 PCR1 PMR1 PUCR1 Port data register 1 Port control register 1 Port mode register 1 Port pull up control register 1 TMOW Timer A module P10 452 ...

Page 457: ... 3 Block Diagram Pin P37 to P36 P3n VCC VCC PUCR3n PMR3n PDR3n PCR3n AEC module Internal data bus SBY VSS AEVH P36 AEVL P37 PDR3 PCR3 PMR3 PUCR3 Port data register 3 Port control register 3 Port mode register 3 Port pull up control register 3 n 7 to 6 ...

Page 458: ...Figure C 2 b Port 3 Block Diagram Pin P35 P35 SCI31 module PDR35 PUCR3 SCINV1 SPC31 PCR35 SBY VSS PDR3 Port data register 3 PCR3 Port control register 3 TXD31 Internal data bus VCC VCC 454 ...

Page 459: ...Figure C 2 c Port 3 Block Diagram Pin P34 P34 VCC VCC SCI31 module PDR34 PCR34 SCINV0 SBY VSS PDR3 Port data register 3 PCR3 Port control register 3 RE31 RXD31 Internal data bus PUCR3 455 ...

Page 460: ...Figure C 2 d Port 3 Block Diagram Pin P33 P33 VCC SCI31 module PDR33 PCR33 SBY VSS PDR3 Port data register 3 PCR3 Port control register 3 SCKIE31 SCKOE31 SCKO31 SCKI31 Internal data bus PUCR3 VCC 456 ...

Page 461: ...rt 3 Block Diagram Pin P32 P32 VCC VCC PUCR32 Internal data bus PMR32 PDR32 PCR32 SBY VSS PDR3 Port data register 3 PCR3 Port control register 3 PMR3 Port mode register 3 PUCR3 Port pull up control register 3 RESO 457 ...

Page 462: ...ock Diagram Pin P31 VCC VCC VSS PUCR31 PDR31 PCR31 UD SBY Internal data bus PDR3 PCR3 PMR3 PUCR3 Port data register 3 Port control register 3 Port mode register 3 Port pull up control register 3 P31 Timer C module PMR31 458 ...

Page 463: ...Block Diagram Pin P30 P30 VCC VCC PUCR30 PMR30 PDR30 PCR30 SBY VSS PDR3 Port data register 3 PCR3 Port control register 3 PMR3 Port mode register 3 PUCR3 Port pull up control register 3 PWM PWM module Internal data bus 459 ...

Page 464: ...C 3 Block Diagrams of Port 4 Figure C 3 a Port 4 Block Diagram Pin P43 P43 PMR43 Internal data bus IRQ0 PMR4 Port mode register 4 460 ...

Page 465: ...Figure C 3 b Port 4 Block Diagram Pin P42 P42 SCI32 module Internal data bus PDR42 SCINV3 PCR42 SBY VSS PDR4 Port data register 4 PCR4 Port control register 4 TXD32 VCC SPC32 461 ...

Page 466: ...Figure C 3 c Port 4 Block Diagram Pin P41 P41 VCC SCI32 module PDR41 PCR41 SBY VSS PDR4 Port data register 4 PCR4 Port control register 4 RE32 RXD32 Internal data bus SCINV2 462 ...

Page 467: ...Figure C 3 d Port 4 Block Diagram Pin P40 P40 VCC SCI32 module PDR40 PCR40 SBY VSS PDR4 Port data register 4 PCR4 Port control register 4 SCKIE32 SCKOE32 SCKO32 Internal data bus SCKI32 463 ...

Page 468: ...igure C 4 Port 5 Block Diagram P5n VCC VCC PUCR5n Internal data bus PMR5n PDR5n PCR5n SBY VSS WKPn PDR5 Port data register 5 PCR5 Port control register 5 PMR5 Port mode register 5 PUCR5 Port pull up control register 5 n 7 to 0 464 ...

Page 469: ...Diagram of Port 6 Figure C 5 Port 6 Block Diagram P6n VCC VCC PUCR6n PDR6n Internal data bus PCR6n SBY VSS PDR6 Port data register 6 PCR6 Port control register 6 PUCR6 Port pull up control register 6 n 7 to 0 465 ...

Page 470: ...C 6 Block Diagram of Port 7 Figure C 6 Port 7 Block Diagram P7n VCC PDR7n Internal data bus PCR7n SBY VSS PDR7 Port data register 7 PCR7 Port control register 7 n 7 to 0 466 ...

Page 471: ...C 7 Block Diagrams of Port 8 Figure C 7 Port 8 Block Diagram P8n VCC PDR8n Internal data bus PCR8n SBY VSS PDR8 PCR8 n 7 to 0 Port data register 8 Port control register 8 467 ...

Page 472: ...C 8 Block Diagram of Port A Figure C 8 Port A Block Diagram PAn VCC PDRAn Internal data bus PCRAn SBY VSS PDRA Port data register A PCRA Port control register A n 3 to 0 468 ...

Page 473: ...C 9 Block Diagram of Port B Figure C 9 Port B Block Diagram PBn Internal data bus AMR3 to AMR0 A D module VIN n 7 to 0 DEC 469 ...

Page 474: ... High Retained Retained High Retained Functions Functions impedance impedance 1 P67 to P60 High Retained Retained High Retained Functions Functions impedance impedance P77 to P70 High Retained Retained High Retained Functions Functions impedance impedance P87 to P80 High Retained Retained High Retained Functions Functions impedance impedance PA3 to PA0 High Retained Retained High Retained Function...

Page 475: ...P TFP 80C H8 3866 Mask ROM HD6433866H HD6433866 H 80 pin QFP FP 80A versions HD6433866F HD6433866 F 80 pin QFP FP 80B HD6433866W HD6433866 W 80 pin TQFP TFP 80C H8 3867 Mask ROM HD6433867H HD6433867 H 80 pin QFP FP 80A versions HD6433867F HD6433867 F 80 pin QFP FP 80B HD6433867W HD6433867 W 80 pin TQFP TFP 80C ZTAT HD6473867H HD6473867H 80 pin QFP FP 80A versions HD6473867F HD6473867F 80 pin QFP F...

Page 476: ...8 3826 Mask ROM HD6433826H HD6433826 H 80 pin QFP FP 80A versions HD6433826F HD6433826 F 80 pin QFP FP 80B HD6433826W HD6433826 W 80 pin TQFP TFP 80C H8 3827 Mask ROM HD6433827H HD6433827 H 80 pin QFP FP 80A versions HD6433827F HD6433827 F 80 pin QFP FP 80B HD6433827W HD6433827 W 80 pin TQFP TFP 80C ZTAT HD6473827H HD6473827H 80 pin QFP FP 80A versions HD6473827F HD6473827F 80 pin QFP FP 80B HD647...

Page 477: ...nd F 3 below Figure F 1 FP 80A Package Dimensions Hitachi Code JEDEC EIAJ Weight reference value FP 80A Conforms 1 2 g Unit mm Dimension including the plating thickness Base material dimension 60 0 8 0 10 0 12 M 17 2 0 3 41 61 80 1 20 40 21 17 2 0 3 0 32 0 08 0 65 3 05 Max 1 6 0 8 0 3 14 2 70 0 17 0 05 0 10 0 15 0 10 0 83 0 30 0 06 0 15 0 04 473 ...

Page 478: ...ht reference value FP 80B 1 7 g Unit mm Dimension including the plating thickness Base material dimension 0 15 M 0 10 0 37 0 08 0 17 0 05 3 10 Max 1 2 0 2 24 8 0 4 20 64 41 40 25 24 1 80 65 18 8 0 4 14 0 15 0 8 2 70 2 4 0 20 0 10 0 20 0 8 1 0 0 35 0 06 0 15 0 04 474 ...

Page 479: ...ight reference value TFP 80C Conforms 0 4 g Unit mm Dimension including the plating thickness Base material dimension 0 10 M 0 10 0 5 0 1 0 8 1 20 Max 14 0 0 2 0 5 12 14 0 0 2 60 41 1 20 80 61 21 40 0 17 0 05 1 0 0 22 0 05 0 10 0 10 1 00 1 25 0 20 0 04 0 15 0 04 475 ...

Page 480: ...ition November 1997 3rd Edition February 1999 Published by ELectronic Devices Sales Marketing Group Semiconductor Integrated Circuits Group Hitachi Ltd Edited by Technical Documentation Group UL Media Co Ltd Copyright Hitachi Ltd 1997 All rights reserved Printed in Japan ...

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