9.7.5
Application Notes
1.
When reading the values in ECH and ECL, first clear bits CUEH and CUEL to 0 in ECCSR to
prevent asynchronous event input to the counter. The correct value will not be returned if the
event counter increments while being read.
When clear bits CUEH and CUEL to 0 in ECCSR, ECH and ECL sometimes count up.
2.
Use a clock with a frequency of up to 6 MHz (Internal step-down circuit not used: V
CC
= 4.5 to
5.5 V), up to 4 MHz (Internal step-down circuit not used: V
CC
= 3.0 to 5.5 V), up to 3.2 MHz
(internal step-down circuit not used: V
CC
= 2.7 to 5.5 V), up to 2 MHz (V
CC
= 2.2 to 5.5 V),
up to 1 MHz (others) for input to the AEVH and AEVL pins, and ensure that the high and low
widths of the clock are at least 83 ns. The duty cycle is immaterial.
Maximum AEVH/AEVL Pin
Mode
Input Clock Frequency
16-bit mode
Internal step-down circuit
8-bit mode
Active (high-speed), sleep (high-speed)
not used:
V
CC
= 4.5 to 5.5 V/6 MHz
V
CC
= 3.0 to 5.5 V/4 MHz
V
CC
= 2.6 to 5.5 V/3.2 MHz
V
CC
= 2.2 to 5.5 V/2 MHz
Other than above/1 MHz
Internal step-down circuit
used:
V
CC
= 2.2 to 5.5 V/2 MHz
Other than above/1 MHz
8-bit mode
Active (medium-speed), sleep (medium-speed) (ø/16)
2 · f
OSC
(ø/32)
f
OSC
(ø/64)
1/2 · f
OSC
f
OSC
= 400 kHz to 4 MHz
(ø/128)
1/4 · f
OSC
8-bit mode
Watch, subactive, subsleep, standby
(øw/2)
1000 kHz
(øw/4)
500 kHz
øw = 32.768 kHz or 38.4 kHz
(øw/8)
250 kHz
3.
When AEC uses with 16-bit mode, set CUEH in ECCSR to “1” first, set CRCH in ECCSR to
“1” second, or set both CUEH and CRCH to “1” at same time before clock entry. While AEC
is operating on 16-bit mode, do not change CUEH. Otherwise, ECH will be miscounted up.
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