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Hitachi Deskstar T7K500, Specifications

The Hitachi Deskstar T7K500 is a high-performance hard drive designed for reliable and efficient data storage. With a spacious capacity and impressive specifications, this product ensures seamless performance for both personal and professional needs. Its user manual is available for free download from manualshive.com, providing detailed information and instructions for optimal use.

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Deskstar T7K500 Hard Disk Drive Specification

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12.42.4  S.M.A.R.T. Log Directory

The following table defines the 512 bytes that make up the S.M.A.R.T. Log Directory.  The S.M.A.R.T. Log Direc-
tory is S.M.A.R.T. Log Address zero and is defined as one sector long.

Table 144: S.M.A.R.T. Log Directory

The value of the S.M.A.R.T. Logging Version word shall be 01h.  The logs at log addresses 80-9Fh shall each be 
defined as 16 sectors long.

12.42.5  S.M.A.R.T. summary error log sector

The following figure defines the 512 bytes that make up the SMART summary error log sector. All multibyte fields 
shown in this data structure follow the ATA/ATAPI-6 specifications for byte ordering.

Table 145: S.M.A.R.T. summary error log sector  

12.42.5.1  S.M.A.R.T. error log version

This value is set to 01h.

12.42.5.2  Error log pointer

This points to the most recent error log data structure. Only values 1 through 5 are valid.

12.42.5.3  Device error count

This field contains the total number of errors. The value will not roll over.

Description

Byte

Offset

S.M.A.R.T. Logging Version

2

00h

Number of sectors in the log at log address 1

1

02h

Reserved

1

03h

Number of sectors in the log at log address 2

1

04h

Reserved

1

05h

...

...

...

Number of sectors in the log at log address 255

1

1FEh

Reserved

1

1FFH

512

Description

Byte

Offset

S.M.A.R.T. error log version

1

00h

Error log pointer

1

01h

1st error log data structure

90

02h

2nd error log data structure

90

5Ch

3rd error log data structure

90

B6h

4th error log data structure

90

110h

5th error log data structure

90

16Ah

Device error count

2

1C4h

Reserved

57

1C6h

Data structure checksum

1

1FFh

512

Summary of Contents for Deskstar T7K500

Page 1: ...odels HDT725025VLAT80 HDT725025VLA380 HDT725025VLA360 HDT725030VLAT80 HDT725030VLA380 HDT725030VLA360 HDT725032VLAT80 HDT725032VLA380 HDT725032VLA360 HDT725040VLAT80 HDT725040VLA380 HDT725040VLA360 HDT725050VLAT80 HDT725050VLA380 HDT725050VLA360 Version 1 2 06 December 2006 ...

Page 2: ......

Page 3: ...odels HDT725025VLAT80 HDT725025VLA380 HDT725025VLA360 HDT725030VLAT80 HDT725030VLA380 HDT725030VLA360 HDT725032VLAT80 HDT725032VLA380 HDT725032VLA360 HDT725040VLAT80 HDT725040VLA380 HDT725040VLA360 HDT725050VLAT80 HDT725050VLA380 HDT725050VLA360 Version 1 2 06 December 2006 ...

Page 4: ...make improvements or changes in any products or programs described in this publication at any time It is possible that this publication may contain reference to or information about Hitachi products machines and programs programming or services that are not announced in your country Such references or information must not be construed to mean that Hitachi intends to announce such Hitachi products ...

Page 5: ...rhead 15 4 5 2 Mechanical positioning 15 4 5 3 Drive ready time 17 4 5 4 Operating modes 17 5 0 Defect flagging strategy 19 6 0 Electrical interface specification 21 6 1 Connector location 21 6 1 1 4 pin DC power connector 22 6 1 2 AT signal connector 22 6 2 Signal definitions PATA model 23 6 3 Signal descriptions 24 6 4 Interface logic signal levels pata model 27 6 5 Signal definition SATA model ...

Page 6: ...al 52 7 3 3 Power supply generated ripple at drive power connector 53 7 4 Reliability 55 7 4 1 Data integrity 55 7 4 2 Cable noise interference 55 7 4 3 Start stop cycles 55 7 4 4 Preventitive Maintenance 55 7 4 5 Data reliability 55 7 4 6 Required power off sequence 55 7 5 Mechanical specifications 56 7 5 1 Physical dimensions and weight 56 7 5 2 Mounting hole locations 58 7 5 3 Connector locatio...

Page 7: ...rol Register 71 9 8 Drive Address Register 72 9 9 Device Head Register 72 9 10 Error Register 73 9 11 Features Register 73 9 12 Sector Count Register 73 9 13 Sector Number Register 74 9 14 Status Register 74 10 0 General operation 77 10 1 Reset response 77 10 2 Register initialization 78 10 3 Diagnostic and Reset considerations 79 10 4 Sector Addressing Mode 80 10 4 1 Logical CHS addressing mode 8...

Page 8: ...ss Offset Feature 100 10 15 1 Enable Disable Address Offset Mode 100 10 15 2 Identify Device Data 101 10 15 3 Exceptions in Address Offset Mode 101 10 16 48 bit Address Feature Set 102 10 17 Streaming feature Set 102 10 17 1 Streaming commands 103 10 17 2 Urgent bit 103 10 17 3 Flush to Disk bit 103 10 17 4 Not Sequential bit 103 10 17 5 Read Continuous bit 104 10 17 6 Write Continuous bit 104 10 ...

Page 9: ...nded Comprehensive SMART Error Log 170 12 17 3 Extended Self test log sector 172 12 17 4 Read Stream Error Log 173 12 17 5 Write Stream Error Log 175 12 17 6 Streaming Performance Log 176 12 18 Read Long 22h 23h 178 12 19 Read Multiple C4h 180 12 20 Read Multiple Ext 29h 181 12 21 Read Native Max ADDRESS F8h 183 12 22 Read Native Max Address Ext 27h 184 12 23 Read Sectors 20h 21h 185 12 24 Read Se...

Page 10: ...Thresholds data structure 233 12 42 4 S M A R T Log Directory 235 12 42 5 S M A R T summary error log sector 235 12 42 6 Self test log data structure 237 12 42 7 Selective self test log data structure 238 12 42 8 Error reporting 239 12 43 Standby E2h 96h 241 12 44 Standby Immediate E0h 94h 243 12 45 Write Buffer E8h 244 12 46 Write DMA CAh CBh 245 12 47 Write DMA Ext 35h 247 12 48 Write DMA FUA Ex...

Page 11: ...cle timing chart Host pausing Read 34 Table 24 Ultra DMA cycle timings Host pausing Read 34 Table 25 Ultra DMA cycle timing chart Host pausing Read 35 Table 26 Ultra DMA cycle timings Device Terminating Read 35 Table 27 Ultra DMA cycle timing chart Initiating Write 36 Table 28 Ultra DMA cycle timing chart Device Pausing Write 37 Table 29 Ultra DMA cycle timings Device Pausing Write 37 Table 30 Ult...

Page 12: ...7 Command Set subcommand 132 Table 68 Check Power Mode command E5h 98h 134 Table 69 Configure Stream 51h 135 Table 70 Check Power Mode Command E5h 98h 137 Table 71 Device Configuration Overlay Features register values 137 Table 72 Device Configuration Overlay Data structure 139 Table 73 DCO error information definition 140 Table 74 Downlad Microcode Command 92h 141 Table 75 Execute Device Diagnost...

Page 13: ...4 Table 111 Read Sectors Command 20h 21h 185 Table 112 Read Sector s Ext command 24h 187 Table 113 Read Stream DMA Command 2Ah 189 Table 114 Read Stream PIO 2Bh 193 Table 115 Read Verify Sectors 40h 41h 196 Table 116 Read Verify Sectors Ext command 42h 198 Table 117 Recalibrate 1xh 200 Table 118 Security Disable Password F6h 201 Table 119 Password Information for Security Disable Password command ...

Page 14: ... data structure 236 Table 147 Error data structure 236 Table 148 Self test log data structure 237 Table 149 Selective self test log data structure 239 Table 150 S M A R T Error Codes 239 Table 151 Standby E2h 96h 241 Table 152 Standby Immediate E0h 94h 243 Table 153 Write Buffer E8h 244 Table 154 Write DMA CAh CBh 245 Table 155 Write DMA Ext Command 35h 247 Table 156 Write Log Ext Command 3Fh 251 ...

Page 15: ...g A Ampere AC alternating current ADM Automatic Drive Maintenance AT Advanced Technology ATA Advanced Technology Attachment BIOS Basic Input Output System C Celsius CSA Canadian Standards Association C UL Canadian Underwriters Laboratory Cyl cylinder DC Direct Current DFT Drive Fitness Test DMA Direct Memory Access ECC error correction code EEC European Economic Community EMC electromagnetic compa...

Page 16: ...its per inch kgf cm kilogram force centimeter KHz kilohertz LBA logical block addressing Lw unit of A weighted sound power m meter max maximum MB 1 000 000 bytes Mbps 1 000 000 bits per second MHz megahertz MLC Machine Level Control mm millimeter ms millisecond us ms microsecond O Output OD Open Drain Programmed Input Output POH power on hours Pop population P N part number p p peak to peak PSD po...

Page 17: ...utscher Electrotechniker W watt 3 state transistor transistor tristate logic 1 4 Caution Do not apply force to the top cover Do not cover the breathing hole on the top cover Do not touch the interface connector pins or the surface of the printed circuit board This drive can be damaged by electrostatic discharge ESD Any damages incurred to the drive after its removal from the shipping package and t...

Page 18: ...Deskstar T7K500 Hard Disk Drive Specification 4 ...

Page 19: ...implementation Write Cache Native command queuing support SATA model Advanced ECC On The Fly EOF Automatic Error Recovery procedures for read and write commands Self Diagnostics on Power on and resident diagnostics PIO Data Transfer Mode 4 16 6 MB s DMA Data Transfer Multiword mode Mode 2 16 6 MB s Ultra DMA Mode 6 133 MB s Serial ATA Data Transfer 3Gbps 1 5Gbps CHS and LBA mode Power saving modes...

Page 20: ...Deskstar T7K500 Hard Disk Drive Specification 6 ...

Page 21: ...Deskstar T7K500 Hard Disk Drive specification 7 Part 1 Functional specification ...

Page 22: ...Deskstar T7K500 Hard Disk Drive Specification 8 ...

Page 23: ...itions of the servo and takes corresponding action if an error occurs Monitors various timers such as head settle and servo failure Performs self checkout diagnostics 3 2 Head disk assembly The head disk assembly HDA is assembled in a clean room environment and contains the disks and actuator assembly Air is constantly circulated and filtered when the drive is operational Venting of the HDA is acc...

Page 24: ...Deskstar T7K500 Hard Disk Drive Specification 10 ...

Page 25: ...heads 16 16 16 Number of Sectors per track 63 63 63 Number of Cylinders2 16 383 16 383 16 383 Number of sectors 488 397 168 586 072 368 625 142 448 Total logical data bytes 250 059 350 016 300 069 052 416 320 072 933 376 Description HDT725040VLxxxx HDT725050VLxxxx Physical Layout Label capacity GB 400 500 Bytes per sector 512 512 Sectors per track 672 1320 720 1500 Number of heads 6 6 Number of di...

Page 26: ...ecification 2 Logical layout Logical layout is an imaginary drive parameter that is the number of heads which is used to access the drive from the system interface The logical layout to Physical layout that is the actual Head and Sec tors translation is done automatically in the drive The default setting can be obtained by issuing an IDENTIFY DEVICE command 3 The 300 GB model is capacity clip mode...

Page 27: ...ta transfer rates Mbps 824 957 848 998 Interface transfer rates Mb s 133 PATA 300 SATA Data buffer size1 KB 8192 16384 Rotational speed RPM 7200 Number of buffer segments read up to 128 Number of buffer segments write up to 63 Recording density max Kbpi 762 837 768 872 Track density KTPI 125 135 125 135 Areal density max Gbits in2 95 113 96 118 Number of data bands 30 Table 3 Word Wide Name Assign...

Page 28: ...cal CHS Depending on the capacity some of the inner zone cylinders are not allocated Data cylinder This cylinder contains the user data which can be sent and retrieved via read write commands and a spare area for reassigned data Spare cylinder The spare cylinder is used by Hitachi Global Storage Technologies manufacturing and includes data sent from a defect location ...

Page 29: ...mmand is written into the command regis ter by a host to the assertion of DRQ for the first data byte of a READ command when the requested data is not in the buffer excluding Physical seek time and Latency The table below gives average command overhead 4 5 2 Mechanical positioning 4 5 2 1 Average seek time without command overhead including settling Table 4 Command overhead Command type Drive is i...

Page 30: ...ighted Average max 1 max where max Maximum seek length n Seek length 1 to max Tnin Inward measured seek time for an n track seek Tnout Outward measured seek time for an n track seek 4 5 2 2 Full stroke seek time without command overhead including settling Full stroke seek is measured as the average of 1 000 full stroke seeks with a random head switch from both direc tions inward and outward 4 5 2 ...

Page 31: ...e Rotational speed RPM Time for one revolution ms Average latency ms 7200 RPM 8 3 4 17 Table 9 Drive ready time Power on to ready Typical sec Maximum sec 250 320 GB models 10 20 400 500 GB models 14 20 Table 10 Description of operating modes Operating mode Description Spin up Start up time period from spindle stop or power down Seek Seek operation mode Write Write operation mode Read Read operatio...

Page 32: ...g the seconds passed until the spindle motor stops Table 11 Mode transition times From To RPM Transition time sec Typical Maximum Standby Idle 0 7200 3 disks 10 20 Idle Standby 7200 0 Immediately Immediately Standby Sleep 0 Immediately Immediately Sleep Standby 0 Immediately Immediately Unload idle Idle 7200 0 7 1 Idle Unload idle 7200 0 7 1 Low RPM Idle Idle 4500 7200 4 2D 6 3D 10 ...

Page 33: ...ysical locations is calculated by an internally maintained table Shipped format Data areas are optimally used No extra sector is wasted as a spare throughout user data areas All pushes generated by defects are absorbed by the spare tracks of the inner zone Table 12 PATA Plist physical format Defects are skipped without any constraint such as track or cylinder boundary N N 1 N 2 N 3 defect defect s...

Page 34: ...Deskstar T7K500 Hard Disk Drive Specification 20 ...

Page 35: ...Deskstar T7K500 Hard Disk Drive Specification 21 6 0 Electrical interface specification 6 1 Connector location Refer to the following illustration to see the location of the connectors PATA SATA ...

Page 36: ... designed to mate with AMP part number 1 480424 0 using AMP pins part number 350078 4 strip part number 61173 4 loose piece or their equivalents Pin assignments are shown in the figure below 6 1 2 AT signal connector The AT signal connector is a 40 pin connector 4 3 2 1 Pin Voltage 1 12 V 2 GND 3 GND 4 5V ...

Page 37: ...e DMA burst Table 13 Signal definitions PIN SIGNAL I O Type PIN SIGNAL I O Type 01 RESET I TTL 02 GND 03 DD7 I O 3 state 04 DD08 I O 3 state 05 DD6 I O 3 state 06 DD09 I O 3 state 07 DD5 I O 3 state 08 DD10 I O 3 state 09 DD4 I O 3 state 10 DD11 I O 3 state 11 DD3 I O 3 state 12 DD12 I O 3 state 13 DD2 I O 3 state 14 DD13 I O 3 state 15 DD1 I O 3 state 16 DD14 I O 3 state 17 DD0 I O 3 state 18 DD1...

Page 38: ...lected See Table 34 I O address map on page 40 RESET This line is used to reset the drive It shall be kept at a Low logic state during power up and kept High thereafter DIOW The rising edge of this signal holds data from the data bus to a register or data register of the drive DIOR When this signal is low it enables data from a register or data register of the drive onto the data bus The data on t...

Page 39: ...ndicate that it is no longer busy and is able to provide status Following the receipt of a valid Execute Drive Diagnostics command device 1 shall negate PDIAG within 1 ms to indicate to device 0 that it is busy and has not yet passed its drive diagnostics If device 1 is present then device 0 shall wait up to 6 seconds from the receipt of a valid Execute Drive Diagnostics command for drive 1 to ass...

Page 40: ...rising and falling edge of HSTROBE latch the data from DD 15 0 into the device The host may stop toggling HSTROBE to pause an Ultra DMA data out transfer STOP Ultra DMA This signal is used only for Ultra DMA data transfers between host and drive The STOP signal shall be asserted by the host prior to initiation of an Ultra DMA burst A STOP shall be negated by the host before data is transferred in ...

Page 41: ...e 2 4 V min 0 5 V max No Plug Connector pin definition Signal I O S1 GND 2nd mate Gnd S2 A Differential signal A from Phy RX Input S3 A RX Input Signal S4 Gnd 2nd mate Gnd S5 B Differential signal B from Phy TX Output S6 B TX Output S7 Gnd 2nd mate Gnd Key and spacing separate signal and power segments P1 V33 3 3V power 3 3V P2 V33 3 3V power 3 3V P3 V33 3 3V power pre charge 2nd Mate 3 3V P4 Gnd ...

Page 42: ...l be referenced about signal specifications Serial ATA High Speed Serialized AT Attachment Revision 1 0a 7 January 2003 Serial ATA II Electrical Specification 1 0 26 May 2004 Serial ATA II Extensions to Serial ATA 1 0a Rev 1 2 27 Aug 2004 6 5 3 Out of band signaling SATA model PARAMETER DESCRIPTION Nominal ns t1 ALINE primitives 106 7 t2 Spacing 320 t3 ALIGN primitives 106 7 t4 Psacing 106 7 ...

Page 43: ... Disk Drive Specification 29 6 6 Reset timings Table 15 System reset timing chart Table 16 System reset timing PARAMETER DESCRIPTION Min usec Max sec t10 RESET low width 25 t14 RESET high to not BUSY 31 t10 t14 RESET BUSY ...

Page 44: ... the next DRQ bit 6 7 2 Read DRQ interval time For read sectors and read multiple operations the interval from the end of negation of the DRQ bit until setting of the next DRQ bit is as follows PARAMETER DESCRIPTION MIN ns MAX ns t0 Cycle time 120 t1 Address valid to DIOR DIOW setup 25 t2 DIOR DIOW pulse width 70 t2i DIOR DIOW recovery time 25 t3 DIOW data setup 20 t4 DIOW data hold 10 t5 DIOR dat...

Page 45: ...API 6 description Table 18 Multiword DMA cycle timing chart Table 19 Multiword DMA cycle timings PARAMETER DESCRIPTION MIN ns MAX ns t0 Cycle time 120 tD DIOR DIOW asserted pulse width 70 tE DIOR data access 50 tF DIOR data hold 5 tG DIOR DIOW data setup 20 tH DIOW data hold 10 tI DMACK to DIOR DIOW setup 0 tJ DIOR DIOW to DMACK hold 5 tKR tKW DIOR DIOW negated pulse width 25 tLR tLW DIOR DIOW to ...

Page 46: ... ORDY Minimum time before driving IORDY 0 0 0 0 0 0 0 tFS First DSTROBE time 0 230 0 200 0 170 0 130 0 120 90 0 80 tCYC Cycle time 112 73 54 39 25 17 13 t2CYC Two cycle time 230 154 115 86 57 38 29 tAZ Maximum time allowed for output drivers to release 10 10 10 10 10 10 10 tZAD Drivers to assert 0 0 0 0 0 0 0 tDS Data setup time at host 15 10 7 7 5 4 8 2 6 tDH Data hold time at host 5 5 5 5 5 4 8 ...

Page 47: ...hen a host does not satisfy tSR timing it should be ready to receive two more data words after HDMARDY is negated PARAMETER DESCRIPTION all values in ns MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tSR DSTROBE to HDMARDY time 50 30 20 tRFS HDMARDY to final DSTROBE time 75 70 60 60 60 50 50 DSTROBE HDMARDY DMACK DMARQ tSR STOP tRFS ...

Page 48: ...imited interlock time 0 150 0 150 0 150 0 100 0 100 0 75 0 60 tAZ Maximum time allowed for output drivers to release 10 10 10 10 10 10 10 tZAH Minimum delay time required for output 20 20 20 20 20 20 20 tMLI Interlock time with minimum 20 20 20 20 20 20 20 tCS CRC word setup time at device 15 10 7 7 5 5 5 tCH CRC word hold time at device 5 5 5 5 5 5 5 tACK Hold time for DMACK 20 20 20 20 20 20 20 ...

Page 49: ...terlock time 0 150 0 150 0 150 0 100 0 100 0 75 0 60 tAZ Maximum time allowed for output drivers to release 10 10 10 10 10 10 10 tZAH Maximum delay time required for output 20 20 20 20 20 20 20 tMLI Interlock time with minimum 20 20 20 20 20 20 20 tCS CRC word setup time at device 15 10 7 7 5 5 5 tCH CRC word hold time at device 5 5 5 5 5 5 5 tACK Hold time for DMACK 20 20 20 20 20 20 20 tIORDYZ M...

Page 50: ...0 20 20 20 tENV Envelope time 20 70 20 70 20 70 20 55 20 55 20 55 20 50 tZIORDY Minimum time before driving IORDY 0 0 0 0 0 0 0 tLI Limited interlock time 0 150 0 150 0 150 0 100 0 100 0 75 0 60 tCYC Cycle time 112 73 54 39 25 16 8 13 0 t2CYC Two cycle time 230 154 115 86 57 38 29 tDS Data setup time at device 15 10 7 7 5 4 2 6 tDH Data Hold time at device 5 5 5 5 5 4 6 3 5 HSTROBE DDMARDY DMACK D...

Page 51: ...e When a device does not satisfy the tSR timing it shall be ready to receive two more strobes after DDMARDY is negated PARAMETER DESCRIPTION all values in ns MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tSR HSTROBE to DDMARDY time 50 30 20 tRFS DDMARDY to final HSTROBE time 75 70 60 60 60 50 50 HSTROBE DDMARDY DMACK DMARQ tSR STOP tRFS ...

Page 52: ...BE time 75 70 60 60 60 50 50 tRP Ready to pause time 160 125 100 100 100 85 85 tLI Limited interlock time 0 150 0 150 0 150 0 100 0 100 0 75 0 60 tMLI Interlocking time with minimum 20 20 20 20 20 20 20 tCS CRC word setup time at device 15 10 7 7 5 5 5 tCH CRC word hold time at device 5 5 5 5 5 5 5 tACK Hold time for DMACK negation 20 20 20 20 20 20 20 tIORDYZ Maximum time before releasing IORDY 2...

Page 53: ...ime from HSTROBE edge to assertion of STOP 50 50 50 50 50 50 50 tLI Limited interlock time 0 150 0 150 0 150 0 100 0 100 0 75 0 60 tMLI Interlock time with mini mum 20 20 20 20 20 20 20 tCS CRC word setup time at device 15 10 7 7 5 5 5 tCH CRC word hold time at device 5 5 5 5 5 5 5 tACK Hold time for DMACK 20 20 20 20 20 20 20 tIO RDYZ Maximum time before releasing IORDY 20 20 20 20 20 20 20 HSTRO...

Page 54: ...ents before interrupt the value is invalid 6 10 1 Cabling The maximum cable length from the host system to the drive plus circuit pattern length in the host system shall not exceed 18 inches For higher data transfer application 8 3 MB s a modification in the system design is recommended to reduce cable noise and cross talk such as a shorter cable bus termination or a shielded cable For systems ope...

Page 55: ...Deskstar T7K500 Hard Disk Drive Specification 41 Part 2 Interface specification ...

Page 56: ...Deskstar T7K500 Hard Disk Drive Specification 42 ...

Page 57: ...per settings 7 1 1 Jumper pin location 7 1 2 Jumper pin identification 7 1 3 Jumper pin assignment There are four jumper settings as shown in the following sections 16 logical head default normal use 15 logical head default 32 GB clip Jumper pins Pin A Pin B Pin I DERA001 prz ...

Page 58: ...ice 1 Cable Selection or Device 1 Slave Present as shown in the following figures The Device 0 setting automatically recognizes device 1 if it is present The Device 1 Slave Present setting is for a slave device that does not comply with the ATA specification Note In conventional terminology Device 0 designates a Master and Device 1 designates a Slave ...

Page 59: ...the jumper positions used to select Device 0 Device 1 Cable Selection or Device1 Slave Present GND DS I G E C A H D B F RSV GND GND RSV CS SP GND RSV G I E C A H F D B DEVICE 0 Master G I E C A H F D B DEVICE 1 Slave G I E C A H F D B CABLE SEL G I E C A H F D B DEVICE 1 Slave Present G I E C A H F D B Shipping Default Condition CABLE SEL ...

Page 60: ...ows the jumper positions used to select Device 0 Device 1 Cable Selection or Device1 Slave Present setting 15 logical heads instead of default 16 logical head models Notes 1 To enable the CSEL mode Cable Selection mode the jumper block must be installed at E F In the CSEL mode the drive address is determined by AT interface signal 28 CSEL as follows When CSEL is grounded or at a low level the driv...

Page 61: ... clips the LBA to 66055248 The CHS is unchanged from the factory default of 16383 16 63 7 1 4 4 Power up in Standby The figure below shows the jumper positions used to select Device 0 Device 1 Cable Selection or Device1 Slave Present to enable Power Up In Standby Table 36 Jumper settings for Disabling Auto Spin G I E C A H F D B DEVICE 0 Master G I E C A H F D B DEVICE 1 Slave G I E C A H F D B CA...

Page 62: ... SET FEATURES subcommand 07h Refer to 12 28 Set Features 3 To enable the CSEL mode Cable Selection mode the jumper block must be installed at E F In the CSEL mode the drive address is determined by AT interface signal 28 CSEL as follows When CSEL is grounded or at a low level the drive address is 0 Device 0 When CSEL is open or at a high level the drive address is 1 Device 1 ...

Page 63: ...aintained at any time Maximum storage period within shipping package is one year Table 37 Temperature and humidity Operating conditions Temperature 0C to 60ºC See note below Relative humidity 8 to 90 non condensing Maximum wet bulb temperature 29 4ºC non condensing Maximum temperature gradient 20ºC hour Altitude 300 to 3 048 m Non operating conditions Temperature 40C to 65ºC Relative humidity 5 to...

Page 64: ...y 7 3 DC power requirements Damage to the drive electronics may result if the power supply cable is connected or disconnected to the legacy Power connector while power is being applied to the drive no hot plug unplug is allowed If SATA power supply cable is connected or disconnected to the SATA power connector hot plug unplug is allowed 40 20 0 20 40 60 Temperature C 0 10 20 30 40 50 60 70 80 90 1...

Page 65: ...wer supply voltage spikes must not exceed specifications 2 12V should be applied within 60 seconds after 5V is applied to the drive Table 39 Input voltage Input voltage supply2 During run and spin up Absolute max spike voltage1 Supply rise time 5 V 5 V 5 0 3 to 5 5 V 0 to 5 sec 12 V 12 V 10 8 0 3 to 15 V 0 to 5 sec ...

Page 66: ...ilent R W average 530 10 440 10 Silent R W peak 1600 30 1000 30 7 9 Start up max 1050 30 2000 30 Standby average 140 4 12 2 0 8 Sleep average 100 4 12 2 0 6 Power supply current of 250 300 320 GB PATA models 5 Volts mA 12 Volts mA values in milliamps RMS Pop Mean Std Dev Pop Mean Std Dev Total W Idle average 300 4 300 4 Idle ripple peak to peak 450 10 400 10 5 0 Low RPM Idle 140 4 130 4 Low RPM Id...

Page 67: ... 1 730 10 640 20 Random R W peak 1800 30 1700 30 11 3 Silent R W average 730 10 440 10 Silent R W peak 1800 30 1000 30 8 9 Start up max 1250 30 2000 30 Standby average 340 4 12 2 1 8 Sleep average 300 4 12 2 1 6 Power supply current of 250 300 320 GB SATA models 5 Volts mA 12 Volts mA values in milliamps RMS Pop Mean Std Dev Pop Mean Std Dev Total W Idle average 500 4 300 4 Idle ripple peak to pea...

Page 68: ...s must remain within the above regulation tolerance A common supply with separate power leads to each drive is a more desirable method of power distribution To prevent external electrical noise from interfering with the performance of the drive the drive must be held by four screws in a user system frame which has no electrical level difference at the four screws position and has less than 300 mil...

Page 69: ...op cycles in a 40 C environment and a minimum of 10 000 start stop cycles in extreme temperature or humidity within the operating range 7 4 4 Preventitive Maintenance None 7 4 5 Data reliability Probability of not recovering data is 1 in 1014 bits read ECC On The Fly correction 1 Symbol 10 bits 1 Interleave 34 ECCs are embedded into each interleave This implementation always recovers 16 random bur...

Page 70: ...Deskstar T7K500 Hard Disk Drive Specification 56 7 5 Mechanical specifications 7 5 1 Physical dimensions and weight ...

Page 71: ...breather hole must be kept uncovered in order to keep the air pressure inside of the disk enclosure equal to external air pressure The following table lists the dimensions of the drive Table 42 Physical dimensions and weight Height mm 26 1 Max Width mm 101 6 0 25 Length mm 147 0 Max Weight grams maximum 640 ...

Page 72: ...mounting hole locations and size of the drive are shown below All dimensions are in mm Thread 1 2 3 4 5 6 7 6 32 UNC 41 28 0 5 44 45 0 2 95 25 0 2 6 35 0 2 28 5 0 5 60 0 0 2 41 6 0 2 Side View 5 6 7 Bottom View 1 2 3 4 I F Connector 4X Max penetration 4 0 mm 6X Max penetration 4 5 mm ...

Page 73: ...Deskstar T7K500 Hard Disk Drive Specification 59 7 5 3 Connector locations 3X 5 08 0 1 4 6 0 5 42 73 REF 13 43 REF 33 39 4 SATA model ...

Page 74: ...ppropriate screws or equivalent mounting hardware The recommended mounting screw torque is 0 6 1 0 Nm 6 10 Kgf cm The recommended mounting screw depth is 4 mm maximum for bottom and 4 5 mm maximum for horizontal mounting Drive level vibration test and shock test are to be conducted with the drive mounted to the table using the bottom four screws 7 5 5 Heads unload and actuator lock The head load u...

Page 75: ...r resonances No data loss occurs with 1 G 0 to peak 5 to 300 to 5 Hz sine wave 0 5 oct min sweep rate with 3 minute dwells at two major resonances 7 6 2 Nonoperating vibration The drive does not sustain permanent damage or loss of previously recorded data after being subjected to the envi ronment described below 7 6 2 1 Random vibration The test consists of a random vibration applied in each of th...

Page 76: ...ate with no degradation of performance after being subjected to shock pulses with the following characteristics 7 6 4 1 Trapezoidal shock wave Approximate square trapezoidal pulse shape Approximate rise and fall time of pulse is 1 ms Average acceleration level is 50 G Average response curve value during the time following the 1 ms rise time and before the 1 ms fall with a time duration of 11 ms Mi...

Page 77: ...eek rate 0 4 average seek time dwell time 7 8 Identification labels The following labels are affixed to every drive A label containing the Hitachi logo the Hitachi Global Storage Technologies part number and the statement Made by Hitachi Global Storage Technologies Inc or Hitachi Global Storage Technol ogies approved equivalent A label containing the drive model number the manufacturing date code ...

Page 78: ...Safe handling The product is conditioned for safe handling in regards to sharp edges and corners 7 9 5 Environment The product does not contain any known or suspected carcinogens Environmental controls meet or exceed all applicable government regulations in the country of origin Safe chemi cal usage and manufacturing control are used to protect the environment An environmental impact assessment ha...

Page 79: ... the approximation of laws of the Member States relating to electromagnetic compatibility 7 10 2 C TICK mark The product complies with the following Australian EMC standard Limits and methods of measurement of radio disturbance characteristics of information technology AS NZS 3548 1995 Class B 7 10 3 BSMI mark The product complies with the Taiwan EMC standard Limits and methods of measurement of r...

Page 80: ...Deskstar T7K500 Hard Disk Drive Specification 66 ...

Page 81: ...eset Refer to section 7 1 Reset response on page 55 for details Download Download command is aborted when teh device is in security locked mode Streaming Commands When the device is in standby mode Streaming Commands can t be completed while waiting for the spindle to reach operating speed even if execution time exceeds specified CCTL Command Completion Time Limit The minimum CCTL is 50ms CCTL is ...

Page 82: ...Deskstar T7K500 Hard Disk Drive Specification 68 ...

Page 83: ...ternate status Addresses Functions CS0 CS1 DA2 DA1 DA0 READ DIOR WRITE DIOW N N x x x Data bus high impedance Not used Control block registers N A 0 x x Data bus high impedance Not used N A 1 0 x Data bus high impedance Not used N A 1 1 0 Alternate Status Device Control N A 1 1 1 Device Address Not used Command block registers A N 0 0 0 Data Data A N 0 0 1 Error Register Features A N 0 1 0 Sector ...

Page 84: ...nd of the com mand this register is updated to reflect the current cylinder number In LBA Mode this register contains Bits 16 23 At the end of the command this register is updated to reflect the current LBA Bits 16 23 The cylinder number may be from zero to the number of cylinders minus one When 48 bit addressing commands are used the most recently written content contains LBA Bits 16 23 and the p...

Page 85: ... DRQ 1 is in the Status Register 9 7 Device Control Register Table 51 Device Control Register 7 6 5 4 3 2 1 0 HOB 1 SRST IEN 0 Bit Definitions HOB HOB high order byte is defined by the 48 bit Address feature set A write to any Command Register shall clear the HOB bit to zero SRST Software Reset The device is held at reset when RST 1 Setting RST 0 again enables the device To ensure that the device ...

Page 86: ...ast significant DS1 Drive Select 1 The Drive Select bit for device 1 is active low DS1 0 when device 1 slave is selected and active DS0 Drive Select 0 The Drive Select bit for device 0 is active low DS0 0 when device 0 master is selected and active 7 6 5 4 3 2 1 0 1 L 1 DRV HS3 HS2 HS1 HS0 L Binary encoded address mode select When L 0 addressing is by CHS mode When L 1 addressing is by LBA mode DR...

Page 87: ... specified If the register is zero at command completion the command was successful If it is not successfully completed the register contains the number of sectors which need to be transferred in order to complete the request The contents of the register are defined otherwise on some commands These definitions are given in the command descriptions 7 6 5 4 3 2 1 0 CRC UNC 0 IDNF 0 ABRT TK0NF AMNF B...

Page 88: ...gisters The host should not read or write any registers when BSY 1 If the host reads any register when BSY 1 the contents of the Status Register will be returned DRDY RDY Device Ready RDY 1 indicates that the device is capable of responding to a command RDY will be set to zero during power on until the device is ready to accept a command If the device detects an error while processing a command RD...

Page 89: ...ee it set to 1 even if the host is continuously reading the Status Register Therefore the host should not attempt to use IDX for timing purposes ERR Error ERR 1 indicates that an error occurred during execution of the previous command The Error Register should be read to determine the error type The device sets bit ERR 0 when the next command is received from the host ...

Page 90: ...Deskstar T7K500 Hard Disk Drive Specification 76 ...

Page 91: ...sponse table POR hard reset soft reset Aborting Host interface O O Aborting Device operation 1 1 Initialization of hardware O X X Internal diagnostic O X X Spinning spindle O X X Initialization of registers 2 O O O DASP handshake O O X PDIAG handshake O O O Reverting programmed parameters to default Number of CHS set by Initialize Device Parameters Multiple mode Write Cache Read look ahead ECC byt...

Page 92: ...rd reset or the Execute Device Diagnostic command is shown in the figure below Table 57 Default Register Values Register Default Value Error Diagnostic Code Sector Count 01h Sector Number 01h Cylinder Low 00h Cylinder High 00h Device Head A0h Status 50h Alternate Status 50h Table 58 Diagnostic codes Code Description 01h No error detected 02h Formatter device error 03h Sector buffer error 04h ECC c...

Page 93: ...ce 0 may assert DASP to indicate device activity Hard Reset Soft Reset If Device 1 is present Device 0 shall read PDIAG to determine when it is valid to clear the BSY bit and whether Device 1 has reset without any errors otherwise Device 0 shall simply reset and clear the BSY bit DASP is asserted by Device 0 and Device 1 if it is present in order to indicate device active Execute Device Diagnostic...

Page 94: ...mbered from 0 to the maximum value allowed by the current CHS translation mode but cannot exceed 65535 0FFFFh When the host selects a CHS translation mode using the INITIALIZE DEVICE PARAMETERS command the host requests the number of sectors per logical track and the number of heads per logical cylinder The device then computes the number of logical cylinders available in requested mode The defaul...

Page 95: ...ed Sleep Mode The lowest power consumption when the device is powered on occurs in Sleep Mode When in Sleep Mode the device requires a reset to be activated Standby Mode The device interface is capable of accepting commands but since the media may not be immediately accessible there is a delay while waiting for the spindle to reach operating speed Idle Mode In Idle Mode the device is capable of re...

Page 96: ...physical interface as defined in the following table Ready RDY is not a power condition A device may post ready at the interface even though the media may not be accessible Table 60 Power conditions Mode BSY RDY Interface active Media Active x x Yes Active Idle o 1 Yes Active Standby o 1 Yes Inactive Sleep x x No Inactive ...

Page 97: ...xisting Accordingly lower attribute values indicate that the analysis algorithms being used by the device are predicting a higher probability of a degrading or faulty condition 10 6 3 Attribute thresholds Each attribute value has a corresponding attribute threshold limit which is used for direct comparison to the attribute value to indicate the existence of a degrading or faulty condition The nume...

Page 98: ...are modification all error log data is discarded and the device error count for the life of the device is reset to zero 10 6 8 Self test The device provides the self test features which are initiated by SMART Execute Off line Immediate command The self test checks the fault of the device reports the test status in Device Attributes Data and stores the test result in the SMART self test log sector ...

Page 99: ...n Media access commands are enabled by either a Security Unlock command or a Security Erase Unit command Device Unlocked Mode The device enables all commands If a password is not set this mode is entered after power on otherwise it is entered by a Security Unlock or a Security Erase Unit command Device Frozen Mode The device enables all commands except those which can update the device lock functi...

Page 100: ...e Lock Function The Master Password Revision Code is set to FFFEh as shipping default by the drive manufacturer Master Password When the Master Password is set the device does NOT enable the Device Lock Function and the device CANNOT be locked with the Master Password but the Master Password can be used for unlocking the locked device Identify Device Information word 92 contains the value of the M...

Page 101: ...is powered on Table 61 Initial setting 10 7 4 3 Operation from POR after user password is set When Device Lock Function is enabled the device rejects media access command until a Security Unlock command Setting password POR Set Password with User Password Normal operation Power off Device locked mode POR No setting password POR Normal operation Power off Device unlocked mode POR ...

Page 102: ...ocked mode Unlock CMD Command 1 Command 1 Password Erase Unit Password Match Reject Complete Complete Erase Unit Lock function Disable Normal operation All commands are available Freeze Lock command Enter Device Frozen mode Normal Operation expect Set Password Disable Password Erase Unit Unlock commands Enter Device Unlock mode N Y N Y Erase Prepare Media Access Non media Access Match ...

Page 103: ...e SECURITY UNLOCK command has an attempt limit the purpose of which is to prevent attempts to unlock the drive with various passwords numerous times The device counts the password mismatch If the password does not match the device counts it without distinguishing the Master password and the User password If the count reaches 5 EXPIRE bit bit 4 of Word 128 in Identify Device information is set and ...

Page 104: ...cutable Executable Executable Idle Executable Executable Executable Idle Immediate Executable Executable Executable Initialize Device Parameters Executable Executable Executable Read Buffer Executable Executable Executable Read DMA Command aborted Executable Executable Read DMA Ext Command aborted Executable Executable Read Log Ext Command aborted Executable Executable Read Long Command aborted Ex...

Page 105: ...le Executable SMART Read Attribute Values Executable Executable Executable SMART Read Attribute Thresholds Executable Executable Executable SMART Return Status Executable Executable Executable SMART Save Attribute Values Executable Executable Executable SMART Read Log Sector Executable Executable Executable SMART Write Log Sector Executable Executable Executable SMART Enable Disable Automatic Off ...

Page 106: ...e is as follows i Issue a Read Native Max ADDRESS command to get the real device maximum LBA Returned value shows that native device maximum LBA is 12 692 735 C1ACFFh regardless of the current setting ii Make the entire device accessible including the protected area by setting the device maximum LBA to 12 692 735 C1ACFFh via Set Max ADDRESS command The option may be either nonvolatile or volatile ...

Page 107: ...et Max Lock Set Max Freeze Lock Set Max Unlock The Set Max Set Password command allows the host to define the password to be used during the current power on cycle The password does not persist over a power cycle but does persist over a hardware or software reset This password is not related to the password used for the Security Mode Feature set When the password is set the device is in the Set_Ma...

Page 108: ...rom the host however the actual seek operation for the next seek command starts immediately after the actual seek operation for the first seek command is completed In other words the execution of two seek commands overlaps excluding the time required for the actual seek operation With this overlap the total elapsed time for a number of seek commands results in the total accumulated time for actual...

Page 109: ...he data onto the disk While writing data after completed acknowledgment of a write command soft reset or hard reset does not affect its operation However power off terminates the writing operation immediately and unwritten data is lost The Soft reset Standby Immediate command and Flush Cache commands during the writing of the cached data are executed after the completion of writing to media So the...

Page 110: ...ecovered write errors When a write operation cannot be completed after the Error Recovery Procedure ERP is fully carried out the sector s are reallocated to the spare location An error is reported to the host system only when the write cache is disabled and the auto reallocation has failed If the Write Cache function is ENABLED when the number of available spare sectors reaches 0 sector both Auto ...

Page 111: ...after power cycle A device needs a SET FEATURES subcommand to spin up to active state when the device has powered up into Standby The device remains in Standby until the SET FEATURES subcommand is received If power up into Standby is enabled when an IDENTIFY DEVICE is received while the device is in Standby as a result of powering up into Standby the device shall set word 0 bit 2 to one to indicat...

Page 112: ... Advanced Power Management A SET FEATURES subcommand to disable Advanced Power Management Advanced Power Management Automatic Acoustic Management and the Standby timer setting are independent functions The device shall enter Standby mode if any of the following are true 1 The Standby timer has been set and times out 2 Automatic Power Management is enabled and the associated algorithm indicates tha...

Page 113: ...ment 2 A SET FEATURES subcommand to disable Automatic Acoustic Management Advanced Power Management Automatic Acoustic Management and the Standby timer setting are independent functions The device shall enter Standby mode if any of the following are true 1 The Standby timer has been set and times out 2 Automatic Power Management is enabled and the associated algorithm indicates that the Standby mo...

Page 114: ...Mode Subcommand code 09h Enable Address Offset Mode offsets address Cylinder 0 Head 0 Sector 1 LBA 0 to the start of the nonvolatile protected area established using the Set Max Address command The offset condition is cleared by Subcommand 89h Disable Address Offset Mode Hardware reset or Power on Reset If Reverting to Power on Defaults has been enabled by Set Features command it is cleared by Sof...

Page 115: ... device is in Address Offset mode 10 15 3 Exceptions in Address Offset Mode Any commands which access sectors across the original native maximum LBA are rejected with error even if the access protection is removed by a Set Max Address command If the sectors for Read Look Ahead operation include the original native maximum LBA Read Look Ahead operation is not carried out even if it is enabled by th...

Page 116: ... the desired register If HOB in the Device Control register is cleared to zero the host reads the most recently written content when the register is read A write to any Command Block register shall cause the device to clear the HOB bit to zero in the Device Control register The most recently written content always gets written by a register write regardless of the state of HOB in the Device Contro...

Page 117: ...e vendor specific The streaming commands may access any user LBA on a device These commands may be interspersed with non streaming commands but there may be an impact on performance due to the unknown time required to complete the non streaming commands The streaming commands should be issued using a specified minimum number of sectors transferred per command as specified in word 95 of the Identif...

Page 118: ...nt for content critical data 10 17 8 Streaming Logs The Streaming Data Transfer feature set requires two error logs and one performance log These logs are accessed via the Read Log Ext command the information included in the error logs is volatile and is not maintained across power cycles hard resets or sleep These error logs are 512 bytes in length and retain the last 31 errors that occurred duri...

Page 119: ...ware or hardware will cause the SCT command to be aborted 10 18 0 3 Resets In an SCT command is executing any reset including Soft Reset Hard Reset COMRESET and Power On Reset all cause the command to be terminated This could result in partial command execution or data loss There is no indication once the drive becomes ready that the previous command was terminated 10 18 1 SCT Command Protocol Com...

Page 120: ...ode LSB Cylinder Low Number of sectors to transfer LSB Cylinder Low Number of sectors to transfer LSB Cylinder High Number of sectors to transfer MSB Cylinder High Number of sectors to transfer MSB Device Head Device Head Status 50h Status 51h Command Block Output Registers Register 7 6 5 4 3 2 1 0 Current Reserved Feature Previous Reserved Current 01h Sector Count Previous 00h Current E0h LBA Low...

Page 121: ... 1 Reserved LBA Low HOB 1 Reserved HOB 0 Number of sectors LSB HOB 0 Number of sectors LSB LBA Mid HOB 1 Reserved LBA Mid HOB 1 Reserved HOB 0 Number of sectors MSB HOB 0 Number of sectors MSB LBA High HOB 1 Reserved LBA High HOB 1 Reserved Device Head Device Head Status 50h Status 51h Byte Field Words Description 1 0 Action Code 1 This field defines the command type and generally specifies the ty...

Page 122: ...m value 0008h Background SCT command was aborted because of an interrupting host command 0009h Background SCT command was terminated because of unrecoverable error 000Ah Invalid Function code in Long Sector Access command 000Bh SCT data transfer command was issued without first issuing an SCT command 000Ch Invalid Function code in Feature Control command 000Dh Invalid Feature code in Feature Contr...

Page 123: ...d Block Output Registers Register 7 6 5 4 3 2 1 0 Feature D5h Read D6h Write Sector Count Number of sectors to be transferred Sector Number E1h Cylinder Low 4Fh Cylinder High C2h Device Head D Command B0h Command Block Output Registers Register 7 6 5 4 3 2 1 0 Current Reserved Feature Previous Reserved Current 01h Sector Count Previous 00h Current E1h LBA Low Previous Reserved Current 00h LBA Mid ...

Page 124: ... host can determine execution progress by requesting SCT status Log page E0h contains the status information Reading log page E0h retrieves the status information The SCT status may be acquired any time that the host is allowing to send a command to the device This command will not change the power state of the drive nor terminate any background activity including any SCT command in progress 10 18...

Page 125: ...served Current 01h Sector Count Previous 00h Current E0h LBA Low Previous Reserved Current 00h LBA Mid Previous 00h Current Reserved LBA High Previous Reserved Device Head D Command 2Fh Word Name Value Description 0 Action Code 0001h Read or Write a sector with full ECC This function is based on the obsolete ATA Read Long Write Long capability and has been extended beyond 28 bit addressing 0001h R...

Page 126: ... Head reserved Status 50h Field Size bytes Description First Block User Data 512 This is the data normally sent or returned by a read or write command This data may be encoded Second Block ECC Data 51 ECC bytes in Vendor Specific Format The number of bytes is returned as TF Data on both read and write reserved 461 All zeros Word Name Value Description 0 Action Code 0002h This action writes a patte...

Page 127: ...bit 0 of the Status Flags in the SCT Status SeeFigure 32 shall be set to 1 A write to any user addressable sector on the drive except another complete write all shall cause the Segment Initialized Flag to be cleared Reallocations as a result of reading data foreground or background do not clear the Segment Initialized Flag Implementation note for Background Operation Function code 0001h 0002h In t...

Page 128: ... 0102h 0017h Blocking SCT Segment Access command was terminated because of unrecoverable error Command Block Input Registers Error Register 7 6 5 4 3 2 1 0 Error 04h Sector Count Extended Status code LSB Sector Number Extended Status code MSB Cylinder Low N A Cylinder High N A Device Head Status 51h Word Name Value Description 0 Action Code 0003h Set the read and write error recovery time 0001h Se...

Page 129: ... sent to the device These timers do not apply to streaming commands or to queued commands when out of order data delivery is enabled These command timers are volatile The default value is 0 i e disable command time out Command Block Input Registers Success Error 00h Sector Count If Function Code was 0002h then this is the LSB of the requested recovery limit Otherwise this field is reserved Sector ...

Page 130: ...nction Code 0003h Return feature option flags 2 Feature Code Word See Error Reference source not found for a list of the feature codes 3 State Word Feature code dependent value 4 Option Flags Word Bit15 1 Reserved If the function code is 0001h setting bit 0 to one causes the requested feature state change to be preserved across power cycles If the function code is 0001h setting bit 0 to zero cause...

Page 131: ...tus Of last SCT command issued FFFFh if SCT command executing in background 17 16 Word Action Code Action code of last SCT command issued If the Extended Status Code is FFFFh this is the Action Code of the command that is current executing 19 18 Word Function Code Function code of last SCT command issued If the Extended Status Code is FFFFh this is the Function Code of the command that is current ...

Page 132: ...rd 85 in the Identify Device information will reflect the true operation state of write cache one indicating enabled and zero indicating disabled The default state is 0001h 0002h 0001h Enable Write Cache Reordering 0002h Disable Write Cache Reordering The default state is 0001h The drive does not return error for setting state 0002h but the state is ignored 0003h Set time interval for temperature ...

Page 133: ...Identify Device information will reflect the true operation state of write cache one indicating enabled and zero indicating disabled The default state is 0001h 0002h 0001h Enable Write Cache Reordering 0002h Disable Write Cache Reordering The default state is 0001h The drive does not return error for setting state 0002h but the state is ignored 0003h Set time interval for temperature logging 0000h...

Page 134: ...ption 0 Action Code 0005h Read a data table 1 Function Code 0001h Read Table 2 Table ID Word See Error Reference source not found for a list of data tables 255 2 reserved 0000h Command Block Input Registers Success Error 00h Sector Count reserved Sector Number reserved Cylinder Low Number of sectors to transfer LSB 01h Cylinder High Number of sectors to transfer MSB 00h Device Head reserved Status...

Page 135: ...is is a fixed value 29 10 Byte 20 Reserved 31 30 Word Queue Size Number of entry locations in history queue This value is 128 33 32 Word Queue Index Last updated entry in queue Queue Index is zero based so Queue Index 0000h is the first location in the buffer at offset 34 The most recent temperature entered in the buffer is at Queue Index 34 See Note 1 and Note 2 Queue Size 33 34 Byte Queue Size Q...

Page 136: ...d absolute temperature value This way an application viewing the history can see the discontinuity in temperature result from the drive being turned off Note 2 When the Absolute HDA Temperature history is cleared for new drives or after changing the Logging Interval the Queue Index shall be set to zero and the first queue location shall be set to the current Absolute HDA Temperature value All rema...

Page 137: ...nger responding Interrupts are cleared when the host reads the Status Register issues a reset or writes to the Command Register See Section 13 0 Timings on page 269 for the device time out values 11 1 PIO Data In commands The following are Data In commands Device Configuration Identity Identify Device Read Buffer Read Log Ext Read Long Read Multiple Read Multiple Ext Read Sector s Read Sector s Ex...

Page 138: ...ort the command by setting BSY 0 ERR 1 ABT 1 and interrupting the host If an error occurs the device will set BSY 0 ERR 1 and DRQ 1 The device will then store the error status in the Error Register and interrupt the host The registers will contain the location of the sector in error The error location will be reported using CHS mode or LBA mode The mode is decided by the mode select bit bit 6 of t...

Page 139: ...device sets BSY 0 and DRQ 1 when it is ready to receive a sector b The host writes one sector of data including ECC bytes via the Data Register c The device sets BSY 1 after it has received the sector d After processing the sector of data the device sets BSY 0 and interrupts the host e In response to the interrupt the host reads the Status Register f The device clears the interrupt in response to ...

Page 140: ... M A R T Disable Operations S M A R T Enable Disable Attribute Autosave S M A R T Enable Disable Automatic Off Line S M A R T Enable Operations S M A R T Execute Off line Data Collection S M A R T Return Status S M A R T Save Attribute Values Standby Standby Immediate Execution of these commands involves no data transfer a The host writes any required parameters to the Features Sector Count Sector...

Page 141: ...diate sector interrupts are issued on multisector commands The host resets the DMA channel prior to reading status from the device The DMA protocol allows high performance multitasking operating systems to eliminate processor overhead asso ciated with PIO transfers The host initializes the Slave DMA channel 1 The host writes any required parameters to the Features Sector Count Sector Number Cylind...

Page 142: ...Deskstar T7K500 Hard Disk Drive Specification 128 ...

Page 143: ...1 1 0 1 1 0 0 0 1 2 Download Microcode 92 1 0 0 1 0 0 1 0 3 Execute Device Diagnos tic 90 1 0 0 1 0 0 0 0 3 Flush Cache E7 1 1 1 0 0 1 1 1 3 Flush Cache Ext EA 1 1 1 0 1 0 1 0 2 Format Track 50 0 1 0 1 0 0 0 0 1 Identify Device EC 1 1 1 0 1 1 0 0 3 Idle E3 1 1 1 0 0 0 1 1 3 Idle 97 1 0 0 1 0 1 1 1 3 Idle Immediate E1 1 1 1 0 0 0 0 1 3 Idle Immediate 95 1 0 0 1 0 1 0 1 3 Initialize Device Param ete...

Page 144: ... 2 Security Unlock F2 1 1 1 1 0 0 1 0 3 Seek 7x 0 1 1 1 3 Set Features EF 1 1 1 0 1 1 1 1 3 Set Max Address F9 1 1 1 1 1 0 0 1 3 Set Max Address Ext 37 0 0 1 1 0 1 1 1 3 Set Multiple Mode C6 1 1 0 0 0 1 1 0 3 Sleep E6 1 1 1 0 0 1 1 0 3 Sleep 99 1 0 0 1 1 0 0 1 3 SMART Disable Operations B0 1 0 1 1 0 0 0 0 3 SMART Enable Disable Attribute Auto save B0 1 0 1 1 0 0 0 0 3 SMART Enable Operations B0 1 ...

Page 145: ...e DMA CB 1 1 0 0 1 0 1 1 4 Write DMA Ext 35 0 0 1 1 0 1 0 1 2 Write Log Ext 3F 0 0 1 1 1 1 1 1 2 Write Long 32 0 0 1 1 0 0 1 0 2 Write Long 33 0 0 1 1 0 0 1 1 2 Write Multiple C5 1 1 0 0 0 1 0 1 2 Write Multiple Ext 39 0 0 1 1 1 0 0 1 2 Write Sector s 30 0 0 1 1 0 0 0 0 2 Write Sector s 31 0 0 1 1 0 0 0 1 2 Write Sector s Ext 34 0 0 1 1 0 1 0 0 4 Write Stream DMA 3A 0 0 1 1 1 0 1 0 4 Write Stream ...

Page 146: ...sable Operations B0 D9 S M A R T Return Status B0 DA S M A R T Enable Disable Automatic Off line B0 DB Set Features Enable Write Cache EF 02 Set Transfer mode EF 03 Enable Advanced Power Management EF 05 Enable Power up in Standby Feature Set EF 06 Power up in Standby Feature Set Device Spin up EF 07 Enable Address Offset mode EF 09 Enable Automatic Acoustic Management EF 42 52 bytes of ECC apply ...

Page 147: ...eaning is already obsolete there is no difference between 0 and 1 Using 0 is rec ommended for future compatibility B Option Bit This indicates that the Option Bit of the Sector Count Register be specified This bit is used by Set Max ADDRESS command V Valid This indicates that the bit is part of an output parameter and should be specified x This indicates that the hex character is not used This ind...

Page 148: ...r is at speed and the device is not in Standby or Sleep mode Other wise the Sector Count Register is set to 0 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count V V V V V V V V Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Dev...

Page 149: ...3 2 1 0 Data Low Data Low Data High Data High Feature Current V V V V V Error see below Previous V V V V V V V V Sector Count Current V V V V V V V V Sector Count HOB 0 Previous V V V V V V V V HOB 1 Sector Number Current Sector Number HOB 0 Previous HOB 1 Cylinder Low Current Cylinder Low HOB 0 Previous HOB 1 Cylinder High Current Cylinder High HOB 0 Previous HOB 1 Device Head 1 1 1 D Device Head...

Page 150: ...by the device when a streaming command with the same stream ID and a CCTL of zero are issued The time is measured from the write of the command register to the final INTRQ for command completion Sector Count Current Allocation Unit Size In Sectors 7 0 Sector Count Previous Allocation Unit Size In Sectors 15 8 Feature Current bit 7 A R If set to one a request to add a new stream If cleared to zero ...

Page 151: ... settings After successful execution of a DEVICE CONFIGURATION FREEZE LOCK com mand all DEVICE CONFIGURATION SET DEVICE CONFIGURATION FREEZE LOCK DEVICE CONFIGURATION IDENTIFY and DEVICE CONFIGURATION RESTORE commands are aborted by the device The DEVICE CONFIGURATION FREEZE LOCK condition shall be cleared by a power down The DEVICE CONFIGURATION FREEZE LOCK condition shall not be cleared by hardw...

Page 152: ...not set in the overlay received from a DEVICE CONFIGURATION IDENTIFY command no action is taken for that bit The format of the overlay transmitted by the device is described in the table in Table 73 Device Configuration Overlay Data structure on page 139 The restrictions on changing these bits is described in the text following that table If any of the bit modification restrictions described are v...

Page 153: ... are supported 0 1 Multiword DMA mode 0 is supported 2 Ultra DMA modes supported 15 6 Reserved 5 1 Ultra DMA mode 5 and below are supported 4 1 Ultra DMA mode 4 and below are supported 3 1 Ultra DMA mode 3 and below are supported 2 1 Ultra DMA mode 2 and below are supported 1 1 Ultra DMA mode 1 and below are supported 0 1 Ultra DMA mode 0 is supported 3 6 Maximum LBA address 7 Command set feature ...

Page 154: ... 3 and below are supported 2 1 Ultra DMA mode 2 and below are supported 1 1 Ultra DMA mode 1 and below are supported 0 1 Ultra DMA mode 0 is supported 3 6 Maximum LBA address 7 Command set feature set supported 12 1 SMART Selective self test is supported 9 1 Streaming feature set is supported 8 1 48 bit Addressing feature set supported 7 1 Host Protected Area feature set supported 6 1 Automatic ac...

Page 155: ...or this Download command UNC error will be set to 1 in the Error Register if the device fails to reload new microcode This error is reported only when the reload of microcode is requested In reloading new microcode the device does DASP handshake in reloading new microcode Thus the device does not recognize the slave device even though it exists Also when the spin up of the device is disabled the d...

Page 156: ...e register contains a diagnostic code See Table 57 Default Register Values on page 78 for the definition Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 Device Head Command 1 0 0 ...

Page 157: ...mand Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Device Head Command 1 1 1 0 0 1 1 1 Status see below Error Register Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ...

Page 158: ...2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current Sector Count HOB 0 Previous HOB 1 Sector Number Current Sector Number HOB 0 Previous HOB 1 Cylinder Low Current Cylinder Low HOB 0 Previous HOB 1 Cylinder High Current Cylinder High HOB 0 Previous HOB 1 Device Head D Device Head Command 1 1 1 0 1 0 1 0 Status See below...

Page 159: ...s to the device Sector Number In LBA mode this register specifies that LBA address bits 0 7 are to be formatted L 1 Cylinder High Low This indicates the cylinder number of the track to be formatted L 0 In LBA mode this register specifies that LBA address bits 8 15 Low and bits 16 23 High are to be formatted L 1 H This indicates the head number of the track to be formatted L 0 In LBA mode this reg ...

Page 160: ...L 1 Cylinder High Low In LBA mode this register specifies the current LBA address bits as 8 15 Low and bits 16 23 High H In LBA mode this register specifies the current LBA address bits as 24 27 L 1 Error The Error Register An Abort error ABT 1 will be returned when LBA is out of range In LBA mode this command formats a single logical track including the specified LBA ...

Page 161: ...ty Erase Prepare F3h command should be completed immediately prior to the Format Unit command If the device receives a Format Unit command without a prior Security Erase Prepare command the device aborts the Format Unit command All values in Feature register are reserved and any values other than 11h should not be put into Feature register This command does not request a data transfer Command exec...

Page 162: ...ontent field indicates the use of those parameters that are vendor specific Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Device Head Command 1 1 1 0 1 1 0 0 Status see below ...

Page 163: ...heads in default translate mode 04 0 Reserved 05 0 Reserved 06 003FH Number of sectors per track in default translate mode 07 0000H Number of bytes of sector gap 08 0000H Number of bytes in sync field 09 0000H Reserved 10 19 XXXX Serial number in ASCII 0 not specified 20 0003H Controller type 0003 dual ported multiple sector buffer with look ahead read 21 XXXXH Buffer size in 512 byte increments 2...

Page 164: ...61 xxxxH Total Number of User Addressable Sectors Word 60 specifies the low word of the number FFFFFFFh The 48 bit native max address is greater than 268 435 455 62 0000H 63 xx07H Multiword DMA Transfer Capability 15 8 Multi word DMA transfer mode active 7 0 7 Multi word DMA transfer modes supported support mode 0 1 and 2 64 0003H Flow Control PIO Transfer Modes Supported 15 8 0 Reserved 7 0 3 Adv...

Page 165: ...Reserved 6 1 Software setting preservation 5 0 Reserved 4 1 In order data delivery 3 1 Device initiated interface power management 2 1 DMA Setup Auto Activate optimization 1 1 Non zero buffer offset in DMA Setup FIS 0 0 Reserved 79 0040H SATA enabled features 15 7 0 Reserved 6 1 Software setting preservation 5 0 Reserved 4 0 In order data delivery 3 0 Device initiated interface power management 2 ...

Page 166: ...AD BUFFER command 12 1 WRITE BUFFER command 11 0 Reserved 10 1 Host Protected Area Feature Set 9 0 DEVICE RESET command 8 0 SERVICE interrupt 7 0 Release interrupt 6 1 LOOK AHEAD 5 1 WRITE CACHE 4 0 PACKET Command feature set 3 1 Power management feature set 2 0 Removable feature set 1 1 Security feature set 0 1 SMART feature Set ...

Page 167: ...pported extension 15 14 01 Word 84 is valid 13 11 0 Reserved 10 1 URG bit supported for WRITE STREAM DMA and WRITE STREAM PIO 9 1 URG bit supported for READ STREAM DMA and READ STREAM PIO 8 1 World wide name supported 7 0 WRITE DMA QUEUED FUA EXT command supported 6 0 WRITE DMA FUA EXT and WRITE MULTIPLE FUA EXT commands supported 5 1 General Purpose Logging feature set supported 4 1 Streaming fea...

Page 168: ...Removable Media Status Notification feature 3 Advanced Power Management Feature set 2 CFA Feature set 1 READ WRITE DMA QUEUED 0 DOWNLOAD MICROCODE command 87 Command set feature default 15 14 01 Word 87 is valid 4763H or 4773H 13 11 0 Reserved 10 1 URG bit supported for WRITE STREAM DMA and WRITE STREAM PIO 9 1 URG bit supported for READ STREAM DMA and READ STREAM PIO 8 1 World wide name supported...

Page 169: ...mpletion Time value xxxxh 2 minutes 90 0000H Time required for Enhanced security erase completion 91 0000H Current Advanced power management value 92 FFFEH Current Password Revision Code 93 SATA 0000H COMRESET result SATA 93 PATA xxxxH Hardware reset result Bit assignments 15 14 01 Word 93 is valid 13 CBLID status 1 Above Vih 0 Below Vil 12 8 Dev 1 H W reset result 12 Reserved 11 PDIAG asertion 1 ...

Page 170: ...ming command is calculated as follows Access Latency word 97 words 99 98 256 If the Streaming Feature set is not supported by the device the content of word 97 shall be zero 98 99 xxxxH Streaming Performance Granularity These words define the fixed unit of time that is used in Identify Device words 97 96 and 104 and Set Features subcommand 43h and in the Streaming Performance Parameters log which ...

Page 171: ...and and in the Command Completion Time Limit that is passed in streaming commands The unit of time for this parameter shall be in microseconds e g ad value of 10000 indicates 10 ms 100 103 xxxxH Maximum user LBA address for 48 bit Address feature set 104 xxxxH Streaming Transfer Time PIO The worst case sustainable transfer time per sector for the device is calculated as follows Streaming Transfer ...

Page 172: ...able 2 Reverting enabled 1 Enable 1 Read Look ahead enabled 1 Enable 0 Write Cache enabled 1 Enable 130 159 xxxxH Reserved 160 205 0000H Reserved 206 SCT Command set support 15 12 Vendor specific 11 6 Reserved 5 Action Code 5 SCT Data Table 1 Support 4 Action Code 4 Features Control 1 Support 3 Action Code 3 Error Recovery Control 1 Support 2 Action Code 2 LBA Segment Access 1 Support 1 Action Cod...

Page 173: ...low When the automatic power down sequence is enabled the drive will enter Standby mode automatically if the time out interval expires with no drive access from the host The time out interval will be reinitialized if there is a drive access before the time out interval expires Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data F...

Page 174: ...st commands immediately The Idle Immediate command will not affect the auto power down time out parameter Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Device Head Command 1 1...

Page 175: ...ans that there are no sectors rather than 256 sectors per track H This indicates the number of heads minus 1 per cylinder The minimum is 0 and the maxi mum is 15 The following condition needs to be met to avoid invalid number of cylinders beyond FFFFh Total number of user addressable sectors sector count x H 1 FFFFh The total number of user addressable sectors is described in Identify Device comma...

Page 176: ...he sector may be different if any reads or writes have occurred since the Write Buffer command was issued Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count V V V V V V V V Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Device ...

Page 177: ...its 0 7 L 1 Cylinder High Low This indicates the cylinder number of the first sector to be transferred L 0 In LBA mode this register specifies the transfer of LBA address bits 8 15 Low and 16 23 High L 1 H This indicates the head number of the first sector to be transferred L 0 In LBA mode this register specifies that LBA bits 24 27 is to be transferred L 1 R This indicates the retry bit This bit ...

Page 178: ...ister contains the current LBA bits 0 7 L 1 Cylinder High Low This indicates the cylinder number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 8 15 Low and bits16 23 High L 1 H This indicates the head number of the sector to be transferred L 0 In LBA mode this register contains the current LBA bits 24 27 L 1 ...

Page 179: ...n the Sector Count register is specified then 65 536 sectors will be transferred Sector Number Current LBA 7 0 Sector Number Previous LBA 31 24 Cylinder Low Current LBA 15 8 Cylinder Low Previous LBA 39 32 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sect...

Page 180: ...unrecoverable error Sector Number HOB 1 LBA 31 24 of the address of the first unrecoverable error Cylinder Low HOB 0 LBA 15 8 of the address of the first unrecoverable error Cylinder Low HOB 1 LBA 39 32 of the address of the first unrecoverable error Cylinder High HOB 0 LBA 23 16 of the address of the first unrecoverable error Cylinder High HOB 1 LBA 47 40 of the address of the first unrecoverable...

Page 181: ...linder Low Current The first sector of the log to be read low order bits 7 0 Cylinder Low Previous The first sector of the log to be read high order bits 15 8 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current V V V V V V V V Sector Count H...

Page 182: ...specified in the Sector Number register is not supported or enabled or if the values in the Sector Count Sector Number or Cylinder Low registers are invalid the device shall return com mand aborted Log Address Content Feature set Type 00h Log directory N A Read Only 03h Extended Comprehensive SMART error log SMART error logging Ready Only 06h SMART self test log SMART self test See Note 07h Extend...

Page 183: ... at log address 01h 7 0 1 02h Number of sectors in the log at log address 01h 15 8 1 03h Number of sectors in the log at log address 01h 7 0 1 04h Number of sectors in the log at log address 01h 15 8 1 05h Number of sectors in the log at log address 20h 7 0 1 40h Number of sectors in the log at log address 20h 7 0 1 41h Number of sectors in the log at log address 21h 7 0 1 42h Number of sectors in...

Page 184: ...rrors reported by the device These error log data structure entries are viewed as a circular buffer The fifth error shall create an error log structure that replaces the first error log data structure The next error after that shall create an error log data structure that replaces the second error log structure etc Unused error log data structures shall be filled with zeros 12 17 2 3 1 Data format...

Page 185: ...mber register 7 0 1 05h Sector number register 15 8 1 06h Cylinder Low register 7 0 1 07h Cylinder Low register 15 8 1 08h Cylinder High register 7 0 1 09h Cylinder High register 15 8 1 0Ah Device Head register 1 0Bh Command register 1 0Ch Reserved 1 0Dh Timestamp milliseconds from Power on 4 0Eh 18 Description Bytes Offset Reserved 1 00h Error register 7 0 1 01h Sector count register 7 0 See Note...

Page 186: ...log sector The figure below defines the format of each of the sectors that comprise the Extended SMART self test log The Extended SMART self test log sector shall support 48 bit and 28 bit addressing All 28 bit entries contained in the SMART self test log defined in 11 42 6 Self test log data structure on page0203 shall also be included in the Extended SMART self test log with all 48 bit entries T...

Page 187: ...greater than 31 but only the most recent 31 errors are represented by entries in the log If the Read Stream Error Count reaches the maximum value that can be represented after the next error is detected the Read Stream Error Count shall remain at the maximum value After successful completion of a Read Log Ext command with the LBA Low Register set to 22h the Read Stream Error Log shall be reset to ...

Page 188: ...vision of the structure format The Read Stream Error Log Count field shall contain the number of uncorrected sector entries currently reportable to the host This value may exceed 31 The Error Log Index indicates the error log data structure representing the most recent error Only values 31 1 are valid 512 Table 101 Read Stream Error Log ...

Page 189: ...turned shall contain a maximum of 31 error entries The Write Stream Error Count shall contain the total number of Write Stream Errors detected since the last successful completion of the Read Log Ext command with LBA Low register set to 21h This error count may be greater than 31 but only the most 31 errors are represented by entries in the log If the Write Stream Error Count reaches the maximum v...

Page 190: ...dware reset was executed The Error Log Index indicates the error log data structure representing the most recent error Only values 31 0 are valid 12 17 6 Streaming Performance Log Figure 112 defines the format of the log returned by the Read Log Ext command when the LBA Low register is 20h This data set is referred to as the Streaming Performance Parameters log the length of which in sectors is st...

Page 191: ...inearly Interpolated Description Bytes Stream Perforamnce Parameters log version 2 K Number of Regions in Sector Time Array 2 L Number of Positions in Position Array 2 M Number of Position differences in Access Time Array 2 Sector Time Array K 8 Position Array L 8 Access Time Array M 4 Reserved Description Bytes LBA of reference location LBA 7 0 LBA 47 40 n n 5 Identify Device words 99 98 65536 ti...

Page 192: ...or Count must be set to one Sector Number This indicates the sector number of the sector to be transferred L 0 In LBA mode this register contains LBA bits 0 7 L 1 Cylinder High Low This indicates the cylinder number of the sector to be transferred L 0 In LBA mode this register contains LBA bits 8 15 Low 16 23 High L 1 H This indicates the head number of the sector to be transferred L 0 In LBA mode...

Page 193: ...number of the transferred sector L 0 In LBA mode this register contains current LBA bits 8 15 Low 16 23 High L 1 H This indicates the head number of the transferred sector L 0 In LBA mode this register contains current LBA bits 24 27 L 1 It should be noted that the device internally uses 52 bytes of ECC data on all data written or read from the disk The 4 byte mode of operation is provided via emu...

Page 194: ...ple command instead of for each sector Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count V V V V V V V V Sector Count V V V V V V V V Sector Number V V V V V V V V Sector Number V V V V V V V V Cylinder Low V V V V V V V V Cylinder Low V V V V V V V V Cylinder High V V V V V V V V Cylinder H...

Page 195: ...BA 7 0 Sector Number Previous LBA 31 24 Cylinder Low Current LBA 15 8 Cylinder Low Previous LBA 39 32 Cylinder High Current LBA 23 16 Cylinder High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current V V V V V V V V Sector...

Page 196: ... HOB 1 LBA 31 24 of the address of the first unrecoverable error Cylinder Low HOB 0 LBA 15 8 of the address of the first unrecoverable error Cylinder Low HOB 1 LBA 39 32 of the address of the first unrecoverable error Cylinder High HOB 0 LBA 23 16 of the address of the first unrecoverable error Cylinder High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 197: ...the native max LBA bits 8 15 Low and bits 16 23 High L 1 In CHS mode this register contains the native max cylinder number L 0 H In LBA mode this register contains the native max LBA bits 24 27 L 1 In CHS mode this register contains the native maximum head number L 0 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Err...

Page 198: ...ax address Cylinder High HOB 1 LBA 47 40 of the address of the Native max address Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current Sector Count HOB 0 Previous HOB 1 Sector Number Current Sector Number HOB 0 V V V V V V V V Previous HOB 1 ...

Page 199: ...s the head number of the first sector to be transferred L 0 In LBA mode this register contains the LBA bits 24 27 L 1 R This is the retry bit but this bit is ignored Input parameters from the device Sector Count This is the number of requested sectors not transferred This will be zero unless an unre coverable error occurs Sector Number This is the sector number of the last transferred sector L 0 I...

Page 200: ... is the cylinder number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 8 15 Low and bits 16 23 High L 1 H This is the head number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 24 27 L 1 ...

Page 201: ...inder Low Current LBA 15 8 Cylinder Low Previous LBA 39 32 Cylinder High Current LBA 23 16 Cylinder High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current V V V V V V V V Sector Count HOB 0 Previous V V V V V V V V HOB 1...

Page 202: ... HOB 1 LBA 31 24 of the address of the first unrecoverable error Cylinder Low HOB 0 LBA 15 8 of the address of the first unrecoverable error Cylinder Low HOB 1 LBA 39 32 of the address of the first unrecoverable error Cylinder High HOB 0 LBA 23 16 of the address of the first unrecoverable error Cylinder High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 203: ...and the Command Completion Time Limit expires the device shall stop execution of the command and pro vide ending status with BSY bit cleared to zero the SE bit set to one the ERR bit cleared to zero and report the fact that the Command Completion Time Limit expired by setting the CCTO bit in the error log to one In all cases the device shall attempt to transfer the amount of data requested within ...

Page 204: ...F or ABRT reported in the error log If the RC bit is set to one and the CCTL expires the device shall stop execution of the command and provide ending status with the BSY bit cleared to zero the SE bit set to one the ERR bit cleared to zero and report the fact that the CCTL expired by setting the CCTO bit in the error log to one In all cases the device shall attempt to transfer the amount of data ...

Page 205: ...continuous sectors to be transferred high order bits 15 8 If zero is specified in the Sector Count register then 65 536 sectors will be transferred Sector Number Current LBA 7 0 Sector Number Previous LBA 31 24 Cylinder Low Current LBA 15 8 Cylinder Low Previous LBA 39 32 Cylinder High Current LBA 23 16 Cylinder High Previous LBA 47 40 Input Parameters From The Device Sector Number HOB 0 LBA 7 0 o...

Page 206: ...s If the RC bit is set to one when the command is issued and ICRC UNC IDNF ABRT or CCTO error occurs the SE bit shall be set to one the ERR bit shall be cleared to zero and the bits that would normally be set in the Error register shall be set in the error log DWE Status bit 4 DWE Deferred Write Error shall be set to one if an error was detected in a deferred write to the media for a previous Writ...

Page 207: ...IDNF or ABRT reported in the error log If the RC bit is set to one and the Command Completion Time Limit expires the device shall stop execution of the command and pro vide ending status with BSY bit cleared to zero the SE bit set to one the ERR bit cleared to zero and report the fact that the Command Completion Time Limit expired by setting the CCTO bit in the error log to one In all cases Comman...

Page 208: ...BSY bit cleared to zero the SE bit set to one the ERR bit cleared to zero and report the fact that the CCTL expired by setting the CCTO bit in the error log to one In all cases the device shall attempt to transfer the amount of data requested within the CCTL even if some data trans ferred is in error NS bit5 NS Not Sequential may be set to one if the next read stream command with the same Stream I...

Page 209: ...inder High HOB 1 LBA 47 40 of the address of the first unrecoverable error CCTO Error bit 0 CCTO bit shall be set to one if a Command Completion Time Limit Out error has occurred SE Status bit 5 SE Stream Error shall be set to one if an error has occurred during the execution of the command and the RC bit is set to one In this case the LBA returned in the Sector Number registers shall be the addre...

Page 210: ...6 23 High L 1 H This is the head number of the first sector to be transferred L 0 In LBA mode this register contains the LBA bits 24 27 L 1 R This is the retry bit this bit is ignored Input parameters from the device Sector Count This is the number of requested sectors not verified This number will be zero unless an unrecoverable error occurs Sector Number This is the sector number of the last tra...

Page 211: ... is the cylinder number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 8 15 Low and bits 16 23 High L 1 H This is the head number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 24 27 L 1 ...

Page 212: ...or Number Previous LBA 31 24 Cylinder Low Current LBA 15 8 Cylinder Low Previous LBA 39 32 Cylinder High Current LBA 23 16 Cylinder High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current V V V V V V V V Sector Count HOB ...

Page 213: ... HOB 1 LBA 31 24 of the address of the first unrecoverable error Cylinder Low HOB 0 LBA 15 8 of the address of the first unrecoverable error Cylinder Low HOB 1 LBA 39 32 of the address of the first unrecoverable error Cylinder High HOB 0 LBA 23 16 of the address of the first unrecoverable error Cylinder High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 214: ... Register Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Device Head Command 0 0 0 1 Status see below Error Register Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 I...

Page 215: ...ty Disable Password command The device will compare the password sent from this host with that specified in the control word Identifier Zero indicates that the device should check the supplied password against the user pass word stored internally One indicates that the device should check the given password against the master password stored internally Command Block Output Registers Command Block ...

Page 216: ... to prevent accidental erasure of the device This command does not request the transfer of data Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Device Head Command 1 1 1 1 0 0 1...

Page 217: ... device should check the given password against the master password stored internally The Security Erase Unit command erases all user data and disables the security mode feature device lock func tion After the completion of this command all the user data will be initialized to zero with a write operation At this time the data write is not verified with a read operation to determine if the data sec...

Page 218: ...device aborts the security erase unit command This command disables the security mode feature device lock function however the master password is still stored internally within the device and may be reactivated later when a new user password is set If you execute this command when disabling the security mode feature device lock function the password sent by the host is NOT compared with either the...

Page 219: ...ode Security Set Password Security Unlock Security Disable Password Security Erase Unit Refer to Table 70 Command table for device lock operation on page 84 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cyli...

Page 220: ...command Table 126 Security Set Password Information Identifier Zero indicates that the device should check the supplied password against the user password stored internally One indicates that the device should check the given password against the master password stored internally Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Dat...

Page 221: ...vel bits The setting of the Identifier and Security level bits interact as follows Identifier User Security level High The password supplied with the command will be saved as the new user password The security mode feature lock function will be enabled from the next power on The drive may then be unlocked by either the user password or the previously set master password Identifier Master Security ...

Page 222: ...sword If the password compare fails the device returns an abort error to the host and decrements the unlock attempt counter This counter is initially set to five and is decremented for each password mismatch When this counter reaches zero all password protected commands are rejected until there is a hard reset or a power off Identifier A zero indicates that the device regards Password as the User ...

Page 223: ... has failed due to a mismatched password since this is the only reason that an abort error will be returned by the drive AFTER the password information has been sent to the device An abort error returned by the device BEFORE the password data has been sent to the drive indicates that another problem exists ...

Page 224: ...ameters from the device Sector Number In LBA mode this register contains the current LBA bits 0 7 L 1 Cylinder High Low In LBA mode this register contains the current LBA bits 8 15 Low and bits16 23 High L 1 H In LBA mode this register contains the current LBA bits 24 27 L 1 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Fea...

Page 225: ... 1 1 1 1 Status see below Error Register Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AMN BSY RDY DF DSC DRQ COR IDX ERR 0 0 0 0 0 V 0 0 0 V 0 0 V 02H Enable write cache 03H Set transfer mode based on value in sector count register 05H Enable Advanced Power Management 06H Enable Power up in Standby feature set 07H Power up in Standby feature set device spin up 09H Enable...

Page 226: ...nt When the Feature Register is 05h Enable Advanced Power Management the Sector Count Register specifies the Advanced Power Management level The idle time to Low power idle mode and Low RPM standby mode vary according to the value in Sector Count register as follows When Low power idle mode is the deepest Power Saving mode Write cache Enable ECC bytes 4 bytes Read look ahead Enable Reverting to po...

Page 227: ... becomes 120 seconds when Low RPM standby mode is enabled Enabled Power Saving mode and idle time y1 and y2 are preserved until Advanced Power Management is dis abled the deepest Power Saving mode becomes Normal Idle mode or a new time is set They are initialized with a hard soft reset unless Reverting to Power on defaults is disabled and the devise receives a soft reset Additional electronics are...

Page 228: ...or Count Register specifies the Automatic Acoustic Management level The device preserves enabling or disabling of Automatic Acoustic Management and the current Automatic Acous tic Management level setting across all forms of reset that is Power on Hardware and Software Resets FFH Aborted C0 FEh Set to Normal Seek mode 80 BFh Set to Quiet Seek mode 00 7Fh Aborted ...

Page 229: ...device returns command aborted for a second nonvolatile Set Max Address command until the next power on or hardware reset The device returns command aborted during Set Max Locked mode or Set Max Frozen mode After a successful command completion Identify Device response words 61 60 shall reflect the maximum address set with this command If the 48 bit Address feature set is supported the value place...

Page 230: ...er In LBA mode this register contains LBA bits 0 7 which is to be set L 1 In CHS mode this register is ignored L 0 Cylinder High Low In LBA mode this register contains LBA bits 8 15 Low 16 23 High which is to be set L 1 In CHS mode this register contains cylinder number which is to be set L 0 H In LBA mode this register contains LBA bits 24 27 which is to be set L 1 In CHS mode this register is ig...

Page 231: ...e accepts this command the device is in Set_Max_Unlocked state Table 132 Set Max Set Password data contents Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature 0 0 0 0 0 0 0 1 Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Devic...

Page 232: ...cted The device remains in this state until a power cycle or the acceptance of a Set Max Unlock or Set Max Freeze Lock command Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature 0 0 0 0 0 0 1 0 Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Devi...

Page 233: ...itially set to 5 and is decremented for each password mismatch When this counter reaches zero all Set Max Unlock commands are rejected until a hard reset or a power off occurs If the password compare matches the device sets the Set_Max_Unlocked state and all Set Max commands are accepted Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 ...

Page 234: ...ected The following commands are disabled by Set Max Freeze Lock Set Max Address Set Max Set PASSWORD Set Max Lock Set Max Unlock Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature 0 0 0 0 0 0 1 0 Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High D...

Page 235: ...and or the device is in the Set Max Locked or Set Max Frozen state the device shall return command aborted If the device in Address Offset mode receives this command with the nonvolatile option the device returns aborted error to the host The device returns the command aborted for a second non volatile Set Max Address Ext command until next power on or hardware reset Command Block Output Registers...

Page 236: ... is not valid when the device is in Address Offset mode Sector Number Current Set Max LBA 7 0 Sector Number Previous Set Max LBA 31 24 Cylinder Low Current Set Max LBA 15 8 Cylinder Low Previous Set Max LBA 39 32 Cylinder High Current Set Max LBA 23 16 Cylinder High Previous Set Max LBA 47 40 Input parameters from the device Sector Number HOB 0 Set Max LBA 7 0 Sector Number HOB 1 Set Max LBA 31 24...

Page 237: ... indicates the block size to be used for the Read Multiple and the Write Multiple com mands Valid block sizes can be selected from 0 1 2 4 8 or 16 If 0 is specified then the Read Multiple and the Write Multiple commands are disabled Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count V V V V V...

Page 238: ...set is the only way to recover from Sleep Mode Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Device Head Command 1 1 1 0 0 1 1 0 Status see below Error Register Status Registe...

Page 239: ...r to select a subcommand the host must write the subcommand code to the Features Register of the device before issuing the S M A R T Function Set command The subcommands and their respective codes are listed below Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature V V V V V V V V Error see below Sector Count V V V V V V ...

Page 240: ... 00h written by the host into the Sector Count Register of the device before issuing the S M A R T Enable Disable Attribute Autosave subcommand will cause this feature to be disabled Disabling this feature does not preclude the device from saving Attribute Values to the Attribute Data sectors during another normal operation such as a power up or a power down A value of F1h written by the host into...

Page 241: ...tine depending on the interrupting command Captive mode When executing self test in captive mode the device sets BSY to one and executes the specified self test routine after receipt of the command At the end of the routine the device sets the execution result in the Self test execution status byte see Table 140 Device Attribute Data Structure on page 230 and ATA registers as defined below and the...

Page 242: ...command D9h This subcommand disables all S M A R T capabilities within the device including the attribute Autosave feature of the device After receipt of this subcommand the device disables all S M A R T operations Non self preserved Attribute Values will no longer be monitored The state of S M A R T either enabled or disabled is preserved by the device across power cycles Upon receipt of the S M ...

Page 243: ...tically collect attribute data in an off line mode and then saves this data to the non volatile memory of the device This subcommand may either cause the device to automatically initiate or resume performance of its off line data collection activities or cause the Automatic Off line Data Collection feature to be disabled A value of zero written by the host into the Sector Count register of the dev...

Page 244: ...he 12 bytes that make up the information for each Attribute entry in the Device Attribute Data Structure Table 141 Individual Attribute Data Structure Description Byte Offset Format Value Data Structure Revision Number 2 00h binary 0010h 1st Device Attribute 12 02h 1 30th Device Attribute 12 15Eh 1 Off line data collection status 1 16Ah 1 Self test execution status 1 16Bh 1 Total time in seconds t...

Page 245: ...ine testing 2 5 Vendor specific 6 15 Reserved 0 Normalized values The device performs conversion of the raw Attribute Values to transform them into normal ized values which the host can then compare with the Threshold values A Threshold is the excursion limit for a normalized Attribute Value 12 42 2 3 Off Line Data Collection Status The value of this byte defines the current status of the off line...

Page 246: ...mented bit 0 S M A R T Enable disable Automatic Off line subcommand is not implemented 1 S M A R T Enable disable Automatic Off line subcommand is implemented 2 Abort restart off line by host bit 0 The device will suspend off line data collection activity after an interrupting command and resume it after a vendor specific event 1 The device will abort off line data collection activity upon receipt...

Page 247: ...or Sleep mode 1 Attribute Autosave capability If bit 1 the device supports the S M A R T ENABLE DISABLE ATTRIBUTE AUTOSAVE command 2 15 Reserved 0 12 42 2 8 Error logging capability Bit Definition 7 1 Reserved 0 0 The Error Logging support bit If bit 1 the device supports the Error Logging 12 42 2 9 Self test failure check point This byte indicates the section of self test where the device detecte...

Page 248: ...e entries in the Individual Attribute Data Structure 12 42 3 3 Attribute ID Numbers Attribute ID Numbers supported by the device are the same as Attribute Values Data Structures 12 42 3 4 Attribute Threshold These values are preset at the factory and are not meant to be changeable 12 42 3 5 Data Structure Checksum The Data Structure Checksum is the two s complement of the result of a simple 8 bit ...

Page 249: ...log sector 12 42 5 1 S M A R T error log version This value is set to 01h 12 42 5 2 Error log pointer This points to the most recent error log data structure Only values 1 through 5 are valid 12 42 5 3 Device error count This field contains the total number of errors The value will not roll over Description Byte Offset S M A R T Logging Version 2 00h Number of sectors in the log at log address 1 1...

Page 250: ...cture 12 0Ch 3rd command data structure 12 18h 4th command data structure 12 24h 5th command data structure 12 30h Error data structure 30 3Ch 90 Description Byte Offset Device Control register 1 00h Features register 1 01h Sector count register 1 02h Sector number register 1 03h Cylinder Low register 1 04h Cylinder High register 1 05h Device Head register 1 06h Command register 1 07h Time stamp m...

Page 251: ...o contain up to 21 descriptors After 21 descriptors has been recorded the oldest descriptor will be overwritten with the new descriptor The self test log index points to the most recent descriptor When there is no descriptor the value is 0 When there are one or more descriptors the value is 1 through 21 Life time stamp hours 2 1Ch 30 Value State x0h Unknown x1h Sleep x2h Standby x3h Active Idle x4...

Page 252: ...e self test log data structure The Selective self test log is a log that may be both written and read by the host This log allows the host to select the parameters for the self test and to monitor the progress of the self test The following table defines the contents ...

Page 253: ...s received by the device with a subcommand value in the Features Regis ter that is either invalid or not supported by this device 51h 04h Description Bytes Offset Read Write Data structure revision 2 00h R W Starting LBA for test span 1 8 02h R W Ending LBA for test span 1 8 0Ah R W Starting LBA for test span 2 8 12h R W Ending LBA for test span 2 8 1Ah R W Starting LBA for test span 3 8 22h R W E...

Page 254: ... than S M A R T ENABLE OPERATIONS was received by the device while the device was in a S M A R T Disabled state 51h 04h The device is unable to read its Attribute Values or Attribute Thresholds data structure 51h 10h or 40h The device is unable to write to its Attribute Values data structure 51h 10h ...

Page 255: ...rs to the device Sector Count Time out Parameter If it is 0 the time out interval Standby Timer is NOT disabled If it is non zero the automatic power down sequence is enabled The time out interval is shown below Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count V V V V V V V V Sector Count S...

Page 256: ...atic power down sequence is enabled the device will enter the Standby mode automatically if the time out interval expires with no device access from the host The time out interval will be reinitialized if there is a drive access before the time out interval expires ...

Page 257: ... delay while waiting for the spindle to reach operating speed The Standby Immediate command will not affect the auto power down time out parameter Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High ...

Page 258: ...tial Write Buffer and Read Buffer commands access the same 512 byte within the buffer Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Device Head Command 1 1 1 0 1 0 0 0 Status ...

Page 259: ...the LBA bits 0 7 L 1 Cylinder High Low This indicates number of the first sector to be transferred L 0 In LBA mode this reg ister contains the LBA bits 8 15 Low and bits 16 23 High L 1 H This indicates the head number of the first sector to be transferred L 0 In LBA mode this register contains the LBA bits 24 27 L 1 R This indicates the retry bit This bit is ignored Input parameters from the devic...

Page 260: ...ister contains the current LBA bits 0 7 L 1 Cylinder High Low This indicates the cylinder number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 8 15 Low and bits 16 23 High L 1 H This indicates the head number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 24 27 L 1 ...

Page 261: ...rder bits 15 8 If zero is specified in the Sector Count register 65 536 sectors will be transferred Sector Number Current LBA 7 0 Sector Number Previous LBA 31 24 Cylinder Low Current LBA 15 8 Cylinder Low Previous LBA 39 32 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see ...

Page 262: ...unrecoverable error Sector Number HOB 1 LBA 31 24 of the address of the first unrecoverable error Cylinder Low HOB 0 LBA 15 8 of the address of the first unrecoverable error Cylinder Low HOB 1 LBA 39 32 of the address of the first unrecoverable error Cylinder High HOB 0 LBA 23 16 of the address of the first unrecoverable error Cylinder High HOB 1 LBA 47 40 of the address of the first unrecoverable...

Page 263: ...d low order bits 7 0 Sector Count Previous The number of continuous sectors to be transferred low order bits 15 8 If zero is specified in the Sector Count register 65 536 sectors will be transferred Sector Number Current LBA 7 0 Sector Number Previous LBA 31 24 Cylinder Low Current LBA 15 8 Cylinder Low Previous LBA 39 32 Command Block Output Registers Command Block Input Registers Register 7 6 5 ...

Page 264: ...unrecoverable error Sector Number HOB 1 LBA 31 24 of the address of the first unrecoverable error Cylinder Low HOB 0 LBA 15 8 of the address of the first unrecoverable error Cylinder Low HOB 1 LBA 39 32 of the address of the first unrecoverable error Cylinder High HOB 0 LBA 23 16 of the address of the first unrecoverable error Cylinder High HOB 1 LBA 47 40 of the address of the first unrecoverable...

Page 265: ...t sector of the log to be written low order bits 7 0 Cylinder Low Previous The first sector of the log to be written high order bits 15 8 If the feature set associated with the log specified in the Sector Number register is not supported or enabled or if the values in the Sector Count Sector Number or Cylinder Low registers are invalid the device shall return com mand aborted If the host attempts ...

Page 266: ...his indicates the cylinder number of the sector to be transferred L 0 In LBA mode this register contains the LBA bits 8 15 Low and bits 16 23 High L 1 H This indicates the head number of the sector to be transferred L 0 In LBA mode this register contains the LBA bits 24 27 L 1 R The retry bit This bit is ignored Input parameters from the device Sector Count This indicates the number of requested s...

Page 267: ...sector to be transferred L 0 In LBA mode this register contains current the LBA bits 24 27 L 1 The drive internally uses 52 bytes of ECC on all data read or writes The 4 byte mode of operation is provided by means of an emulation technique As a consequence of this emulation it is recommended that 52 byte ECC mode be used for all tests to confirm the operation of the ECC hardware of the drive Unexp...

Page 268: ...er contains the LBA bits 8 15 Low and bits 16 23 High L 1 H This indicates the head number of the first sector to be transferred L 0 In LBA mode this register contains the LBA bits 24 27 L 1 Input parameters from the device Sector Count This indicates the number of requested sectors not transferred The Sector Count will be zero unless an unrecoverable error occurs Sector Number This indicates the ...

Page 269: ...tes the cylinder number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 8 15 Low and bits 16 23 High L 1 H This indicates the head number of the last transferred sector L 0 In LBA mode this register contains current the LBA bits 24 27 L 1 ...

Page 270: ...0 Sector Number Previous LBA 31 24 Cylinder Low Current LBA 15 8 Cylinder Low Previous LBA 39 32 Cylinder High Current LBA 23 16 Cylinder High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current V V V V V V V V Error See below Previous V V V V V V V V Sector Count Cur...

Page 271: ... HOB 1 LBA 31 24 of the address of the first unrecoverable error Cylinder Low HOB 0 LBA 15 8 of the address of the first unrecoverable error Cylinder Low HOB 1 LBA 39 32 of the address of the first unrecoverable error Cylinder High HOB 0 LBA 23 16 of the address of the first unrecoverable error Cylinder High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 272: ...its 15 8 If zero is specified 65 536 sectors shall be transferred Sector Number Current LBA 7 0 Sector Number Previous LBA 31 24 Cylinder Low Current LBA 15 8 Cylinder Low Previous LBA 39 32 Cylinder High Current LBA 23 16 Cylinder High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data ...

Page 273: ... HOB 1 LBA 31 24 of the address of the first unrecoverable error Cylinder Low HOB 0 LBA 15 8 of the address of the first unrecoverable error Cylinder Low HOB 1 LBA 39 32 of the address of the first unrecoverable error Cylinder High HOB 0 LBA 23 16 of the address of the first unrecoverable error Cylinder High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 274: ...tes the head number of the first sector to be transferred L 0 In LBA mode this register contains the LBA bits 24 27 L 1 R This indicates the retry bit this bit is ignored Input parameters from the device Sector Count This indicates the number of requested sectors not transferred This will be zero unless an unrecoverable error occurs Sector Number This indicates the sector number of the last transf...

Page 275: ...cates the cylinder number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 8 15 Low and 16 23 High L 1 H This indicates the head number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 24 27 L 1 ...

Page 276: ... 8 Cylinder Low Previous LBA 39 32 Cylinder High Current LBA 23 16 Cylinder High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error See below Previous Sector Count Current V V V V V V V V Sector Count HOB 0 Previous V V V V V V V V HOB 1 Sector Number Current V...

Page 277: ... HOB 1 LBA 31 24 of the address of the first unrecoverable error Cylinder Low HOB 0 LBA 15 8 of the address of the first unrecoverable error Cylinder Low HOB 1 LBA 39 32 of the address of the first unrecoverable error Cylinder High HOB 0 LBA 23 16 of the address of the first unrecoverable error Cylinder High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 278: ...it set to one the ERR bit cleared to zero and report the fact that the Command Completion Time Limit expired by setting the CCTO bit in the error log to one In all cases the device shall attempt to transfer the amount of data requested within the Command Completion Time Limit event if some data transferred is in error Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 ...

Page 279: ... that all data for the specified stream shall be flushed to the media before command complete is reported when set to one HSE bit4 HSE Handle Stream Error specifies that this command starts at the LBA of the last reported error for this stream so the device may attempt to continue its corresponding error recovery sequence where it left off earlier Stream ID bit 0 2 Stream ID specifies the stream b...

Page 280: ...mmand Completion Time Limit expired by setting the CCTO bit in the error log to one In all cases the device shall attempt to transfer the amount of data requested within the Command Completion Time Limit event if some data transferred is in error Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feat...

Page 281: ...es that all data for the specified stream shall be flushed to the media before command complete is reported when set to one HSE bit4 HSE Handle Stream Error specifies that this command starts at the LBA of the last reported error for this stream so the device may attempt to continue its corresponding error recovery sequence where it left off earlier Stream ID bit 0 2 Stream ID specifies the stream...

Page 282: ... 5 SE Stream Error shall be set to one if an error has occurred during the execution of the command and the WC bit is set to one In this case the LBA returned in the Sector Number registers shall be the address of the first sector in error and the Sector Count registers shall contain the number of consecutive sectors that may contain errors If the WC bit is set to one when the command is issued an...

Page 283: ... 1 31 sec Hard Reset Device Busy After Hard Reset Bus RESET Signal Asserted Status Register BSY 1 400 ns Device Ready After Hard Reset Bus RESET Signal Asserted Status Register BSY 0 and RDY 1 31 sec Data In Com mand Device Busy After Com mand Code Out OUT To Command Register Status Register BSY 1 400 ns Interrupt DRQ For Data Transfer In Status Register BSY 1 Status Register BSY 0 and DRQ 1 Inter...

Page 284: ...t APM 98 Alternate Status Register 70 AT signal connector 22 Attribute thresholds 83 Attribute values 83 Attributes 83 Auto Reassign function 96 Automatic Acoustic Management 99 B BSMI mark 65 BSY 74 C Cable noise interference 55 Cabling 40 Capacity clip to 32GB 47 Capacity formatted 11 Caution 3 CE Mark 65 CE mark 65 Check Power Mode E5h 98h 134 Command descriptions 129 Command overhead 15 Comman...

Page 285: ...ve parameters 11 Defect flagging strategy 19 Description of operating modes 17 Deviations from standard 67 Device Control Register 71 Device Pausing Write DMA 37 Device Terminating Read DMA 35 Device Terminating Write DMA 38 Device Head Register 72 Diagnostic and Reset considerations 79 DMA commands 127 DMA Data Transfer commands 127 Drive Address Register 72 Drive characteristics 11 Drive format ...

Page 286: ...eral operation 77 German safety mark 64 H Handle Streaming Error bit 104 Head disk assembly 9 Head disk assembly data 9 Heads unload 60 Heads unload and actuator lock 60 Host Pausing Read DMA 33 Host Terminating Read DMA 34 Host Terminating Write DMA 39 Humidity 49 humidity 49 I Identification labels 63 Identify Device Data 101 Initiating Read DMA 32 Initiating Write DMA 36 Input voltage 51 Interf...

Page 287: ...ressing mode 80 M Master Password setting 86 Mechanical positioning 15 Mechanical specifications 56 MIC Mark 65 Mode transition time 18 Mounting hole locations 57 58 Mounting orientation 60 Multi word DMA timings 31 N Non data commands 126 Nonoperating rotational shock 62 Nonoperating shock 62 Nonoperating vibration 61 Nonrecovered write errors 96 Not Sequential bit 103 O Off line read scanning 83...

Page 288: ...power connector 53 Power Up in Standby feature set 97 Preventive maintenance 55 Protected Area 92 R Random vibration 61 Read Continuous bit 104 Read DRQ interval time 30 Reassign function 96 References 1 Register initialization 78 Register set 69 Registers 69 Reliability 55 Required power off sequence 55 Reset response 77 Reset timings 27 RX RX 28 S S M A R T commands 83 S M A R T Function 83 Set ...

Page 289: ...x security extension commands 93 Shock 61 Signal definition SATA model 27 Signal definitions 23 Signal definitions PATA model 23 Signal descriptions 24 Specification 43 Standby timer 81 Start stop cycles 55 Status Register 74 Streaming commands 103 Streaming feature Set 102 Streaming Logs 104 Substance restriction requirements 65 T Temperature 49 Threshold exceeded condition 83 Time out values 269...

Page 290: ...V Vibration 61 W Weight 56 World Wide Name Assignment 13 Write Buffer 244 Write cache function 95 Write Continuous bit 104 Write DRQ interval time 30 ...

Page 291: ...istered trade marks of their respective companies References in this publication to Hitachi Global Storage Technologies products programs or services do not imply that Hitachi Global Storage Technologies intends to make these available in all countries in which Hitachi Global Storage Technologies operates Product information is provided for information pur poses only and does not constitute a warr...

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