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Hitachi Deskstar 7K80, Specifications

The Hitachi Deskstar 7K80 is a high-performance hard drive designed to meet your storage needs. With speedy data transfer rates and a large capacity, it's an ideal choice for both personal and professional use. Ensure a hassle-free installation with the Quick Installation Manual, available for free download from our website.

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Deskstar 7K80 Hard Disk Drive Specification

250

Corrosion test  ..................................................................................................................59
CSA approval ..................................................................................................................69
C-TICK mark  ..................................................................................................................70
Cylinder allocation ..........................................................................................................22, 23
Cylinder High Register ...................................................................................................74
Cylinder Low Register ....................................................................................................74

D

Data In commands  ..........................................................................................................109
Data integrity  ..................................................................................................................31
Data Out Commands .......................................................................................................110
Data Register ...................................................................................................................75
Data Reliability ...............................................................................................................61
Data sheet ........................................................................................................................21, 22
Data transfer speed ..........................................................................................................27
DC power connector  .......................................................................................................33
DC power requirements  ..................................................................................................59
Defect flagging strategy ..................................................................................................31
Deviations from standard ................................................................................................71
Device Control Register ..................................................................................................75
Device Terminating Write DMA  ....................................................................................48
Device/Head Register .....................................................................................................76
DMA commands .............................................................................................................113
DMA Data Transfer commands ......................................................................................113
Drive Address Register  ...................................................................................................76
Drive characteristics  .......................................................................................................21
Drive format ....................................................................................................................22
Drive organization  ..........................................................................................................22
Drive ready time  .............................................................................................................26

E

Electrical interface  ..........................................................................................................33
Electrical interface specification .....................................................................................33
Electromagnetic compatibility ........................................................................................69, 70
Environment ....................................................................................................................58
Error log  ..........................................................................................................................88
Error Register ..................................................................................................................77

Summary of Contents for Deskstar 7K80

Page 1: ...Hard Disk Drive Specification Deskstar 7K80 3 5 inch Ultra ATA 133 hard disk drive Models HDS728040PLAT20 HDS728080PLAT20 Version 1 6 12 September 2006 ...

Page 2: ......

Page 3: ...Hard Disk Drive Specification Deskstar 7K80 3 5 inch Ultra ATA 133 hard disk drive Models HDS728040PLAT20 HDS728080PLAT20 Version 1 6 12 September 2006 ...

Page 4: ... Hitachi may make improvements or changes in any products or programs described in this publication at any time It is possible that this publication may contain reference to or information about Hitachi products machines and programs programming or services that are not announced in your country Such references or information must not be construed to mean that Hitachi intends to announce such Hita...

Page 5: ...e Assignment 22 4 4 Drive organization 22 4 4 1 Drive format 22 4 4 2 Cylinder allocation 23 4 5 Performance characteristics 24 4 5 1 Command overhead 24 4 5 2 Mechanical positioning 24 4 5 3 Drive ready time 26 4 5 4 Data transfer speed 27 4 5 5 Throughput 28 4 5 6 Operating modes 29 5 0 Defect flagging strategy 31 6 0 Electrical interface specification 33 6 1 Connector location 33 6 1 1 DC power...

Page 6: ...s 54 7 2 Environment 58 7 2 1 Temperature and humidity 58 7 2 2 Corrosion test 59 7 3 DC power requirements 59 7 3 1 Input voltage 59 7 3 2 Power supply current typical 60 7 3 3 Power supply generated ripple at drive power connector 60 7 4 Reliability 61 7 4 1 Data integrity 61 7 4 2 Cable noise interference 61 7 4 3 Start stop cycles 61 7 4 4 Preventive maintenance 61 7 4 5 Data reliability 61 7 ...

Page 7: ... set 73 9 2 Alternate Status Register 74 9 3 Command Register 74 9 4 Cylinder High Register 74 9 5 Cylinder Low Register 74 9 6 Data Register 75 9 7 Device Control Register 75 9 8 Drive Address Register 76 9 9 Device Head Register 76 9 10 Error Register 77 9 11 Features Register 77 9 12 Sector Count Register 77 9 13 Sector Number Register 78 9 14 Status Register 78 10 0 General operation 81 10 1 R...

Page 8: ...overlap 98 10 10 Write cache function 99 10 11 Reassign function 100 10 11 1 Auto Reassign function 100 10 12 Power Up in Standby feature set 101 10 13 Advanced Power Management feature set APM 102 10 14 Automatic Acoustic Management feature set AAM 103 10 15 Address Offset Feature 104 10 15 1 Enable Disable Address Offset Mode 104 10 15 2 Identify Device Data 105 10 15 3 Exceptions in Address Off...

Page 9: ...vice Parameters 91h 145 12 14 Read Buffer E4h 146 12 15 Read DMA C8h C9h 147 12 16 Read DMA Ext 25h 149 12 17 Read Log Ext 2Fh 151 12 17 1 General Purpose Log Directory 153 12 17 2 Extended Comprehensive SMART Error Log 154 12 17 3 Extended Self test log sector 156 12 17 4 Read Stream Error Log 157 12 17 5 Write Stream Error Log 158 12 17 6 Streaming Performance Log 159 12 18 Read Long 22h 23h 161...

Page 10: ...1 Sleep E6h 99h 207 12 42 S M A R T Function Set B0h 208 12 42 1 S M A R T Function Subcommands 209 12 42 2 Device Attribute Data Structure 213 12 42 3 Device Attribute Thresholds data structure 216 12 42 4 S M A R T Log Directory 218 12 42 5 S M A R T summary error log sector 218 12 42 6 Self test log data structure 220 12 42 7 Error reporting 221 12 43 Standby E2h 96h 222 12 44 Standby Immediate...

Page 11: ...art 39 Table 23 Multiword DMA cycle timing chart 41 Table 24 Multiword DMA cycle timings 41 Table 25 Ultra DMA cycle timings Initiating Read 42 Table 26 Ultra DMA cycle timing chart Host pausing Read 43 Table 27 Ultra DMA cycle timings Host pausing Read 43 Table 28 Ultra DMA cycle timing chart Host pausing Read 44 Table 29 Ultra DMA cycle timings Host pausing Read 44 Table 30 Ultra DMA cycle timin...

Page 12: ...s 82 Table 63 Reset error register values 83 Table 64 Power conditions 86 Table 65 Initial setting 91 Table 66 Usual operation for POR 92 Table 67 Password lost 93 Table 68 Seek overlap 98 Table 69 Device address map before and after Set Feature 104 Table 70 Command Set 115 Table 71 Command Set subcommand 118 Table 72 Check Power Mode command E5h 98h 120 Table 73 Configure Stream 51h 121 Table 74 ...

Page 13: ...ormance Parameters log 160 Table 109 Sector Time Array Entry Linearly Interpolated 160 Table 110 Access Time Array Entry Linearly Interpolated 160 Table 111 Read Long 22h 23h 161 Table 112 Read Multiple C4h 163 Table 113 Read DMA Ext Command 25h 164 Table 114 Read Native Max ADDRESS F8h 166 Table 115 Read Native Max Address Ext command 27h 167 Table 116 Read Sectors Command 20h 21h 168 Table 117 R...

Page 14: ...217 Table 147 Individual Threshold Data Structure 217 Table 148 S M A R T Log Directory 218 Table 149 S M A R T summary error log sector 218 Table 150 Error log data structure 219 Table 151 Command data structure 219 Table 152 Error data structure 219 Table 153 Self test log data structure 220 Table 154 S M A R T Error Codes 221 Table 155 Standby E2h 96h 222 Table 156 Standby Immediate E0h 94h 224...

Page 15: ...breviation Meaning A Ampere AC alternating current AT Advanced Technology ATA Advanced Technology Attachment BIOS Basic Input Output System C Celsius CSA Canadian Standards Association C UL Canadian Underwriters Laboratory Cyl cylinder DC Direct Current DFT Drive Fitness Test DMA Direct Memory Access ECC error correction code EEC European Economic Community EMC electromagnetic compatibility ERP Er...

Page 16: ...Mbps 1 000 000 bits per second MHz megahertz MLC Machine Level Control mm millimeter ms millisecond us ms microsecond O Output OD Open Drain Programmed Input Output POH power on hours Pop population P N part number p p peak to peak PSD power spectral density RES radiated electromagnetic susceptibility RFI radio frequency interference RH relative humidity RMS root mean square RPM revolutions per mi...

Page 17: ... Caution Do not apply force to the top cover Do not cover the breathing hole on the top cover Do not touch the interface connector pins or the surface of the printed circuit board This drive can be damaged by electrostatic discharge ESD Any damages incurred to the drive after its removal from the shipping package and the ESD protective bag are the responsibility of the user ...

Page 18: ...Deskstar 7K80 Hard Disk Drive Specification 14 ...

Page 19: ...B is used for firmware Ring buffer implementation Write Cache Advanced ECC On The Fly EOF Automatic Error Recovery procedures for read and write commands Self Diagnostics on Power on and resident diagnostics PIO Data Transfer Mode 4 16 6 MB s DMA Data Transfer Multiword mode Mode 2 16 6 MB s Ultra DMA Mode 6 133 MB s CHS and LBA mode Power saving modes Low RPM idle mode APM S M A R T Self Monitori...

Page 20: ...Deskstar 7K80 Hard Disk Drive Specification 16 ...

Page 21: ...Deskstar 7K80 Hard Disk Drive specification 17 Part 1 Functional specification ...

Page 22: ...Deskstar 7K80 Hard Disk Drive Specification 18 ...

Page 23: ...itions of the servo and takes corresponding action if an error occurs Monitors various timers such as head settle and servo failure Performs self checkout diagnostics 3 2 Head disk assembly The head disk assembly HDA is assembled in a clean room environment and contains the disks and actuator assembly Air is constantly circulated and filtered when the drive is operational Venting of the HDA is acc...

Page 24: ...Deskstar 7K80 Hard Disk Drive Specification 20 ...

Page 25: ... Physical layout that is the actual Head and Sec tors translation is done automatically in the drive The default setting can be obtained by issuing an IDENTIFY DEVICE command Table 1 Formatted capacities HDS728040PLAT20 HDS728080PLAT20 Physical Layout Label capacity GB 40 80 Bytes per sector 512 512 Sectors per track 567 1170 567 1170 Number of heads 1 2 Number of disks 1 1 Data sectors per cylind...

Page 26: ...ble 2 Mechanical positioning performance Data transfer rates Mbps 757 Interface transfer rates Mb s 133 Data buffer size1 KB 2048 Rotational speed RPM 7200 Number of buffer segments read up to 128 Number of buffer segments write up to 63 Recording density max Kbpi 689 Track density TPI 87 90 93 Areal density max Gbits in2 62 Number of data bands 30 Table 3 Word Wide Name Assignment Description Org...

Page 27: ... cylinder The spare cylinder is used by Hitachi Global Storage Technologies manufacturing and includes data sent from a defect location Table 4 Cylinder allocation Data Zone Physical Cylinders Blk Trk 0 1 444 1 170 1 3 095 1 147 2 3 095 1 147 3 3 389 1 134 4 3 043 1 125 5 3 845 1 080 6 3 946 1 080 7 4 501 1 026 8 4 001 1 026 9 3 232 1 012 10 3 726 990 11 3 193 972 12 4 286 945 13 3 120 918 14 3 09...

Page 28: ...ritten into the command regis ter by a host to the assertion of DRQ for the first data byte of a READ command when the requested data is not in the buffer excluding Physical seek time and Latency The table below gives average command overhead 4 5 2 Mechanical positioning 4 5 2 1 Average seek time without command overhead including settling Table 5 Command overhead Command type Drive is in quiescen...

Page 29: ...d Average max 1 max where max Maximum seek length n Seek length 1 to max Tnin Inward measured seek time for an n track seek Tnout Outward measured seek time for an n track seek 4 5 2 2 Full stroke seek time without command overhead including settling Full stroke seek is measured as the average of 1 000 full stroke seeks with a random head switch from both direc tions inward and outward 4 5 2 3 Hea...

Page 30: ...d and outward 4 5 2 6 Average latency 4 5 3 Drive ready time Ready The condition in which the drive is able to perform a media access command for exam ple read write immediately Power on This includes the time required for the internal self diagnostics Note Max Power On to ready time is the maximum time period that Device 0 waits for Device 1 to assert PDIAG Cylinder switch time typical ms 1 6 Tab...

Page 31: ...y the following for mula Sustained Transfer Rate A B C D where A 512 number of data sectors per cylinder B number of Surfaces per cylinder 1 head switch time C cylinder change time D number of surfaces time for one revolution Instantaneous buffer host transfer rate Mbyte s defines the maximum data transfer rate on the AT Bus It also depends on the speed of the host The method of measurement is giv...

Page 32: ...transfer rate byte sec Note It is assumed that a host system responds instantaneously and host data transfer is faster than sustained data rate 4 5 5 2 Random access The following table illustrates simple sequential access for enclosure The above table gives the time required to execute a total of 1000h read commands which access a single random LBA Typical and Max values are given by 105 and 110 ...

Page 33: ...le stop or power down Seek Seek operation mode Write Write operation mode Read Read operation mode Unload Idle Spindle rotation at 7200 RPM with heads unloaded Idle Spindle motor and servo system are working normally Commands can be received and pro cessed immediately Standby Actuator is unloaded and spindle motor is stopped Commands can be received immediately Sleep TActuator is unloaded and spin...

Page 34: ...Deskstar 7K80 Hard Disk Drive Specification 30 ...

Page 35: ...sical locations is calculated by an internally maintained table Shipped format Data areas are optimally used No extra sector is wasted as a spare throughout user data areas All pushes generated by defects are absorbed by the spare tracks of the inner zone Table 17 PATA Plist physical format Defects are skipped without any constraint such as track or cylinder boundary N N 1 N 2 N 3 defect defect sk...

Page 36: ...Deskstar 7K80 Hard Disk Drive Specification 32 ...

Page 37: ...Figure 1 Connector location 6 1 1 DC power connector The DC power connector is designed to mate with AMP part number 1 480424 0 using AMP pins part number 350078 4 strip part number 61173 4 loose piece or their equivalents Pin assignments are shown in the figure below 6 1 2 AT signal connector The AT signal connector is a 40 pin connector 4 3 2 1 Pin Voltage 1 12 V 2 GND 3 GND 4 5V ...

Page 38: ...urst Table 18 Signal definitions PIN SIGNAL I O Type PIN SIGNAL I O Type 01 RESET I TTL 02 GND 03 DD7 I O 3 state 04 DD08 I O 3 state 05 DD6 I O 3 state 06 DD09 I O 3 state 07 DD5 I O 3 state 08 DD10 I O 3 state 09 DD4 I O 3 state 10 DD11 I O 3 state 11 DD3 I O 3 state 12 DD12 I O 3 state 13 DD2 I O 3 state 14 DD13 I O 3 state 15 DD1 I O 3 state 16 DD14 I O 3 state 17 DD0 I O 3 state 18 DD15 I O 3...

Page 39: ...ected See Table 39 I O address map on page 50 RESET This line is used to reset the drive It shall be kept at a Low logic state during power up and kept High thereafter DIOW The rising edge of this signal holds data from the data bus to a register or data register of the drive DIOR When this signal is low it enables data from a register or data register of the drive onto the data bus The data on th...

Page 40: ...dicate that it is no longer busy and is able to provide status Following the receipt of a valid Execute Drive Diagnostics command device 1 shall negate PDIAG within 1 ms to indicate to device 0 that it is busy and has not yet passed its drive diagnostics If device 1 is present then device 0 shall wait up to 6 seconds from the receipt of a valid Execute Drive Diagnostics command for drive 1 to asse...

Page 41: ...ising and falling edge of HSTROBE latch the data from DD 15 0 into the device The host may stop toggling HSTROBE to pause an Ultra DMA data out transfer STOP Ultra DMA This signal is used only for Ultra DMA data transfers between host and drive The STOP signal shall be asserted by the host prior to initiation of an Ultra DMA burst A STOP shall be negated by the host before data is transferred in a...

Page 42: ...al specifications 6 5 Reset timings Table 20 System reset timing chart Table 21 System reset timing Inputs Input High Voltage Input Low Voltage 2 0 V min 0 8 V max Outputs Output High Voltage Output Low Voltage 2 4 V min 0 5 V max PARAMETER DESCRIPTION Min µs Max µs t10 RESET low width 25 t14 RESET high to not BUSY 31 t10 t14 RESET BUSY ...

Page 43: ...the next DRQ bit 6 6 2 Read DRQ interval time For read sectors and read multiple operations the interval from the end of negation of the DRQ bit until setting of the next DRQ bit is as follows PARAMETER DESCRIPTION MIN ns MAX ns t0 Cycle time 120 t1 Address valid to DIOR DIOW setup 25 t2 DIOR DIOW pulse width 70 t2i DIOR DIOW recovery time 25 t3 DIOW data setup 20 t4 DIOW data hold 10 t5 DIOR data...

Page 44: ...ent that a host reads the status register only before the sector or block transfer DRQ interval the DRQ interval 4 2 µs In the event that a host reads the status register after or both before and after the sector or block transfer the DRQ interval is 11 5 µs ...

Page 45: ... Cycle time 120 tD DIOR DIOW asserted pulse width 70 tE DIOR data access 50 tF DIOR data hold 5 tG DIOR DIOW data setup 20 tH DIOW data hold 10 tI DMACK to DIOR DIOW setup 0 tJ DIOR DIOW to DMACK hold 5 tKR tKW DIOR DIOW negated pulse width 25 tLR tLW DIOR DIOW to DMARQ delay 35 tM CS 1 0 valid to DIOR DIOW 25 tN CS 1 0 10 tZ DMACK to read data released 25 WRITE DATA READ DATA DMACK DMARQ DIOR DIO...

Page 46: ...ORDY Minimum time before driving IORDY 0 0 0 0 0 0 0 tFS First DSTROBE time 0 230 0 200 0 170 0 130 0 120 90 0 80 tCYC Cycle time 112 73 54 39 25 17 13 t2CYC Two cycle time 230 154 115 86 57 38 29 tAZ Maximum time allowed for output drivers to release 10 10 10 10 10 10 10 tZAD Drivers to assert 0 0 0 0 0 0 0 tDS Data setup time at host 15 10 7 7 5 4 8 2 6 tDH Data hold time at host 5 5 5 5 5 4 8 3...

Page 47: ...en a host does not satisfy tSR timing it should be ready to receive two more data words after HDMARDY is negated PARAMETER DESCRIPTION all values in ns MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tSR DSTROBE to HDMARDY time 50 30 20 tRFS HDMARDY to final DSTROBE time 75 70 60 60 60 50 50 DSTROBE HDMARDY DMACK DMARQ tSR STOP tRFS ...

Page 48: ...mited interlock time 0 150 0 150 0 150 0 100 0 100 0 75 0 60 tAZ Maximum time allowed for output drivers to release 10 10 10 10 10 10 10 tZAH Minimum delay time required for output 20 20 20 20 20 20 20 tMLI Interlock time with minimum 20 20 20 20 20 20 20 tCS CRC word setup time at device 15 10 7 7 5 5 5 tCH CRC word hold time at device 5 5 5 5 5 5 5 tACK Hold time for DMACK 20 20 20 20 20 20 20 t...

Page 49: ...erlock time 0 150 0 150 0 150 0 100 0 100 0 75 0 60 tAZ Maximum time allowed for output drivers to release 10 10 10 10 10 10 10 tZAH Maximum delay time required for output 20 20 20 20 20 20 20 tMLI Interlock time with minimum 20 20 20 20 20 20 20 tCS CRC word setup time at device 15 10 7 7 5 5 5 tCH CRC word hold time at device 5 5 5 5 5 5 5 tACK Hold time for DMACK 20 20 20 20 20 20 20 tIORDYZ Ma...

Page 50: ... 20 20 20 tENV Envelope time 20 70 20 70 20 70 20 55 20 55 20 55 20 50 tZIORDY Minimum time before driving IORDY 0 0 0 0 0 0 0 tLI Limited interlock time 0 150 0 150 0 150 0 100 0 100 0 75 0 60 tCYC Cycle time 112 73 54 39 25 16 8 13 0 t2CYC Two cycle time 230 154 115 86 57 38 29 tDS Data setup time at device 15 10 7 7 5 4 2 6 tDH Data Hold time at device 5 5 5 5 5 4 6 3 5 HSTROBE DDMARDY DMACK DM...

Page 51: ... When a device does not satisfy the tSR timing it shall be ready to receive two more strobes after DDMARDY is negated PARAMETER DESCRIPTION all values in ns MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tSR HSTROBE to DDMARDY time 50 30 20 tRFS DDMARDY to final HSTROBE time 75 70 60 60 60 50 50 HSTROBE DDMARDY DMACK DMARQ tSR STOP tRFS ...

Page 52: ...E time 75 70 60 60 60 50 50 tRP Ready to pause time 160 125 100 100 100 85 85 tLI Limited interlock time 0 150 0 150 0 150 0 100 0 100 0 75 0 60 tMLI Interlocking time with minimum 20 20 20 20 20 20 20 tCS CRC word setup time at device 15 10 7 7 5 5 5 tCH CRC word hold time at device 5 5 5 5 5 5 5 tACK Hold time for DMACK negation 20 20 20 20 20 20 20 tIORDYZ Maximum time before releasing IORDY 20...

Page 53: ...me from HSTROBE edge to assertion of STOP 50 50 50 50 50 50 50 tLI Limited interlock time 0 150 0 150 0 150 0 100 0 100 0 75 0 60 tMLI Interlock time with mini mum 20 20 20 20 20 20 20 tCS CRC word setup time at device 15 10 7 7 5 5 5 tCH CRC word hold time at device 5 5 5 5 5 5 5 tACK Hold time for DMACK 20 20 20 20 20 20 20 tIO RDYZ Maximum time before releasing IORDY 20 20 20 20 20 20 20 HSTROB...

Page 54: ...nts before interrupt the value is invalid 6 9 1 Cabling The maximum cable length from the host system to the drive plus circuit pattern length in the host system shall not exceed 18 inches For higher data transfer application 8 3 MB s a modification in the system design is recommended to reduce cable noise and cross talk such as a shorter cable bus termination or a shielded cable For systems opera...

Page 55: ...Deskstar 7K80 Hard Disk Drive Specification 51 Part 2 Interface specification ...

Page 56: ...Deskstar 7K80 Hard Disk Drive Specification 52 ...

Page 57: ...Deskstar 7K80 Hard Disk Drive Specification 53 7 0 Specification 7 1 Jumper settings 7 1 1 Jumper pin location 7 1 2 Jumper pin identification Jumper pins Jumper pins Pin A Pin B Pin I DERA001 prz ...

Page 58: ... 1 if it is present The Device 1 Slave Present setting is for a slave device that does not comply with the ATA specification Note In conventional terminology Device 0 designates a Master and Device 1 designates a Slave 7 1 4 Jumper positions 7 1 4 1 16 logical head default normal use The figure below shows the jumper positions used to select Device 0 Device 1 Cable Selection or Device1 Slave Prese...

Page 59: ... default The figure below shows the jumper positions used to select Device 0 Device 1 Cable Selection or Device1 Slave Present setting 15 logical heads instead of default 16 logical head models Notes 1 To enable the CSEL mode Cable Selection mode the jumper block must be installed at E F In the CSEL mode the drive address is determined by AT interface signal 28 CSEL as follows When CSEL is grounde...

Page 60: ...clips the LBA to 66055248 The CHS is unchanged from the factory default of 16383 16 63 7 1 4 4 Power up in Standby The figure below shows the jumper positions used to select Device 0 Device 1 Cable Selection or Device1 Slave Present to enable Power Up In Standby Table 41 Jumper settings for Disabling Auto Spin G I E C A H F D B DEVICE 0 Master G I E C A H F D B DEVICE 1 Slave G I E C A H F D B CAB...

Page 61: ...SET FEATURES subcommand 07h Refer to 12 28 Set Features 3 To enable the CSEL mode Cable Selection mode the jumper block must be installed at E F In the CSEL mode the drive address is determined by AT interface signal 28 CSEL as follows When CSEL is grounded or at a low level the drive address is 0 Device 0 When CSEL is open or at a high level the drive address is 1 Device 1 ...

Page 62: ...intained at any time Maximum storage period within shipping package is one year Table 42 Temperature and humidity Operating conditions Temperature 5C to 55ºC See note below Relative humidity 8 to 90 non condensing Maximum wet bulb temperature 29 4ºC non condensing Maximum temperature gradient 15ºC hour Altitude 300 to 3 048 m Non operating conditions Temperature 40C to 65ºC Relative humidity 5 to ...

Page 63: ...ug is allowed Connections to the drive should be made in a low voltage isolated secondary circuit SELV There is no special power on off sequencing required 7 3 1 Input voltage 1 To avoid damage to the drive electronics power supply voltage spikes must not exceed specifications 2 12V should be applied within 60 seconds after 5V is applied to the drive Table 44 Input voltage Input voltage supply2 Du...

Page 64: ...by four screws in a user system frame which has no electrical level difference at the four screws position and has less than 300 millivolts peak to peak level difference to the ground of the drive power connector Table 46 Power supply generated ripple at drive power connector Maximum mV pp MHz 5 V dc 100 0 10 12 V dc 150 0 10 Power supply current of 40 GB and 80 GB models PATA 5 Volts mA 12 Volts ...

Page 65: ...start stop cycles in a 40 C environment and a minimum of 10 000 start stop cycles in extreme temperature or humidity within the operating range See Table 42 Temperature and humidity on page 58 and Figure 9 Limits of temperature and humidity on page 48 7 4 4 Preventive maintenance None 7 4 5 Data reliability Probability of not recovering data is 1 in 1014 bits read ECC On The Fly correction 1 Symbo...

Page 66: ...re are in millimeters The breather hole must be kept uncovered in order to keep the air pressure inside of the disk enclosure equal to external air pressure The following table lists the dimensions of the drive Table 47 Physical dimensions and weight Height mm 24 3 0 3 Width mm 101 6 0 4 Length mm 146 0 0 6 Weight grams maximum 560 BREATHER HOLE ...

Page 67: ...locations and size of the drive are shown below All dimensions are in mm 7 5 3 Connector locations Thread 1 2 3 4 5 6 7 6 32 UNC 41 28 0 5 44 45 0 2 95 25 0 2 6 35 0 2 28 5 0 5 60 0 0 2 41 6 0 2 Side View 5 6 7 Bottom View 1 2 3 4 I F Connector 4X Max penetration 4 0 mm 6X Max penetration 4 5 mm ...

Page 68: ...propriate screws or equivalent mounting hardware The recommended mounting screw torque is 0 6 1 0 Nm 6 10 Kgf cm The recommended mounting screw depth is 4 mm maximum for bottom and 4 5 mm maximum for horizontal mounting Drive level vibration test and shock test are to be conducted with the drive mounted to the table using the bottom four screws 7 5 5 Heads unload and actuator lock The head load un...

Page 69: ...g in the specified conditions No errors occur with 0 5 G 0 to peak 5 to 300 to 5 Hz sine wave 0 5 oct min sweep rate with 3 minute dwells at two major resonances No data loss occurs with 1 G 0 to peak 5 to 300 to 5 Hz sine wave 0 5 oct min sweep rate with 3 minute dwells at two major resonances 7 6 2 Nonoperating vibration The drive does not sustain permanent damage or loss of previously recorded ...

Page 70: ...y procedures No error occurs with a 10 G half sine shock pulse of 11 ms duration in all models No data loss occurs with a 30 G half sine shock pulse of 4 ms duration in all models No data loss occurs with a 55 G half sine shock pulse of 2 ms duration in all models 7 6 4 Nonoperating shock The drive will operate with no degradation of performance after being subjected to shock pulses with the follo...

Page 71: ...pulse The figure below shows the maximum acceleration level and duration 7 6 5 Nonoperating rotational shock All shock inputs shall be applied around the actuator pivot axis Table 52 Rotational shock Table 51 Sinusoidal shock wave Acceleration level G Duration ms 350 2 150 11 Duration Rad s2 1 ms 30 000 2 ms 20 000 ...

Page 72: ...well time 0 5 x 60 RPM Seek rate 0 4 average seek time dwell time 7 8 Identification labels The following labels are affixed to every drive A label containing the Hitachi logo the Hitachi Global Storage Technologies part number and the statement Made by Hitachi Global Storage Technologies Inc or Hitachi Global Storage Technol ogies approved equivalent A label containing the drive model number the ...

Page 73: ...afe handling The product is conditioned for safe handling in regards to sharp edges and corners 7 9 5 Environment The product does not contain any known or suspected carcinogens Environmental controls meet or exceed all applicable government regulations in the country of origin Safe chemi cal usage and manufacturing control are used to protect the environment An environmental impact assessment has...

Page 74: ...s pproved two forms of C Tick Marking for Hitachi Global Storage Technologies The product is declared to be in conformity with requirements of the following EC directives under the sole responsibility of Hitachi Global Storage Technologies Japan Ltd Council Directive 89 336 EEC on the approximation of laws of the Member States relating to electromagnetic compatibility 7 10 1 C TICK mark The produc...

Page 75: ...logy 8 3 Deviations from standard The device conforms to the referenced specifications with the following deviations Check Power Mode Check Power Mode command returns FFh to Sector Count Register when the device is in Idle mode This command does not support 80h as the return value Hard Reset Hard reset response is not the same as that of power on reset Refer to section 10 1 Reset response on page ...

Page 76: ...Deskstar 7K80 Hard Disk Drive Specification 72 ...

Page 77: ...ernate status Addresses Functions CS0 CS1 DA2 DA1 DA0 READ DIOR WRITE DIOW N N x x x Data bus high impedance Not used Control block registers N A 0 x x Data bus high impedance Not used N A 1 0 x Data bus high impedance Not used N A 1 1 0 Alternate Status Device Control N A 1 1 1 Device Address Not used Command block registers A N 0 0 0 Data Data A N 0 0 1 Error Register Features A N 0 1 0 Sector C...

Page 78: ...d of the com mand this register is updated to reflect the current cylinder number In LBA Mode this register contains Bits 16 23 At the end of the command this register is updated to reflect the current LBA Bits 16 23 The cylinder number may be from zero to the number of cylinders minus one When 48 bit addressing commands are used the most recently written content contains LBA Bits 16 23 and the pr...

Page 79: ...DRQ 1 is in the Status Register 9 7 Device Control Register Table 56 Device Control Register 7 6 5 4 3 2 1 0 HOB 1 SRST IEN 0 Bit Definitions HOB HOB high order byte is defined by the 48 bit Address feature set A write to any Command Register shall clear the HOB bit to zero SRST Software Reset The device is held at reset when RST 1 Setting RST 0 again enables the device To ensure that the device r...

Page 80: ...st significant DS1 Drive Select 1 The Drive Select bit for device 1 is active low DS1 0 when device 1 slave is selected and active DS0 Drive Select 0 The Drive Select bit for device 0 is active low DS0 0 when device 0 master is selected and active 7 6 5 4 3 2 1 0 1 L 1 DRV HS3 HS2 HS1 HS0 L Binary encoded address mode select When L 0 addressing is by CHS mode When L 1 addressing is by LBA mode DRV...

Page 81: ...specified If the register is zero at command completion the command was successful If it is not successfully completed the register contains the number of sectors which need to be transferred in order to complete the request The contents of the register are defined otherwise on some commands These definitions are given in the command descriptions 7 6 5 4 3 2 1 0 CRC UNC 0 IDNF 0 ABRT TK0NF AMNF Bi...

Page 82: ...bit commands are used the most recently written content contains LBA Bits 0 7 and the previous con tent contains Bits 24 31 9 14 Status Register Table 60 Status Register This register contains the device status The contents of this register are updated whenever an error occurs and at the completion of each command If the host reads this register when an interrupt is pending it is considered to be ...

Page 83: ... device just before a Seek begins When an error occurs this bit is not changed until the Status Register is read by the host at which time the bit again indicates the current Seek complete status When the device enters into or is in Standby mode or Sleep mode this bit is set by the device in spite of the drive not spinning up DRQ Data Request Bit DRQ 1 indicates that the device is ready to transfe...

Page 84: ...Deskstar 7K80 Hard Disk Drive Specification 80 ...

Page 85: ...ponse table POR hard reset soft reset Aborting Host interface O O Aborting Device operation 1 1 Initialization of hardware O X X Internal diagnostic O X X Spinning spindle O X X Initialization of registers 2 O O O DASP handshake O O X PDIAG handshake O O O Reverting programmed parameters to default Number of CHS set by Initialize Device Parameters Multiple mode Write Cache Read look ahead ECC byte...

Page 86: ...d reset or the Execute Device Diagnostic command is shown in the figure below Table 62 Default Register Values Register Default Value Error Diagnostic Code Sector Count 01h Sector Number 01h Cylinder Low 00h Cylinder High 00h Device Head A0h Status 50h Alternate Status 50h Table 63 Diagnostic codes Code Description 01h No error detected 02h Formatter device error 03h Sector buffer error 04h ECC ci...

Page 87: ...e 0 may assert DASP to indicate device activity Hard Reset Soft Reset If Device 1 is present Device 0 shall read PDIAG to determine when it is valid to clear the BSY bit and whether Device 1 has reset without any errors otherwise Device 0 shall simply reset and clear the BSY bit DASP is asserted by Device 0 and Device 1 if it is present in order to indicate device active Execute Device Diagnostic ...

Page 88: ...bered from 0 to the maximum value allowed by the current CHS translation mode but cannot exceed 65535 0FFFFh When the host selects a CHS translation mode using the INITIALIZE DEVICE PARAMETERS command the host requests the number of sectors per logical track and the number of heads per logical cylinder The device then computes the number of logical cylinders available in requested mode The default...

Page 89: ...d Sleep Mode The lowest power consumption when the device is powered on occurs in Sleep Mode When in Sleep Mode the device requires a reset to be activated Standby Mode The device interface is capable of accepting commands but since the media may not be immediately accessible there is a delay while waiting for the spindle to reach operating speed Idle Mode In Idle Mode the device is capable of res...

Page 90: ...hysical interface as defined in the following table Ready RDY is not a power condition A device may post ready at the interface even though the media may not be accessible Table 65 Power conditions Mode BSY RDY Interface active Media Active x x Yes Active Idle o 1 Yes Active Standby o 1 Yes Inactive Sleep x x No Inactive ...

Page 91: ...isting Accordingly lower attribute values indicate that the analysis algorithms being used by the device are predicting a higher probability of a degrading or faulty condition 10 6 3 Attribute thresholds Each attribute value has a corresponding attribute threshold limit which is used for direct comparison to the attribute value to indicate the existence of a degrading or faulty condition The numer...

Page 92: ...re modification all error log data is discarded and the device error count for the life of the device is reset to zero 10 6 8 Self test The device provides the self test features which are initiated by SMART Execute Off line Immediate command The self test checks the fault of the device reports the test status in Device Attributes Data and stores the test result in the SMART self test log sector a...

Page 93: ... Media access commands are enabled by either a Security Unlock command or a Security Erase Unit command Device Unlocked Mode The device enables all commands If a password is not set this mode is entered after power on otherwise it is entered by a Security Unlock or a Security Erase Unit command Device Frozen Mode The device enables all commands except those which can update the device lock functio...

Page 94: ... Lock Function The Master Password Revision Code is set to FFFEh as shipping default by the drive manufacturer Master Password When the Master Password is set the device does NOT enable the Device Lock Function and the device CANNOT be locked with the Master Password but the Master Password can be used for unlocking the locked device Identify Device Information word 92 contains the value of the Ma...

Page 95: ...s powered on Table 66 Initial setting 10 7 4 3 Operation from POR after user password is set When Device Lock Function is enabled the device rejects media access command until a Security Unlock command Setting password POR Set Password with User Password Normal operation Power off Device locked mode POR No setting password POR Normal operation Power off Device unlocked mode POR ...

Page 96: ...cked mode Unlock CMD Command 1 Command 1 Password Erase Unit Password Match Reject Complete Complete Erase Unit Lock function Disable Normal operation All commands are available Freeze Lock command Enter Device Frozen mode Normal Operation expect Set Password Disable Password Erase Unit Unlock commands Enter Device Unlock mode N Y N Y Erase Prepare Media Access Non media Access Match ...

Page 97: ... SECURITY UNLOCK command has an attempt limit the purpose of which is to prevent attempts to unlock the drive with various passwords numerous times The device counts the password mismatch If the password does not match the device counts it without distinguishing the Master password and the User password If the count reaches 5 EXPIRE bit bit 4 of Word 128 in Identify Device information is set and t...

Page 98: ...utable Executable Executable Idle Executable Executable Executable Idle Immediate Executable Executable Executable Initialize Device Parameters Executable Executable Executable Read Buffer Executable Executable Executable Read DMA Command aborted Executable Executable Read DMA Ext Command aborted Executable Executable Read Log Ext Command aborted Executable Executable Read Long Command aborted Exe...

Page 99: ...e Executable SMART Read Attribute Values Executable Executable Executable SMART Read Attribute Thresholds Executable Executable Executable SMART Return Status Executable Executable Executable SMART Save Attribute Values Executable Executable Executable SMART Read Log Sector Executable Executable Executable SMART Write Log Sector Executable Executable Executable SMART Enable Disable Automatic Off L...

Page 100: ... is as follows i Issue a Read Native Max ADDRESS command to get the real device maximum LBA Returned value shows that native device maximum LBA is 12 692 735 C1ACFFh regardless of the current setting ii Make the entire device accessible including the protected area by setting the device maximum LBA to 12 692 735 C1ACFFh via Set Max ADDRESS command The option may be either nonvolatile or volatile i...

Page 101: ...t Max Lock Set Max Freeze Lock Set Max Unlock The Set Max Set Password command allows the host to define the password to be used during the current power on cycle The password does not persist over a power cycle but does persist over a hardware or software reset This password is not related to the password used for the Security Mode Feature set When the password is set the device is in the Set_Max...

Page 102: ...om the host however the actual seek operation for the next seek command starts immediately after the actual seek operation for the first seek command is completed In other words the execution of two seek commands overlaps excluding the time required for the actual seek operation With this overlap the total elapsed time for a number of seek commands results in the total accumulated time for actual ...

Page 103: ...e data onto the disk While writing data after completed acknowledgment of a write command soft reset or hard reset does not affect its operation However power off terminates the writing operation immediately and unwritten data is lost The Soft reset Standby Immediate command and Flush Cache commands during the writing of the cached data are executed after the completion of writing to media So the ...

Page 104: ...ecovered write errors When a write operation cannot be completed after the Error Recovery Procedure ERP is fully carried out the sector s are reallocated to the spare location An error is reported to the host system only when the write cache is disabled and the auto reallocation has failed If the Write Cache function is ENABLED when the number of available spare sectors reaches 0 sector both Auto ...

Page 105: ...fter power cycle A device needs a SET FEATURES subcommand to spin up to active state when the device has powered up into Standby The device remains in Standby until the SET FEATURES subcommand is received If power up into Standby is enabled when an IDENTIFY DEVICE is received while the device is in Standby as a result of powering up into Standby the device shall set word 0 bit 2 to one to indicate...

Page 106: ... Advanced Power Management A SET FEATURES subcommand to disable Advanced Power Management Advanced Power Management Automatic Acoustic Management and the Standby timer setting are independent functions The device shall enter Standby mode if any of the following are true 1 The Standby timer has been set and times out 2 Automatic Power Management is enabled and the associated algorithm indicates tha...

Page 107: ...ent 2 A SET FEATURES subcommand to disable Automatic Acoustic Management Advanced Power Management Automatic Acoustic Management and the Standby timer setting are independent functions The device shall enter Standby mode if any of the following are true 1 The Standby timer has been set and times out 2 Automatic Power Management is enabled and the associated algorithm indicates that the Standby mod...

Page 108: ...ode Subcommand code 09h Enable Address Offset Mode offsets address Cylinder 0 Head 0 Sector 1 LBA 0 to the start of the nonvolatile protected area established using the Set Max Address command The offset condition is cleared by Subcommand 89h Disable Address Offset Mode Hardware reset or Power on Reset If Reverting to Power on Defaults has been enabled by Set Features command it is cleared by Soft...

Page 109: ...device is in Address Offset mode 10 15 3 Exceptions in Address Offset Mode Any commands which access sectors across the original native maximum LBA are rejected with error even if the access protection is removed by a Set Max Address command If the sectors for Read Look Ahead operation include the original native maximum LBA Read Look Ahead operation is not carried out even if it is enabled by the...

Page 110: ...the desired register If HOB in the Device Control register is cleared to zero the host reads the most recently written content when the register is read A write to any Command Block register shall cause the device to clear the HOB bit to zero in the Device Control register The most recently written content always gets written by a register write regardless of the state of HOB in the Device Control...

Page 111: ...and the device shall operate according to the Stream ID set by the streaming command The operation is device vendor specific The streaming commands may access any user LBA on a device These commands may be interspersed with non streaming commands but there may be an impact on performance due to the unknown time required to complete the non streaming commands The streaming commands should be issued...

Page 112: ... the Command Completion Time Limit the erroneous section on the media may be unchanged or may contain undefined data A future read of this area may not report an error even though the data is erroneous 10 17 7 Handle Streaming Error bit The Handle Streaming Error bit specifies to the device that this command starts at the LBA of a recently reported error section so the device may attempt to contin...

Page 113: ...ger responding Interrupts are cleared when the host reads the Status Register issues a reset or writes to the Command Register See Section 13 0 Timings on page 247 for the device time out values 11 1 PIO Data In commands The following are Data In commands Device Configuration Identity Identify Device Read Buffer Read Log Ext Read Long Read Multiple Read Multiple Ext Read Sector s Read Sector s Ext...

Page 114: ...rt the command by setting BSY 0 ERR 1 ABT 1 and interrupting the host If an error occurs the device will set BSY 0 ERR 1 and DRQ 1 The device will then store the error status in the Error Register and interrupt the host The registers will contain the location of the sector in error The error location will be reported using CHS mode or LBA mode The mode is decided by the mode select bit bit 6 of th...

Page 115: ...evice sets BSY 0 and DRQ 1 when it is ready to receive a sector b The host writes one sector of data including ECC bytes via the Data Register c The device sets BSY 1 after it has received the sector d After processing the sector of data the device sets BSY 0 and interrupts the host e In response to the interrupt the host reads the Status Register f The device clears the interrupt in response to t...

Page 116: ...M A R T Disable Operations S M A R T Enable Disable Attribute Autosave S M A R T Enable Disable Automatic Off Line S M A R T Enable Operations S M A R T Execute Off line Data Collection S M A R T Return Status S M A R T Save Attribute Values Standby Standby Immediate Execution of these commands involves no data transfer a The host writes any required parameters to the Features Sector Count Sector ...

Page 117: ...iate sector interrupts are issued on multisector commands The host resets the DMA channel prior to reading status from the device The DMA protocol allows high performance multitasking operating systems to eliminate processor overhead asso ciated with PIO transfers The host initializes the Slave DMA channel 1 The host writes any required parameters to the Features Sector Count Sector Number Cylinde...

Page 118: ...Deskstar 7K80 Hard Disk Drive Specification 114 ...

Page 119: ... 1 0 1 1 0 0 0 1 2 Download Microcode 92 1 0 0 1 0 0 1 0 3 Execute Device Diagnos tic 90 1 0 0 1 0 0 0 0 3 Flush Cache E7 1 1 1 0 0 1 1 1 3 Flush Cache Ext EA 1 1 1 0 1 0 1 0 2 Format Track 50 0 1 0 1 0 0 0 0 1 Identify Device EC 1 1 1 0 1 1 0 0 3 Idle E3 1 1 1 0 0 0 1 1 3 Idle 97 1 0 0 1 0 1 1 1 3 Idle Immediate E1 1 1 1 0 0 0 0 1 3 Idle Immediate 95 1 0 0 1 0 1 0 1 3 Initialize Device Param eter...

Page 120: ...2 Security Unlock F2 1 1 1 1 0 0 1 0 3 Seek 7x 0 1 1 1 3 Set Features EF 1 1 1 0 1 1 1 1 3 Set Max Address F9 1 1 1 1 1 0 0 1 3 Set Max Address Ext 37 0 0 1 1 0 1 1 1 3 Set Multiple Mode C6 1 1 0 0 0 1 1 0 3 Sleep E6 1 1 1 0 0 1 1 0 3 Sleep 99 1 0 0 1 1 0 0 1 3 SMART Disable Operations B0 1 0 1 1 0 0 0 0 3 SMART Enable Disable Attribute Auto save B0 1 0 1 1 0 0 0 0 3 SMART Enable Operations B0 1 0...

Page 121: ... DMA CB 1 1 0 0 1 0 1 1 4 Write DMA Ext 35 0 0 1 1 0 1 0 1 2 Write Log Ext 3F 0 0 1 1 1 1 1 1 2 Write Long 32 0 0 1 1 0 0 1 0 2 Write Long 33 0 0 1 1 0 0 1 1 2 Write Multiple C5 1 1 0 0 0 1 0 1 2 Write Multiple Ext 39 0 0 1 1 1 0 0 1 2 Write Sector s 30 0 0 1 1 0 0 0 0 2 Write Sector s 31 0 0 1 1 0 0 0 1 2 Write Sector s Ext 34 0 0 1 1 0 1 0 0 4 Write Stream DMA 3A 0 0 1 1 1 0 1 0 4 Write Stream P...

Page 122: ...able Operations B0 D9 S M A R T Return Status B0 DA S M A R T Enable Disable Automatic Off line B0 DB Set Features Enable Write Cache EF 02 Set Transfer mode EF 03 Enable Advanced Power Management EF 05 Enable Power up in Standby Feature Set EF 06 Power up in Standby Feature Set Device Spin up EF 07 Enable Address Offset mode EF 09 Enable Automatic Acoustic Management EF 42 52 bytes of ECC apply o...

Page 123: ...aning is already obsolete there is no difference between 0 and 1 Using 0 is rec ommended for future compatibility B Option Bit This indicates that the Option Bit of the Sector Count Register be specified This bit is used by Set Max ADDRESS command V Valid This indicates that the bit is part of an output parameter and should be specified x This indicates that the hex character is not used This indi...

Page 124: ... is at speed and the device is not in Standby or Sleep mode Other wise the Sector Count Register is set to 0 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count V V V V V V V V Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Devi...

Page 125: ... 2 1 0 Data Low Data Low Data High Data High Feature Current V V V V V Error see below Previous V V V V V V V V Sector Count Current V V V V V V V V Sector Count HOB 0 Previous V V V V V V V V HOB 1 Sector Number Current Sector Number HOB 0 Previous HOB 1 Cylinder Low Current Cylinder Low HOB 0 Previous HOB 1 Cylinder High Current Cylinder High HOB 0 Previous HOB 1 Device Head 1 1 1 D Device Head ...

Page 126: ...y the device when a streaming command with the same stream ID and a CCTL of zero are issued The time is measured from the write of the command register to the final INTRQ for command completion Sector Count Current Allocation Unit Size In Sectors 7 0 Sector Count Previous Allocation Unit Size In Sectors 15 8 Feature Current bit 7 A R If set to one a request to add a new stream If cleared to zero a...

Page 127: ...settings After successful execution of a DEVICE CONFIGURATION FREEZE LOCK com mand all DEVICE CONFIGURATION SET DEVICE CONFIGURATION FREEZE LOCK DEVICE CONFIGURATION IDENTIFY and DEVICE CONFIGURATION RESTORE commands are aborted by the device The DEVICE CONFIGURATION FREEZE LOCK condition shall be cleared by a power down The DEVICE CONFIGURATION FREEZE LOCK condition shall not be cleared by hardwa...

Page 128: ...ot set in the overlay received from a DEVICE CONFIGURATION IDENTIFY command no action is taken for that bit The format of the overlay transmitted by the device is described in the table in Table 77 Device Configuration Overlay Data structure on page 125 The restrictions on changing these bits is described in the text following that table If any of the bit modification restrictions described are vi...

Page 129: ...are supported 0 1 Multiword DMA mode 0 is supported 2 Ultra DMA modes supported 15 6 Reserved 5 1 Ultra DMA mode 5 and below are supported 4 1 Ultra DMA mode 4 and below are supported 3 1 Ultra DMA mode 3 and below are supported 2 1 Ultra DMA mode 2 and below are supported 1 1 Ultra DMA mode 1 and below are supported 0 1 Ultra DMA mode 0 is supported 3 6 Maximum LBA address 7 Command set feature s...

Page 130: ...3 and below are supported 2 1 Ultra DMA mode 2 and below are supported 1 1 Ultra DMA mode 1 and below are supported 0 1 Ultra DMA mode 0 is supported 3 6 Maximum LBA address 7 Command set feature set supported 12 1 SMART Selective self test is supported 9 1 Streaming feature set is supported 8 1 48 bit Addressing feature set supported 7 1 Host Protected Area feature set supported 6 1 Automatic aco...

Page 131: ...UNC error will be set to 1 in the Error Register if the device fails to reload new microcode This error is reported only when the reload of microcode is requested In reloading new microcode the device does not preserve its state and settings but reset them just like the device is executing a power on For instance the device does DASP handshake in reloading new microcode Thus the Command Block Outp...

Page 132: ...tar 7K80 Hard Disk Drive Specification 128 device does not recognize the slave device even though it exists Also when the spin up of the device is disabled the device spins down after reloading new microcode ...

Page 133: ... register contains a diagnostic code See Table 62 Default Register Values on page 82 for the definition Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 Device Head Command 1 0 0 1...

Page 134: ...and Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Device Head Command 1 1 1 0 0 1 1 1 Status see below Error Register Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 A...

Page 135: ... 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current Sector Count HOB 0 Previous HOB 1 Sector Number Current Sector Number HOB 0 Previous HOB 1 Cylinder Low Current Cylinder Low HOB 0 Previous HOB 1 Cylinder High Current Cylinder High HOB 0 Previous HOB 1 Device Head D Device Head Command 1 1 1 0 1 0 1 0 Status See below ...

Page 136: ... to the device Sector Number In LBA mode this register specifies that LBA address bits 0 7 are to be formatted L 1 Cylinder High Low This indicates the cylinder number of the track to be formatted L 0 In LBA mode this register specifies that LBA address bits 8 15 Low and bits 16 23 High are to be formatted L 1 H This indicates the head number of the track to be formatted L 0 In LBA mode this reg i...

Page 137: ... 1 Cylinder High Low In LBA mode this register specifies the current LBA address bits as 8 15 Low and bits 16 23 High H In LBA mode this register specifies the current LBA address bits as 24 27 L 1 Error The Error Register An Abort error ABT 1 will be returned when LBA is out of range In LBA mode this command formats a single logical track including the specified LBA ...

Page 138: ... F3h command should be completed immediately prior to the Format Unit command If the device receives a Format Unit command without a prior Security Erase Prepare command the device aborts the Format Unit command All values in Feature register are reserved and any values other than 11h should not be put into Feature register This command does not request a data transfer Command execution time depen...

Page 139: ...ntent field indicates the use of those parameters that are vendor specific Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Device Head Command 1 1 1 0 1 1 0 0 Status see below E...

Page 140: ... 00xxH Number of heads in default translate mode 04 0 Reserved 05 0 Reserved 06 003FH Number of sectors per track in default translate mode 07 0000H Number of bytes of sector gap 08 0000H Number of bytes in sync field 09 0000H Reserved 10 19 XXXX Serial number in ASCII 0 not specified 20 0003H Controller type 0003 dual ported multiple sector buffer with look ahead read 21 XXXXH Buffer size in 512 ...

Page 141: ...d 54 58 are Valid 54 xxxxH Number of current cylinders 55 xxxxH Number of current heads 56 xxxxH Number of current sectors per track 57 58 xxxxH Current capacity in sectors Word 57 specifies the low word of the capacity 59 0xxxH Current Multiple setting bit assignments 15 9 0 Reserved 8 1 Multiple Sector Setting is Valid 7 0 xxh Current setting for number of sectors 60 61 xxxxH Total Number of Use...

Page 142: ...00H Reserved 75 00xxH Queue depth 15 5 Reserved 4 0 Maximum queued depth 0 76 79 0000H Reserved 80 00FCH Major version number 15 0 FCh ATA 2 ATA 3 ATA ATAPI 4 ATA ATAPI 5 and ATA ATAPI 6 and ATA ATAPI 7 81 001AH Minor version number 15 0 1Ah ATA ATAPI 7 T13 1532D revision 1 82 74EBH Command set supported 15 0 Reserved 14 1 NOP command 13 1 READ BUFFER command 12 1 WRITE BUFFER command 11 0 Reserve...

Page 143: ...re supported extension 15 14 01 Word 84 is valid 13 11 0 Reserved 10 1 URG bit supported for WRITE STREAM DMA and WRITE STREAM PIO 9 1 URG bit supported for READ STREAM DMA and READ STREAM PIO 8 1 World wide name supported 7 0 WRITE DMA QUEUED FUA EXT command supported 6 0 WRITE DMA FUA EXT and WRITE MULTIPLE FUA EXT commands supported 5 1 General Purpose Logging feature set supported 4 1 Streamin...

Page 144: ... Media Status Notification feature 3 Advanced Power Management Feature set 2 CFA Feature set 1 READ WRITE DMA QUEUED 0 DOWNLOAD MICROCODE command 87 Command set feature default 15 14 01 Word 87 is valid 4723H or 4733H 13 11 0 Reserved 10 1 URG bit supported for WRITE STREAM DMA and WRITE STREAM PIO 9 1 URG bit supported for READ STREAM DMA and READ STREAM PIO 8 1 World wide name supported 7 0 WRIT...

Page 145: ...or security erase unit completion Time value xxxxh 2 minutes 90 0000H Time required for Enhanced security erase completion 91 0000H Current Advanced power management value 92 FFFEH Current Password Revision Code 93 xxxxH Hardware reset result Bit assignments 15 14 01 Word 93 is valid 13 CBLID status 1 Above Vih 0 Below Vil 12 8 Dev 1 H W reset result 12 Reserved 11 PDIAG asertion 1 assert 0 not as...

Page 146: ... command is calculated as follows Access Latency word 97 words 99 98 256 If the Streaming Feature set is not supported by the device the content of word 97 shall be zero 98 99 xxxxH Streaming Performance Granularity These words define the fixed unit of time that is used in Identify Device words 97 96 and 104 and Set Features subcommand 43h and in the Streaming Performance Parameters log which is a...

Page 147: ...ow When the automatic power down sequence is enabled the drive will enter Standby mode automatically if the time out interval expires with no drive access from the host The time out interval will be reinitialized if there is a drive access before the time out interval expires Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Fe...

Page 148: ...t commands immediately The Idle Immediate command will not affect the auto power down time out parameter Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Device Head Command 1 1 ...

Page 149: ...ns that there are no sectors rather than 256 sectors per track H This indicates the number of heads minus 1 per cylinder The minimum is 0 and the maxi mum is 15 The following condition needs to be met to avoid invalid number of cylinders beyond FFFFh Total number of user addressable sectors sector count x H 1 FFFFh The total number of user addressable sectors is described in Identify Device comman...

Page 150: ...e sector may be different if any reads or writes have occurred since the Write Buffer command was issued Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count V V V V V V V V Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Device H...

Page 151: ...ts 0 7 L 1 Cylinder High Low This indicates the cylinder number of the first sector to be transferred L 0 In LBA mode this register specifies the transfer of LBA address bits 8 15 Low and 16 23 High L 1 H This indicates the head number of the first sector to be transferred L 0 In LBA mode this register specifies that LBA bits 24 27 is to be transferred L 1 R This indicates the retry bit This bit i...

Page 152: ...ster contains the current LBA bits 0 7 L 1 Cylinder High Low This indicates the cylinder number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 8 15 Low and bits16 23 High L 1 H This indicates the head number of the sector to be transferred L 0 In LBA mode this register contains the current LBA bits 24 27 L 1 ...

Page 153: ... the Sector Count register is specified then 65 536 sectors will be transferred Sector Number Current LBA 7 0 Sector Number Previous LBA 31 24 Cylinder Low Current LBA 15 8 Cylinder Low Previous LBA 39 32 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Secto...

Page 154: ...nrecoverable error Sector Number HOB 1 LBA 31 24 of the address of the first unrecoverable error Cylinder Low HOB 0 LBA 15 8 of the address of the first unrecoverable error Cylinder Low HOB 1 LBA 39 32 of the address of the first unrecoverable error Cylinder High HOB 0 LBA 23 16 of the address of the first unrecoverable error Cylinder High HOB 1 LBA 47 40 of the address of the first unrecoverable ...

Page 155: ...inder Low Current The first sector of the log to be read low order bits 7 0 Cylinder Low Previous The first sector of the log to be read high order bits 15 8 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current V V V V V V V V Sector Count HO...

Page 156: ...ssociated with the log specified in the Sector Number register is not supported or enabled or if the values in the Sector Count Sector Number or Cylinder Low registers are invalid the device shall return com mand aborted Log Address Content Feature set Type 00h Log directory N A Read Only 03h Extended Comprehensive SMART error log SMART error logging Ready Only 06h SMART self test log SMART self t...

Page 157: ... at log address 01h 7 0 1 02h Number of sectors in the log at log address 01h 15 8 1 03h Number of sectors in the log at log address 01h 7 0 1 04h Number of sectors in the log at log address 01h 15 8 1 05h Number of sectors in the log at log address 20h 7 0 1 40h Number of sectors in the log at log address 20h 7 0 1 41h Number of sectors in the log at log address 21h 7 0 1 42h Number of sectors in...

Page 158: ...rors reported by the device These error log data structure entries are viewed as a circular buffer The fifth error shall create an error log structure that replaces the first error log data structure The next error after that shall create an error log data structure that replaces the second error log structure etc Unused error log data structures shall be filled with zeros 12 17 2 3 1 Data format ...

Page 159: ...mber register 7 0 1 05h Sector number register 15 8 1 06h Cylinder Low register 7 0 1 07h Cylinder Low register 15 8 1 08h Cylinder High register 7 0 1 09h Cylinder High register 15 8 1 0Ah Device Head register 1 0Bh Command register 1 0Ch Reserved 1 0Dh Timestamp milliseconds from Power on 4 0Eh 18 Description Bytes Offset Reserved 1 00h Error register 7 0 1 01h Sector count register 7 0 See Note...

Page 160: ...og sector The figure below defines the format of each of the sectors that comprise the Extended SMART self test log The Extended SMART self test log sector shall support 48 bit and 28 bit addressing All 28 bit entries contained in the SMART self test log defined in 11 42 6 Self test log data structure on page0203 shall also be included in the Extended SMART self test log with all 48 bit entries Th...

Page 161: ...reater than 31 but only the most recent 31 errors are represented by entries in the log If the Read Stream Error Count reaches the maximum value that can be represented after the next error is detected the Read Stream Error Count shall remain at the maximum value After successful completion of a Read Log Ext command with the LBA Low Register set to 22h the Read Stream Error Log shall be reset to a...

Page 162: ... A C 8 1 1 0 0 1 0 0 0 4 R e a d D M A C 9 1 1 0 0 1 0 0 1 4 R e a d D M A E x t 2 5 0 0 1 0 0 1 0 1 1 R e a d L o n g 2 2 0 0 1 0 0 0 1 0 1 R e a d L o n g 2 3 0 0 1 0 0 0 1 1 1 R e a d L o g E x t 2 F 0 0 1 0 1 1 1 1 1 R e a d M u l ti p l e C 4 1 1 0 0 0 1 0 0 1 R e a d M u l ti p l e E x t 2 9 0 0 1 0 1 0 0 1 3 R e a d N a t iv e M a x A d d r e s s F 8 1 1 1 1 1 0 0 0 3 R e a d N a t iv e M a...

Page 163: ...Data Structure Version field shall contain a value of 02h indicating the second revision of the structure format The Write Stream Error Log Count field shall contain the number of Write Stream command entries since the last power on since this log was last read or since hardware reset was executed The Error Log Index indicates the error log data structure representing the most recent error Only va...

Page 164: ...nearly Interpolated Description Bytes Stream Perforamnce Parameters log version 2 K Number of Regions in Sector Time Array 2 L Number of Positions in Position Array 2 M Number of Position differences in Access Time Array 2 Sector Time Array K 8 Position Array L 8 Access Time Array M 4 Reserved Description Bytes LBA of reference location LBA 7 0 LBA 47 40 n n 5 Identify Device words 99 98 65536 tim...

Page 165: ...r Count must be set to one Sector Number This indicates the sector number of the sector to be transferred L 0 In LBA mode this register contains LBA bits 0 7 L 1 Cylinder High Low This indicates the cylinder number of the sector to be transferred L 0 In LBA mode this register contains LBA bits 8 15 Low 16 23 High L 1 H This indicates the head number of the sector to be transferred L 0 In LBA mode ...

Page 166: ...umber of the transferred sector L 0 In LBA mode this register contains current LBA bits 8 15 Low 16 23 High L 1 H This indicates the head number of the transferred sector L 0 In LBA mode this register contains current LBA bits 24 27 L 1 It should be noted that the device internally uses 52 bytes of ECC data on all data written or read from the disk The 4 byte mode of operation is provided via emul...

Page 167: ...le command instead of for each sector Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count V V V V V V V V Sector Count V V V V V V V V Sector Number V V V V V V V V Sector Number V V V V V V V V Cylinder Low V V V V V V V V Cylinder Low V V V V V V V V Cylinder High V V V V V V V V Cylinder Hi...

Page 168: ...A 7 0 Sector Number Previous LBA 31 24 Cylinder Low Current LBA 15 8 Cylinder Low Previous LBA 39 32 Cylinder High Current LBA 23 16 Cylinder High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current V V V V V V V V Sector ...

Page 169: ...HOB 1 LBA 31 24 of the address of the first unrecoverable error Cylinder Low HOB 0 LBA 15 8 of the address of the first unrecoverable error Cylinder Low HOB 1 LBA 39 32 of the address of the first unrecoverable error Cylinder High HOB 0 LBA 23 16 of the address of the first unrecoverable error Cylinder High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 170: ...he native max LBA bits 8 15 Low and bits 16 23 High L 1 In CHS mode this register contains the native max cylinder number L 0 H In LBA mode this register contains the native max LBA bits 24 27 L 1 In CHS mode this register contains the native maximum head number L 0 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Erro...

Page 171: ...x address Cylinder High HOB 1 LBA 47 40 of the address of the Native max address Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current Sector Count HOB 0 Previous HOB 1 Sector Number Current Sector Number HOB 0 V V V V V V V V Previous HOB 1 V...

Page 172: ... the head number of the first sector to be transferred L 0 In LBA mode this register contains the LBA bits 24 27 L 1 R This is the retry bit but this bit is ignored Input parameters from the device Sector Count This is the number of requested sectors not transferred This will be zero unless an unre coverable error occurs Sector Number This is the sector number of the last transferred sector L 0 In...

Page 173: ...is the cylinder number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 8 15 Low and bits 16 23 High L 1 H This is the head number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 24 27 L 1 ...

Page 174: ...nder Low Current LBA 15 8 Cylinder Low Previous LBA 39 32 Cylinder High Current LBA 23 16 Cylinder High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current V V V V V V V V Sector Count HOB 0 Previous V V V V V V V V HOB 1 ...

Page 175: ...HOB 1 LBA 31 24 of the address of the first unrecoverable error Cylinder Low HOB 0 LBA 15 8 of the address of the first unrecoverable error Cylinder Low HOB 1 LBA 39 32 of the address of the first unrecoverable error Cylinder High HOB 0 LBA 23 16 of the address of the first unrecoverable error Cylinder High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 176: ...nd the Command Completion Time Limit expires the device shall stop execution of the command and pro vide ending status with BSY bit cleared to zero the SE bit set to one the ERR bit cleared to zero and report the fact that the Command Completion Time Limit expired by setting the CCTO bit in the error log to one In all cases the device shall attempt to transfer the amount of data requested within t...

Page 177: ... or ABRT reported in the error log If the RC bit is set to one and the CCTL expires the device shall stop execution of the command and provide ending status with the BSY bit cleared to zero the SE bit set to one the ERR bit cleared to zero and report the fact that the CCTL expired by setting the CCTO bit in the error log to one In all cases the device shall attempt to transfer the amount of data r...

Page 178: ...ontinuous sectors to be transferred high order bits 15 8 If zero is specified in the Sector Count register then 65 536 sectors will be transferred Sector Number Current LBA 7 0 Sector Number Previous LBA 31 24 Cylinder Low Current LBA 15 8 Cylinder Low Previous LBA 39 32 Cylinder High Current LBA 23 16 Cylinder High Previous LBA 47 40 Input Parameters From The Device Sector Number HOB 0 LBA 7 0 of...

Page 179: ... If the RC bit is set to one when the command is issued and ICRC UNC IDNF ABRT or CCTO error occurs the SE bit shall be set to one the ERR bit shall be cleared to zero and the bits that would normally be set in the Error register shall be set in the error log DWE Status bit 4 DWE Deferred Write Error shall be set to one if an error was detected in a deferred write to the media for a previous Write...

Page 180: ...DNF or ABRT reported in the error log If the RC bit is set to one and the Command Completion Time Limit expires the device shall stop execution of the command and pro vide ending status with BSY bit cleared to zero the SE bit set to one the ERR bit cleared to zero and report the fact that the Command Completion Time Limit expired by setting the CCTO bit in the error log to one In all cases Command...

Page 181: ...SY bit cleared to zero the SE bit set to one the ERR bit cleared to zero and report the fact that the CCTL expired by setting the CCTO bit in the error log to one In all cases the device shall attempt to transfer the amount of data requested within the CCTL even if some data trans ferred is in error NS bit5 NS Not Sequential may be set to one if the next read stream command with the same Stream ID...

Page 182: ...nder High HOB 1 LBA 47 40 of the address of the first unrecoverable error CCTO Error bit 0 CCTO bit shall be set to one if a Command Completion Time Limit Out error has occurred SE Status bit 5 SE Stream Error shall be set to one if an error has occurred during the execution of the command and the RC bit is set to one In this case the LBA returned in the Sector Number registers shall be the addres...

Page 183: ... 23 High L 1 H This is the head number of the first sector to be transferred L 0 In LBA mode this register contains the LBA bits 24 27 L 1 R This is the retry bit this bit is ignored Input parameters from the device Sector Count This is the number of requested sectors not verified This number will be zero unless an unrecoverable error occurs Sector Number This is the sector number of the last tran...

Page 184: ...is the cylinder number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 8 15 Low and bits 16 23 High L 1 H This is the head number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 24 27 L 1 ...

Page 185: ...r Number Previous LBA 31 24 Cylinder Low Current LBA 15 8 Cylinder Low Previous LBA 39 32 Cylinder High Current LBA 23 16 Cylinder High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current V V V V V V V V Sector Count HOB 0...

Page 186: ...HOB 1 LBA 31 24 of the address of the first unrecoverable error Cylinder Low HOB 0 LBA 15 8 of the address of the first unrecoverable error Cylinder Low HOB 1 LBA 39 32 of the address of the first unrecoverable error Cylinder High HOB 0 LBA 23 16 of the address of the first unrecoverable error Cylinder High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 187: ...Register Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Device Head Command 0 0 0 1 Status see below Error Register Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 ID...

Page 188: ...y Disable Password command The device will compare the password sent from this host with that specified in the control word Identifier Zero indicates that the device should check the supplied password against the user pass word stored internally One indicates that the device should check the given password against the master password stored internally Command Block Output Registers Command Block I...

Page 189: ...to prevent accidental erasure of the device This command does not request the transfer of data Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Device Head Command 1 1 1 1 0 0 1 ...

Page 190: ...check the given password against the master password stored internally The Security Erase Unit command erases all user data and disables the security mode feature device lock func tion After the completion of this command all the user data will be initialized to zero with a write operation At this time the data write is not verified with a read operation to determine if the data sector is initiali...

Page 191: ...aborts the security erase unit command This command disables the security mode feature device lock function however the master password is still stored internally within the device and may be reactivated later when a new user password is set If you execute this command when disabling the security mode feature device lock function the password sent by the host is NOT compared with either the Master...

Page 192: ...de Security Set Password Security Unlock Security Disable Password Security Erase Unit Refer to Table 70 Command table for device lock operation on page 84 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylin...

Page 193: ...ommand Table 131 Security Set Password Information Identifier Zero indicates that the device should check the supplied password against the user password stored internally One indicates that the device should check the given password against the master password stored internally Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data...

Page 194: ...el bits The setting of the Identifier and Security level bits interact as follows Identifier User Security level High The password supplied with the command will be saved as the new user password The security mode feature lock function will be enabled from the next power on The drive may then be unlocked by either the user password or the previously set master password Identifier Master Security l...

Page 195: ...word If the password compare fails the device returns an abort error to the host and decrements the unlock attempt counter This counter is initially set to five and is decremented for each password mismatch When this counter reaches zero all password protected commands are rejected until there is a hard reset or a power off Identifier A zero indicates that the device regards Password as the User P...

Page 196: ...has failed due to a mismatched password since this is the only reason that an abort error will be returned by the drive AFTER the password information has been sent to the device An abort error returned by the device BEFORE the password data has been sent to the drive indicates that another problem exists ...

Page 197: ...meters from the device Sector Number In LBA mode this register contains the current LBA bits 0 7 L 1 Cylinder High Low In LBA mode this register contains the current LBA bits 8 15 Low and bits16 23 High L 1 H In LBA mode this register contains the current LBA bits 24 27 L 1 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feat...

Page 198: ...1 1 1 1 Status see below Error Register Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AMN BSY RDY DF DSC DRQ COR IDX ERR 0 0 0 0 0 V 0 0 0 V 0 0 V 02H Enable write cache 03H Set transfer mode based on value in sector count register 05H Enable Advanced Power Management 06H Enable Power up in Standby feature set 07H Power up in Standby feature set device spin up 09H Enable ...

Page 199: ...agement When the Feature Register is 05h Enable Advanced Power Management the Sector Count Register specifies the Advanced Power Management level The idle time to Low power idle mode and Low RPM standby mode vary according to the value in Sector Count register as follows When Low power idle mode is the deepest Power Saving mode Write cache Enable ECC bytes 4 bytes Read look ahead Enable Reverting ...

Page 200: ...becomes 120 seconds when Low RPM standby mode is enabled Enabled Power Saving mode and idle time y1 and y2 are preserved until Advanced Power Management is dis abled the deepest Power Saving mode becomes Normal Idle mode or a new time is set They are initialized with a hard soft reset unless Reverting to Power on defaults is disabled and the devise receives a soft reset Additional electronics are ...

Page 201: ...r Count Register specifies the Automatic Acoustic Management level The device preserves enabling or disabling of Automatic Acoustic Management and the current Automatic Acous tic Management level setting across all forms of reset that is Power on Hardware and Software Resets FFH Aborted C0 FEh Set to Normal Seek mode 80 BFh Set to Quiet Seek mode 00 7Fh Aborted ...

Page 202: ...evice returns command aborted for a second nonvolatile Set Max Address command until the next power on or hardware reset The device returns command aborted during Set Max Locked mode or Set Max Frozen mode After a successful command completion Identify Device response words 61 60 shall reflect the maximum address set with this command If the 48 bit Address feature set is supported the value placed...

Page 203: ...r In LBA mode this register contains LBA bits 0 7 which is to be set L 1 In CHS mode this register is ignored L 0 Cylinder High Low In LBA mode this register contains LBA bits 8 15 Low 16 23 High which is to be set L 1 In CHS mode this register contains cylinder number which is to be set L 0 H In LBA mode this register contains LBA bits 24 27 which is to be set L 1 In CHS mode this register is ign...

Page 204: ... accepts this command the device is in Set_Max_Unlocked state Table 137 Set Max Set Password data contents Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature 0 0 0 0 0 0 0 1 Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Device...

Page 205: ...ted The device remains in this state until a power cycle or the acceptance of a Set Max Unlock or Set Max Freeze Lock command Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature 0 0 0 0 0 0 1 0 Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Devic...

Page 206: ...tially set to 5 and is decremented for each password mismatch When this counter reaches zero all Set Max Unlock commands are rejected until a hard reset or a power off occurs If the password compare matches the device sets the Set_Max_Unlocked state and all Set Max commands are accepted Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 D...

Page 207: ...cted The following commands are disabled by Set Max Freeze Lock Set Max Address Set Max Set PASSWORD Set Max Lock Set Max Unlock Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature 0 0 0 0 0 0 1 0 Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High De...

Page 208: ...nd or the device is in the Set Max Locked or Set Max Frozen state the device shall return command aborted If the device in Address Offset mode receives this command with the nonvolatile option the device returns aborted error to the host The device returns the command aborted for a second non volatile Set Max Address Ext command until next power on or hardware reset Command Block Output Registers ...

Page 209: ...is not valid when the device is in Address Offset mode Sector Number Current Set Max LBA 7 0 Sector Number Previous Set Max LBA 31 24 Cylinder Low Current Set Max LBA 15 8 Cylinder Low Previous Set Max LBA 39 32 Cylinder High Current Set Max LBA 23 16 Cylinder High Previous Set Max LBA 47 40 Input parameters from the device Sector Number HOB 0 Set Max LBA 7 0 Sector Number HOB 1 Set Max LBA 31 24 ...

Page 210: ...indicates the block size to be used for the Read Multiple and the Write Multiple com mands Valid block sizes can be selected from 0 1 2 4 8 or 16 If 0 is specified then the Read Multiple and the Write Multiple commands are disabled Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count V V V V V ...

Page 211: ...et is the only way to recover from Sleep Mode Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Device Head Command 1 1 1 0 0 1 1 0 Status see below Error Register Status Register...

Page 212: ... to select a subcommand the host must write the subcommand code to the Features Register of the device before issuing the S M A R T Function Set command The subcommands and their respective codes are listed below Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature V V V V V V V V Error see below Sector Count V V V V V V V...

Page 213: ...00h written by the host into the Sector Count Register of the device before issuing the S M A R T Enable Disable Attribute Autosave subcommand will cause this feature to be disabled Disabling this feature does not preclude the device from saving Attribute Values to the Attribute Data sectors during another normal operation such as a power up or a power down A value of F1h written by the host into ...

Page 214: ...routine automatically or not start its routine depending on the interrupting command Captive mode When executing self test in captive mode the device sets BSY to one and executes the specified self test routine after receipt of the command At the end of the routine the device sets the execution result in the Self test execution status byte see Table 145 Device Attribute Data Structure on page 213 ...

Page 215: ...device After receipt of this subcommand the device disables all S M A R T operations Non self preserved Attribute Values will no longer be monitored The state of S M A R T either enabled or disabled is preserved by the device across power cycles Upon receipt of the S M A R T Disable Operations subcommand from the host the device asserts BSY disables S M A R T capabilities and functions clears BSY ...

Page 216: ...itiate or resume performance of its off line data collection activities or cause the Automatic Off line Data Collection feature to be disabled A value of zero written by the host into the Sector Count register of the device before issuing this subcommand causes the feature to be disabled Disabling this feature does not preclude the device from saving attribute values to nonvolatile memory during s...

Page 217: ...e 12 bytes that make up the information for each Attribute entry in the Device Attribute Data Structure Table 146 Individual Attribute Data Structure Description Byte Offset Format Value Data Structure Revision Number 2 00h binary 0010h 1st Device Attribute 12 02h 1 30th Device Attribute 12 15Eh 1 Off line data collection status 1 16Ah 1 Self test execution status 1 16Bh 1 Total time in seconds to...

Page 218: ...ne testing 2 5 Vendor specific 6 15 Reserved 0 Normalized values The device performs conversion of the raw Attribute Values to transform them into normal ized values which the host can then compare with the Threshold values A Threshold is the excursion limit for a normalized Attribute Value 12 42 2 3 Off Line Data Collection Status The value of this byte defines the current status of the off line ...

Page 219: ...ented bit 0 S M A R T Enable disable Automatic Off line subcommand is not implemented 1 S M A R T Enable disable Automatic Off line subcommand is implemented 2 Abort restart off line by host bit 0 The device will suspend off line data collection activity after an interrupting command and resume it after a vendor specific event 1 The device will abort off line data collection activity upon receipt ...

Page 220: ...r Sleep mode 1 Attribute Autosave capability If bit 1 the device supports the S M A R T ENABLE DISABLE ATTRIBUTE AUTOSAVE command 2 15 Reserved 0 12 42 2 8 Error logging capability Bit Definition 7 1 Reserved 0 0 The Error Logging support bit If bit 1 the device supports the Error Logging 12 42 2 9 Self test failure check point This byte indicates the section of self test where the device detected...

Page 221: ... entries in the Individual Attribute Data Structure 12 42 3 3 Attribute ID Numbers Attribute ID Numbers supported by the device are the same as Attribute Values Data Structures 12 42 3 4 Attribute Threshold These values are preset at the factory and are not meant to be changeable 12 42 3 5 Data Structure Checksum The Data Structure Checksum is the two s complement of the result of a simple 8 bit a...

Page 222: ...og sector 12 42 5 1 S M A R T error log version This value is set to 01h 12 42 5 2 Error log pointer This points to the most recent error log data structure Only values 1 through 5 are valid 12 42 5 3 Device error count This field contains the total number of errors The value will not roll over Description Byte Offset S M A R T Logging Version 2 00h Number of sectors in the log at log address 1 1 ...

Page 223: ...ture 12 0Ch 3rd command data structure 12 18h 4th command data structure 12 24h 5th command data structure 12 30h Error data structure 30 3Ch 90 Description Byte Offset Device Control register 1 00h Features register 1 01h Sector count register 1 02h Sector number register 1 03h Cylinder Low register 1 04h Cylinder High register 1 05h Device Head register 1 06h Command register 1 07h Time stamp ms...

Page 224: ... contain up to 21 descriptors After 21 descriptors has been recorded the oldest descriptor will be overwritten with the new descriptor The self test log index points to the most recent descriptor When there is no descriptor the value is 0 When there are one or more descriptors the value is 1 through 21 Life time stamp hours 2 1Ch 30 Value State x0h Unknown x1h Sleep x2h Standby x3h Active Idle x4h...

Page 225: ...aded into the Cylinder High and Cylinder Low registers 51h 04h A S M A R T FUNCTION SET command was received by the device with a subcommand value in the Features Regis ter that is either invalid or not supported by this device 51h 04h A S M A R T FUNCTION SET command subcommand other than S M A R T ENABLE OPERATIONS was received by the device while the device was in a S M A R T Disabled state 51h...

Page 226: ...s to the device Sector Count Time out Parameter If it is 0 the time out interval Standby Timer is NOT disabled If it is non zero the automatic power down sequence is enabled The time out interval is shown below Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count V V V V V V V V Sector Count Se...

Page 227: ...tic power down sequence is enabled the device will enter the Standby mode automatically if the time out interval expires with no device access from the host The time out interval will be reinitialized if there is a drive access before the time out interval expires ...

Page 228: ...delay while waiting for the spindle to reach operating speed The Standby Immediate command will not affect the auto power down time out parameter Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High D...

Page 229: ...ial Write Buffer and Read Buffer commands access the same 512 byte within the buffer Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Device Head Command 1 1 1 0 1 0 0 0 Status s...

Page 230: ...he LBA bits 0 7 L 1 Cylinder High Low This indicates number of the first sector to be transferred L 0 In LBA mode this reg ister contains the LBA bits 8 15 Low and bits 16 23 High L 1 H This indicates the head number of the first sector to be transferred L 0 In LBA mode this register contains the LBA bits 24 27 L 1 R This indicates the retry bit This bit is ignored Input parameters from the device...

Page 231: ...ster contains the current LBA bits 0 7 L 1 Cylinder High Low This indicates the cylinder number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 8 15 Low and bits 16 23 High L 1 H This indicates the head number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 24 27 L 1 ...

Page 232: ...der bits 15 8 If zero is specified in the Sector Count register 65 536 sectors will be transferred Sector Number Current LBA 7 0 Sector Number Previous LBA 31 24 Cylinder Low Current LBA 15 8 Cylinder Low Previous LBA 39 32 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see b...

Page 233: ...nrecoverable error Sector Number HOB 1 LBA 31 24 of the address of the first unrecoverable error Cylinder Low HOB 0 LBA 15 8 of the address of the first unrecoverable error Cylinder Low HOB 1 LBA 39 32 of the address of the first unrecoverable error Cylinder High HOB 0 LBA 23 16 of the address of the first unrecoverable error Cylinder High HOB 1 LBA 47 40 of the address of the first unrecoverable ...

Page 234: ...t sector of the log to be written low order bits 7 0 Cylinder Low Previous The first sector of the log to be written high order bits 15 8 If the feature set associated with the log specified in the Sector Number register is not supported or enabled or if the values in the Sector Count Sector Number or Cylinder Low registers are invalid the device shall return com mand aborted If the host attempts ...

Page 235: ...is indicates the cylinder number of the sector to be transferred L 0 In LBA mode this register contains the LBA bits 8 15 Low and bits 16 23 High L 1 H This indicates the head number of the sector to be transferred L 0 In LBA mode this register contains the LBA bits 24 27 L 1 R The retry bit This bit is ignored Input parameters from the device Sector Count This indicates the number of requested se...

Page 236: ...ector to be transferred L 0 In LBA mode this register contains current the LBA bits 24 27 L 1 The drive internally uses 52 bytes of ECC on all data read or writes The 4 byte mode of operation is provided by means of an emulation technique As a consequence of this emulation it is recommended that 52 byte ECC mode be used for all tests to confirm the operation of the ECC hardware of the drive Unexpe...

Page 237: ...r contains the LBA bits 8 15 Low and bits 16 23 High L 1 H This indicates the head number of the first sector to be transferred L 0 In LBA mode this register contains the LBA bits 24 27 L 1 Input parameters from the device Sector Count This indicates the number of requested sectors not transferred The Sector Count will be zero unless an unrecoverable error occurs Sector Number This indicates the s...

Page 238: ...es the cylinder number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 8 15 Low and bits 16 23 High L 1 H This indicates the head number of the last transferred sector L 0 In LBA mode this register contains current the LBA bits 24 27 L 1 ...

Page 239: ... Sector Number Previous LBA 31 24 Cylinder Low Current LBA 15 8 Cylinder Low Previous LBA 39 32 Cylinder High Current LBA 23 16 Cylinder High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current V V V V V V V V Error See below Previous V V V V V V V V Sector Count Curr...

Page 240: ...HOB 1 LBA 31 24 of the address of the first unrecoverable error Cylinder Low HOB 0 LBA 15 8 of the address of the first unrecoverable error Cylinder Low HOB 1 LBA 39 32 of the address of the first unrecoverable error Cylinder High HOB 0 LBA 23 16 of the address of the first unrecoverable error Cylinder High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 241: ...es the head number of the first sector to be transferred L 0 In LBA mode this register contains the LBA bits 24 27 L 1 R This indicates the retry bit this bit is ignored Input parameters from the device Sector Count This indicates the number of requested sectors not transferred This will be zero unless an unrecoverable error occurs Sector Number This indicates the sector number of the last transfe...

Page 242: ...ates the cylinder number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 8 15 Low and 16 23 High L 1 H This indicates the head number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 24 27 L 1 ...

Page 243: ...ylinder Low Previous LBA 39 32 Cylinder High Current LBA 23 16 Cylinder High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error See below Previous Sector Count Current V V V V V V V V Sector Count HOB 0 Previous V V V V V V V V HOB 1 Sector Number Current V V V...

Page 244: ...HOB 1 LBA 31 24 of the address of the first unrecoverable error Cylinder Low HOB 0 LBA 15 8 of the address of the first unrecoverable error Cylinder Low HOB 1 LBA 39 32 of the address of the first unrecoverable error Cylinder High HOB 0 LBA 23 16 of the address of the first unrecoverable error Cylinder High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 245: ...t set to one the ERR bit cleared to zero and report the fact that the Command Completion Time Limit expired by setting the CCTO bit in the error log to one In all cases the device shall attempt to transfer the amount of data requested within the Command Completion Time Limit event if some data transferred is in error Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2...

Page 246: ...that all data for the specified stream shall be flushed to the media before command complete is reported when set to one HSE bit4 HSE Handle Stream Error specifies that this command starts at the LBA of the last reported error for this stream so the device may attempt to continue its corresponding error recovery sequence where it left off earlier Stream ID bit 0 2 Stream ID specifies the stream be...

Page 247: ...mand Completion Time Limit expired by setting the CCTO bit in the error log to one In all cases the device shall attempt to transfer the amount of data requested within the Command Completion Time Limit event if some data transferred is in error Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Featu...

Page 248: ...s that all data for the specified stream shall be flushed to the media before command complete is reported when set to one HSE bit4 HSE Handle Stream Error specifies that this command starts at the LBA of the last reported error for this stream so the device may attempt to continue its corresponding error recovery sequence where it left off earlier Stream ID bit 0 2 Stream ID specifies the stream ...

Page 249: ...5 SE Stream Error shall be set to one if an error has occurred during the execution of the command and the WC bit is set to one In this case the LBA returned in the Sector Number registers shall be the address of the first sector in error and the Sector Count registers shall contain the number of consecutive sectors that may contain errors If the WC bit is set to one when the command is issued and...

Page 250: ...Deskstar 7K80 Hard Disk Drive Specification 246 ...

Page 251: ...1 31 sec Hard Reset Device Busy After Hard Reset Bus RESET Signal Asserted Status Register BSY 1 400 ns Device Ready After Hard Reset Bus RESET Signal Asserted Status Register BSY 0 and RDY 1 31 sec Data In Com mand Device Busy After Com mand Code Out OUT To Command Register Status Register BSY 1 400 ns Interrupt DRQ For Data Transfer In Status Register BSY 1 Status Register BSY 0 and DRQ 1 Interr...

Page 252: ...er Managemen 102 Alternate Status Register 74 AT signal connector 33 Attribute thresholds 87 Attribute values 87 Attributes 87 Auto Reassign function 100 Automatic Acoustic Management 103 B BSMI mark 70 BSY 79 C Cable noise interference 61 Cabling 50 Capacity formatted 21 Caution 13 CE mark 70 Command descriptions 115 Command overhead 24 Command protocol 109 Command Register 74 Command table 94 Co...

Page 253: ...sfer speed 27 DC power connector 33 DC power requirements 59 Defect flagging strategy 31 Deviations from standard 71 Device Control Register 75 Device Terminating Write DMA 48 Device Head Register 76 DMA commands 113 DMA Data Transfer commands 113 Drive Address Register 76 Drive characteristics 21 Drive format 22 Drive organization 22 Drive ready time 26 E Electrical interface 33 Electrical interf...

Page 254: ...eatures 15 General operation 81 H Handle Streaming Error bit 108 Head disk assembly 19 Head disk assembly data 19 Heads unload 64 Host Terminating Write DMA 49 Humidity 58 I Identification labels 68 Initiating Read DMA 42 Initiating Write DMA 46 Input voltage 59 Interface capability for power modes 86 Interface logic signal levels 38 Interface specification 51 Introduction 11 J Jumper pin location...

Page 255: ... 90 Mechanical positioning 24 Mechanical specifications 62 Mode transition time 29 Mounting hole locations 62 63 Mounting orientation 64 Multi word DMA timings 41 N Non data commands 112 Not Sequential bit 108 O Off line read scanning 87 Operating modes 29 description 27 Operating shock 66 Operation example 90 P Packaging 70 Passwords 90 Performance characteristics 24 Physical dimensions 62 PIO ti...

Page 256: ... 73 Reset response 81 Reset timings 38 S S M A R T commands 87 S M A R T Function Set 208 Safety 69 Secondary circuit protection 69 Sector Addressing 84 Sector Addressing Mode 84 Sector Count Register 77 Sector Number Register 78 Security extensions 97 Security level 89 Security mode 89 Security Mode Feature Set 89 Seek overlap 98 Self test 88 Shock 65 Signal definitions 34 Signal descriptions 35 ...

Page 257: ...ature 58 Threshold exceeded condition 87 Time out values 247 Timings 247 reset 38 U UL approval 69 Ultra DMA timings 42 Urgent bit 107 V Vibration 65 W Weight 62 World Wide Name Assignment 22 Write Buffer 225 Write cache function 99 Write Continuous bit 108 ...

Page 258: ...stered trade marks of their respective companies References in this publication to Hitachi Global Storage Technologies products programs or services do not imply that Hitachi Global Storage Technologies intends to make these available in all countries in which Hitachi Global Storage Technologies operates Product information is provided for information pur poses only and does not constitute a warra...

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