6.2.3 Multiword DMA timings
The Multiword DMA timing meets Mode 2 of the ATA/ATAPI-6 description.
WRITE DATA
READ DATA
DMACK-
DMARQ
DIOR-/DIOW-
t0
tLR/tLW
tJ
tI
tD
tKR/tKW
tF
tG
tH
tG
tZ
CS0-/CS1-
tM
tN
tE
Figure 25. Multiword DMA cycle timing chart
25
–
DMACK– to read data released
tZ
–
10
CS (1:0) hold
tN
–
25
CS (1:0) valid to DIOR–/DIOW–
tM
35
–
DIOR–/DIOW– to DMARQ– delay
tLR/tLW
–
25
DIOR–/DIOW– negated pulse width
tKR/tKW
–
5
DIOR–/DIOW– to DMACK– hold
tJ
–
0
DMACK– to –DIOR–/DIOW– setup
tI
–
10
DIOW– data hold
tH
–
20
DIOR–/DIOW– data setup
tG
–
5
DIOR– data hold
tF
50
–
DIOR– data access
tE
–
70
DIOR–/DIOW– asserted pulse width
tD
–
120
Cycle time
t0
MAX (ns)
MIN (ns)
PARAMETER DESCRIPTION
Figure 26. Multiword DMA cycle timings
Deskstar 180GXP hard disk drive specifications
29
Summary of Contents for Deskstar 180GXP
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