hilscher netRAPID 90, Design Manual

Page: 53 / 108

Electrical aspects for the stand-alone solution 53/108
Example
The ADC input is driven by a low-ohmic shunt resistor, e.g. 200 mΩ. The
RC-network needs a minimum time of (R
in
+ R
ext
) x C
in
x 9, where R
in
is ADC_MUX_RSER and C
in
is ADC_MUX_CIN.
Assuming the ADC clock period is 30 ns (default setting is 70 ns), the settle
time is
(1.5 kΩ + 0.2 Ω) x 10pF x 9 = 135 ns
.
The sampling time by default is 2 cycles, i.e. 2 x 30 ns = 60 ns.
As a result, the sampling time must be extended. The additional delay can
be programmed by register and is calculated
tt_add = ceil( ( (Rint + Rext) x 9 x Cin / Period) - 2)
= 3
.
Symbol Parameter Conditions Min Typ Max Unit
ADC_RES Resolution 12 Bits
ADC_ENOB ENOB FIn = 50
kHz 10.5 Bits
ADC_INL INL -1.5 1.5 LSB
ADC_DNL DNL -1 2 LSB
ADC_OFSERR Offset error
1) -15 15 LSB
ADC_GAINERR Fullscale
gain - Error
1) -5 5 LSB
ADC_SRATE Minimal
tracking
phase of 2
cycles used ADC_CLK /
14 MSa/s
ADC_CLK ADC clock
period Programma
ble by
register 30 90 ns
ADC_MUX_CIN Input
capacitance
ADC0 and
ADC1 10 pF
ADC_MUX_CIN Input
capacitance
ADC2 and
ADC3 12 pF
ADC_MUX_RSER Serial
resistance 1.5 kΩ
ADC_WARMUP Warm-up
time ADC_ENA
BLE 0 →1 10 Μs
ADC_MUX_CIN Input
capacitance
ADC2 and
ADC3 12 pF
ADC_MUX_RSER Serial
resistance 1.5 kΩ
ADC_WARMUP Warm-up
time ADC_ENA
BLE 0 →1 10 μs
ADC_REF Reference
voltage T=27 °C 2.55 2.6 2.65 V
netRAPID 90 | Design guide
DOC190601DG01EN | Revision 1 (Draft 10) | English | 2019-09 | Preliminary | Public © Hilscher 2019