Date printed: 24.01.12
34
D21m System
6.3 digital I/O Cards
6.3.1 aES/EBU M2 Cards
(
and
)
A949.0454, A949.0455, A949.0456
AES/EBU input/output card with 16 Ch I/O, available in 3 different versions:
A949.0454xx
without SRCs (Sampling Rate Converters; Vista only)
A949.0455xx
with input SRCs only
A949.0456xx
with input and output SRCs (see adjacent picture).
Selectable output sampling rates: 96 kHz, 48 kHz, 44.1 kHz, or external refer-
ence (22-108 kHz). Input and output SRCs can individually be bypassed per
channel pair. Output dither and word length is selectable for every AES/EBU
output to 24, 20, 18 or 16 bit (when the output SRC is enabled). Settings are
made with DIP switches. Inputs and outputs are on standard 25-pin D-type
connectors (female).
SRC Delay
Enabled input and output SRCs each cause a delay (D) that depends on the
SRC’s input and output sampling rate (f
S_IN
and f
S_OUT
). Input and output delays
can be calculated using the following formulas.
[2]
f
S_OUT
> f
S_IN
:
D =
48
f
S_IN
[s]
[1]
f
S_IN
> f
S_OUT
:
D =
16
f
S_IN
+
[s]
32
f
S_OUT
Examples: For a 96 kHz input signal and a 48 kHz system clock (i.e., the ‘output signal’
of the input SRC), input delay is 40 output samples or 0.833 ms (formula [1]).
For a 48 kHz system clock (i.e., the ‘input signal’ of the output SRC) and a
96 kHz output signal, output delay is 96 output samples or 1 ms (formula [2]).
Input / output impedance
110
Ω
Input sensitivity
min. 0.2 V
Output level
(into 110
Ω
)
4.0 V
THD + noise
max. –115 dB
SRC range
22-108 kHz
Current consumption
(3.3 V) A949.0454: 0.43 A/.0455: 0.67 A/.0456: 0.94 A
(5 V)
0.45 A
Operating temperature
0-40 °C
Backplane Connector
SRC Bypass**
Clock Selection*
96 k, 48 k, 44.1 k, ext.
Word Length Sel.*
24, 20, 18, 16 bit
Z, C, U bit location
* for A949.0456xx only ** for A949.0455xx and A949.0456xx only
AES Tx 1
AES Rx Sync*
AES Tx 8
AES Rx 1
AES Rx 8
AES Out 1
AES Sync In *
AES Out 8
AES In 1
AES In 8
SRC Out 1*
SRC In 8**
SRC Out 8*
SRC In 1**
