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M29W800DT, M29W800DB

BUS OPERATIONS

There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby and Automatic Standby. See
Tables

and

, Bus Operations, for a summary.

Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect bus operations.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Inputs, applying a Low signal, V

, to Chip Enable

and Output Enable and keeping Write Enable
High, V

. The Data Inputs/Outputs will output the

value, see

Figure 12., Read Mode AC Waveforms

and

Table 12., Read AC Characteristics

for details

of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En-
able must remain High, V

, during the whole Bus

Write operation. See Figures

and

, Write AC

Waveforms, and Tables

and

, Write AC

Characteristics, for details of the timing require-
ments.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, V

Standby. When Chip Enable is High, V

, the

memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high-imped-

ance state. To reduce the Supply Current to the
Standby Supply Current, I

CC2

, Chip Enable should

be held within V

± 0.2V. For the Standby current

level see

Table 11., DC Characteristics

During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, I

CC3

, for Program or Erase operations un-

til the operation completes.
Automatic Standby. If CMOS levels (V

± 0.2V)

are used to drive the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
duced to the Standby Supply Current, I

CC2

. The

Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Special Bus Operations. Additional bus opera-
tions can be performed to read the Electronic Sig-
nature and also to apply and remove Block
Protection. These bus operations are intended for
use by programming equipment and are not usu-
ally used in applications. They require V

to be

applied to some pins.
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Tables

and

, Bus Operations.

Block Protection and Blocks Unprotection.
Each block can be separately protected against
accidental Program or Erase. Protected blocks
can be unprotected to allow data to be changed.
There are two methods available for protecting
and unprotecting the blocks, one for use on pro-
gramming equipment and the other for in-system
use. Block Protect and Chip Unprotect operations
are described in

APPENDIX C.

Table 2. Bus Operations, BYTE = V

Note: X = V

or V

Operation

Address Inputs

DQ15A–1, A0-A18

Data Inputs/Outputs

DQ14-DQ8

DQ7-DQ0

Bus Read

Cell Address