H3C UniServer R6900 G5, Manual

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Figure 17 DIMM population schemes (four processors present)(for processors 3 and 4)
Guidelines for mixture installation of DCPMMs and DRAM DIMMs
When you install DRAM DIMMs and DCPMMs on the server, follow these restrictions and guidelines:
•
Make sure the corresponding processors are present before powering on the server.
•
Make sure all DRAM DIMMs have the same product code and all DCPMMs have the same
product code. For information about DIMM product codes, visit the query tool at
http://www.h3c.com/cn/Service/Document_Software/Document_Center/Server/ .
•
If two processors are present, populate DIMMs as shown in Figure 18 .
Figure 18 DIMM population for mixed installation (two processors present)
•
If four processors are present, populate DIMMs as shown in Figure 19 and Figure 20 .
Figure 19 DIMM population scheme for mixed installation (four processors present)(for
processors 1 and 2)
Figure 20 DIMM population scheme for mixed installation (four processors present)(for
processors 3 and 4)
Prerequisites
Take the following ESD prevention measures:
•
Wear antistatic clothing.
•
Wear an ESD wrist strap and make sure it makes good skin contact and is reliably grounded.
•
Do not wear any conductive objects, such as jewelry or watches.
When you replace a component, examine the slot and connector for damages. Make sure the pins
are not damaged (bent for example) and do not contain any foreign objects.
F0 F1 E0 E1 D0 D1 A1 A0 B1 B0 C1 C0 F0 F1 E0 E1 D0 D1 A1 A0 B1 B0 C1 C0
1
*
2
*
3 *
●
4
√
● ●
7
*
● ●
16 √
● ● ● ● ● ● ● ●
18
*
● ● ● ● ● ● ● ●
20
*
● ● ● ● ● ● ● ●
22 *
● ● ● ● ● ● ● ● ● ●
24
√
● ● ● ● ● ● ● ● ● ● ● ●
30 *
● ● ● ● ● ● ● ● ● ● ● ●
36
*
● ● ● ● ● ● ● ● ● ● ● ●
42
*
● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●
48 √
● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●
DIMM population schemes
Number of DIMMs
√
Recommended
* Not recommended
CPU 3 CPU 4
CH6 CH5 CH4 CH1 CH2 CH3 CH6 CH5 CH4 CH1 CH2 CH3
F0 F1 E0 E1 D0 D1 A1 A0 B1 B0 C1 C0 F0 F1 E0 E1 D0 D1 A1 A0 B1 B0 C1 C0
12 12 DRAM
DCPMM
DRAM
DCPMM
DRAM
DCPMM DCPMM
DRAM
DCPMM
DRAM
DCPMM
DRAM DRAM
DCPMM
DRAM
DCPMM
DRAM
DCPMM DCPMM
DRAM
DCPMM
DRAM
DCPMM
DRAM
CH3
DIMM population schemes
CPU 2 CPU 1
CH6 CH5 CH4 CH1 CH2 CH3 CH6 CH5
DRAMs DCPMMs
CH4 CH1 CH2
F0 F1 E0 E1 D0 D1 A1 A0 B1 B0 C1 C0 F0 F1 E0 E1 D0 D1 A1 A0 B1 B0 C1 C0
24 24 DRAM
DCPMM DRAM DCPMM DRAM DCPMM DCPMM DRAM DCPMM DRAM DCPMM DRAM
DRAM
DCPMM DRAM DCPMM DRAM DCPMM DCPMM DRAM DCPMM DRAM DCPMM DRAM
CH5 CH4 CH1 CH2 CH3
DRAMs DCPMMs
DIMM population scheme
CPU1 CPU2
CH6 CH5 CH4 CH1 CH2 CH3 CH6
F0 F1 E0 E1 D0 D1 A1 A0 B1 B0 C1 C0 F0 F1 E0 E1 D0 D1 A1 A0 B1 B0 C1 C0
24 24 DRAM
DCPMM DRAM DCPMM DRAM DCPMM DCPMM DRAM DCPMM DRAM DCPMM DRAM
DRAM
DCPMM DRAM DCPMM DRAM DCPMM DCPMM DRAM DCPMM DRAM DCPMM DRAM
CH3
DRAMs DCPMMs
DIMM population scheme
CPU3 CPU4
CH6 CH5 CH4 CH1 CH2 CH3 CH6 CH5 CH4 CH1 CH2