Guardian G25AMK005, Technical Manual

Page: 40 / 85

3-10 G U A R D I A N V H F 1 1 0 W M O B I L E
upper path signal removes the dc component from the upper path signal. Following this, the resulting signal passes
through a single-bit quantizer and the output buffered for use by the code removal step. Data extraction and DCS
code comparisons are then accomplished.
3.3.2.3.3 CVSD DES Detection
Detection of CVSD DES waveform is performed by a secure detection function. This function also recovers the
12 kbps bit stream from the 48 ksps input signal. The detector looks for a 12 kbps data stream to determine if a
CVSD signal is received.
3.3.2.4 Project 25 Voice Module
The physical layer task extracts FS, NID, SS symbols, and data. All other dibits are passed to the receive framing
task. The module performs recovery and symbol extraction based on frame synchronization using a correlation
detector. Symbol extraction and error-correction decoding follow carrier frequency offset compensation.
VOCODER data and Project 25 framing data is removed and secure mode decryption performed. The VOCODER
converts the compressed voice data stream to a 8 ksps audio data stream that is sent to the Modulation module.
3.3.2.5 Analog FM Module
The analog FM module performs two tasks. The detection task uses an FIR filter to down-sample the FM
demodulated bit stream from 48 ksps to 8 ksps. It then uses four detectors (noise, single-tone CTCSS, multi-tone
CTCSS, and multi-code DCS) to determine signal squelch. The post-detection audio-shaping task applies de-
emphasis on/off filtering to a received clear analog signal.
3.3.2.6 CVSD DES Module
The CVSD DES module consists of a 12 kbps clock detection/recovery task, a 12 kbps symbol resolver, a
differential decoder, a DES decoder, a 12 kbps CVSD decoder, and a 12 ksps to 8 ksps sample rate converter. The
input to the clock detection algorithm is a 48 ksps data stream, representing the sampled FM demodulated carrier.
To allow for variation in carrier frequency, the dc component of the demodulated carrier is removed before zero-
crossing detection. From a zero-crossing phase profile, a decision can be made whether a 12 ksps data stream is
present on the demodulated carrier, or a 12 kHz clock recovered for usage within the 12 kbps symbol resolver.
Differential encoding of the binary FSK modulation ensures compatibility between manufacturers, so that either a
positive or negative frequency shift can be used to represent a 1 symbol. In the CVSD receive chain, differential
decoding precedes one-bit cipher feedback DES decoding. To conserve memory and aid processing efficiency, all
symbols (encoded and decoded) are packed in memory. The 12 kbps CVSD decoder is modeled after FED-STD-
1023.
The decoder consists of a modulation level analyzer (MLA), a syllabic filter, a pulse modulator, a principal
integrator and a comparator. The output of the CVSD decoder is at 12 kbps and must be changed to 8 ksps for
output by the CODEC.
3.3.2.7 Audio Processing Module
An audio receive task function and an audio filter is used to output Project 25, clear analog, or secure analog speech
samples to the CODEC. When in active receive modes, the ISR is enabled and the task outputs data to the CODEC
circular buffer as data is written to it’s audio input circular buffer.
3.3.2.8 Audio CODEC
The audio CODEC and the DSP interface uses the DSP ESSI 0 port. The serial clock to the CODEC operates at
2.048 MHz, and is derived from the DSP internal clock. ESSI 0 is configured to operate using a frame rate divider
of 16 and a word length of 16 bits, transmitting packets of encoded audio to the CODEC at 8 kHz. The CODEC is
used in a linear decode mode, where 13 bits are used to represent the full audio range. The post-processed DSP
signal is fed to the audio CODEC, which converts the signal to an analog waveform, applies gain, and routes it to
the appropriate output device.