Guardian G25AMK005, Technical Manual

Page: 17 / 85

G U A R D I A N V H F 1 1 0 W M O B I L E 2-7
LCDA0: LCD controller A0 command/ data select
LCDCS: LCD chip select
SCL: I
2
C and synthesizer clock
DACSDA: Transceiver serial data, synthesizer, DAC, S-R
SYNTHENA: Synthesizer framing pulse
DACENA: DAC framing pulse
SRENA: S-R framing pulse
/DINT: Interrupt to DSP from H8
/RESO: Watchdog output from H8
2.4.1.12 H8 Input/Output Requirements
The total requirements for parallel input/output signals on H8, which need to be read and controlled are:
BATBUS: Not used in the mobile configurations
SDA: I
2
C data
2.4.1.13 H8 Input Interrupt Requirements
The total requirements for parallel input interrupt signals on H8 are:
LBOUT: Not used in the mobile configuration
DSPINT DSP: Interrupt
2.4.2 DSP
The DSP56309 (or DSP56302) processor implements all baseband signal-processing functions in the radio. It
interfaces with the transceiver through one ESSI port, to the user for voice through the second ESSI port. The DSP
function is controlled by H8 through the DSP host port. The DSP has direct access to the main Flash memory
through the bus arbitration logic in H8, this allows it to download program images. The initial power-on code
download is through the host port. The hardware-reset line resets the DSP. The TCXO clock output line clocks the
DSP at 12.288 MHz. The DSP ESSI 1 port is used to provide a synchronous interface to the IF ADC and the
transceiver 12-bit DAC. In receive modes that interface is capable of writing to the DAC at 48 ksps while still
reading the ADC at 96 ksps. The DSP ESSI “0” port is used to provide a full-duplex synchronous interface to the
audio CODEC using 8 kHz sampling rate and 13 bit samples. The data transfer is at 2.048 MHz using a DSP
sourced clock and framing pulse.
2.4.3 Flash ROM
A 512k x16 Flash ROM is used as the main program store for the H8 controller and DSP. The Flash ROM uses a
protected boot sector that is factory programmed via the DSP JTAG port. Normal reprogramming is implemented
by running H8 from the boot sector and using 3V, programming the bulk of the device. The Flash is used to provide
a parameter storage area for nonvolatile data storage of frequencies and keys, etc. This storage area is capable of in
excess of 100k write cycles.
2.4.4 RAM
A 128k x 8 static RAM is used for temporary storage of data by the H8 controller. This RAM is powered by a
continuous supply that maintains its contents as long as a power source is present. Additionally the RAM has a
backup capacitor to retain its contents over power interruptions.
2.4.5 TCXO
This oscillator serves as the reference for all logic and power supply clocks within the control logic and keypad. It
provides the data rate clocks for radio operation, and is the source of the ADC/DAC/CODEC conversion clocks. The
TCXO is at 12.288 MHz, with a temperature tolerance of +2.5 ppm. Additional calibration is performed to provide
a typical temperature tolerance of ± 1.0 ppm, a trimmer to set the initial frequency is provided. A Schmitt trigger
buffer squares up the TCXO sine wave output before being output to H8 and DSP.