3-6
G U A R D I A N V H F 1 1 0 W M O B I L E
3.2.6.1
Audio and Power Supply Unit (PSU) Driver
A serial interface driver controls the output bits of a serial-to-parallel output shift register in the FPGA. Clock and
data source for this shift register is the same serial port used for the user interface serial bus, but data is directed to
the shift register using high-order H8 address lines.
3.2.6.2
Transceiver Serial Bus Driver
A serial interface driver controls the transceiver shift register, DAC, and synthesizer. It uses a common clock and
data line, and three separate strobe lines for each device.
3.2.6.3 DSP
Host
Driver
The H8 software includes a DSP host driver for controlling the DSP mode of operation, and initial start-up code
download.
3.2.6.4 IIC
Bus
Driver
The H8 software includes a driver that allows the controller software to read and write to the transceiver EEPROM
using IIC protocols. The two lines are general-purpose I/O lines controlled on a bit-by-bit basis by the software.
3.3 Digital Signal Processing
The DSP software implements all baseband signals processing in the radio. It processes signals between the user
audio and data interface, and the transceiver modulation and intermediate frequency (IF) interfaces. The signal
processing provides compatible analog FM modes, common air interface (CAI) compatible modes, and 12 kbps
secure CVSD modes.
3.3.1 DSP Transmit Chain
Signal processing while the radio is transmitting depends on the radio's operational mode. The possible modes are
clear analog voice FM, CVSD DES voice, Project 25 clear digital voice, and Project 25 DES digital voice. The
Transmit DSP Chain block diagram is shown in Figure 3-2. The major signal processing functions of the DSP
transmit chain are described in the following paragraphs.
3.3.1.1 Audio
Coder/Decoder (CODEC)
The Guardian uses a Texas Instruments® TLV320-AC36 audio CODEC. Data is transferred to and from the
CODEC using the DSP enhanced synchronous serial interface (ESSI) 0 port. The data word is 16 bits long. The
first thirteen bits are the two’s compliment audio sample, and the last 3 are the volume control word in the receive
direction (DIN), and zero padded in the transmit direction (DOUT). The DSP currently sets volume control bits for
no attenuation. Scaling the signal prior to sending it to the CODEC controls the volume. The sample rate from the
CODEC is 8 ksps.
3.3.1.2
Audio Processing Board
The Audio Processing board receives audio input from the audio CODEC, applies filtering and automatic gain
control (AGC), and transmits it to the mode-specific formatting module. The audio filter has a passband from
300 Hz to 3 kHz. This board also transmits DTMF tones to the audio CODEC. DTMF over-dial is supported to
allow redirection through the phone network via a base station. Data is transferred to and from the CODEC under
interrupt service routine (ISR) control.
3.3.1.3
Project 25 Voice Module
The Project 25 Voice module performs framing and conversion tasks. The framing function uses its own task table
to build a CAI time-division multiple access (TDMA) frame. This includes compression of the voice signal using
the IMBE VOCODER, forward error correction, and encryption. The physical layer task converts a 4.8 ksps dibit
data stream into a 48 ksps real sampled waveform, which is then fed to the Modulation module. The physical layer
scales each dibit symbol so that the proper frequency deviation is attained. It applies raised cosine filtering for
control of inter-symbol interference.
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