GOWIN GW1N Series User Manual Download Page 27

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3FPGA Circuits

3.9LVDS

DBUG353-1.06E

20(25)

Signal Name

Pin No.

40P Socket Pin No.

BANK

Description

I/O

H_B_IO33

General I/O

VCCO1

H_B_IO34

General I/O

VCCO1

H_B_IO35

General I/O

VCCO1

H_B_IO36

General I/O

VCCO1

VCC5

GND

Note

！

The VCCO1 of GW1N-4 can only be supplied with 3.3V or 2.5V, optional;

3.9

LVDS

3.9.1

Overview

Two 2 mm DC3-20P sockets are reserved on the development board

for LVDS testing and data communication.

3.9.2

LVDS Circuit

Figure 3-8 LVDS Circuit

F_LVDS_A1_P

F_LVDS_A2_P

F_LVDS_A3_P

F_LVDS_A4_P

F_LVDS_A5_P

F_LVDS_A1_N

F_LVDS_A2_N

F_LVDS_A3_N

F_LVDS_A4_N

F_LVDS_A5_N

J10

F_LVDS_B1_P

F_LVDS_B2_P

F_LVDS_B3_P

F_LVDS_B4_P

F_LVDS_B5_P

F_LVDS_B1_N

F_LVDS_B2_N

F_LVDS_B3_N

F_LVDS_B4_N

F_LVDS_B5_N

J11

3.9.3

Pins Distribution

Table 3-9 J10 FPGA Pin Distribution

Signal Name

Pin No.

40P Socket Pin No.

BANK

Description

I/O

F_LVDS_A1_P

Differential Channel 1+

2.5V

F_LVDS_A1_N

Differential Channel 1-

2.5V

GND

Summary of Contents for GW1N Series

Page 1: ...DK_START_GW1N LV4LQ144C6I5_V1 1 User Guide DBUG353 1 06E 01 06 2021 ...

Page 2: ... identified as trademarks or service marks are the property of their respective holders as described at www gowinsemi com GOWINSEMI assumes no liability and provides no warranty either expressed or implied and is not responsible for any damage incurred to your hardware software data or property resulting from usage of the materials or intellectual property except as outlined in the GOWINSEMI Terms...

Page 3: ...d 11 20 2017 1 02E Notes for GW1N 1 GW1N 4 4B and GW1N 9 updated 8 29 2018 1 03E DK_START_GW1N LV4LQ144C6I5_V1 1 circuit diagrams updated 12 20 2018 1 04E Power pins distribution modified Further details about Bank power supply requirements added 04 23 2019 1 05E Supported Products updated 01 06 2021 1 06E The name of the board updated The description of chapter 3 1 FPGA Module updated ...

Page 4: ...upport and Feedback 2 2 Development Board Description 3 2 1 Overview 3 2 2 A Development Board Kit 4 2 3 PCB Components 5 2 4 System Architecture 6 2 5 Features 6 2 6 Development Board Specification 7 3 FPGA Circuits 9 3 1 FPGA Module 9 3 2 Download Interface 9 3 2 1 Overview 9 3 2 2 USB Download Circuit 10 3 2 3 Downloading the Data Stream 10 3 2 4 Pins Distribution 11 3 3 Power Supply 11 3 3 1 O...

Page 5: ... 14 3 5 2 LED Circuit 14 3 5 3 Pins Distribution 14 3 6 Switches 15 3 6 1 Overview 15 3 6 2 Key Switch Circuit 15 3 6 3 Pins Distribution 15 3 7 Key 16 3 7 1 Overview 16 3 7 2 Key Circuit 16 3 7 3 Pins Distribution 16 3 8 GPIO 16 3 8 1 Overview 16 3 8 2 GPIO Circuit 17 3 8 3 Pins Distribution 17 3 9 LVDS 20 3 9 1 Overview 20 3 9 2 LVDS Circuit 20 3 9 3 Pins Distribution 20 4 Notes 23 5 Gowin Softw...

Page 6: ...ts 5 Figure 2 4 System Architecture 6 Figure 3 3 Connection Diagram for FPGA USB Downloading and Configuration 10 Figure 3 4 Power System Distribution 12 Figure 3 5 Clock Reset 13 Figure 3 6 LED Circuit 14 Figure 3 7 Key Switch Circuit 15 Figure 3 8 Key Circuit Diagram 16 Figure 3 9 GPIO Circuit 17 Figure 3 10 LVDS Circuit 20 Figure 4 1 Download Speed 23 ...

Page 7: ...ion 11 Table 3 4 GW1N 4 FPGA Power Pins Distribution 12 Table 3 5 FPGA Clock and Reset Pins Distribution 14 Table 3 6 LED Pins Distribution 14 Table 3 7 Clock Circuit Pins Distribution 15 Table 3 8 Key Pins Distribution 16 Table 3 9 J8 FPGA Pin Distribution 17 Table 3 10 J9 FPGA Pin Distribution 19 Table 3 11 J10 FPGA Pin Distribution 20 Table 3 12 J10 FPGA Pin Distribution 21 ...

Page 8: ...sing the development board Introduction to the use of the FPGA development software 1 2 Supported Products The information in the guide applies to GW1N series of FPGA products GW1N 4 1 3 Related Documents The latest user guides are available on the GOWINSEMI Website You can find the related documents at www gowinsemi com DS100 GW1N series of FPGA Products Data Sheet UG103 GW1N series of FPGA Produ...

Page 9: ...O Low Dropout Regulator GPIO Gowin Programmable I O LUT4 Four input Look up Tables SSRAM Shadow Static Random Access Memory BSRAM Block Static Random Access Memory PLL Phase locked Loop DLL Delay locked Loop DSP Digital Signal Processing LQ144 LQFP144 1 5 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support If you have any questions comments or suggestio...

Page 10: ...ding low power consumption instant start up high security low cost and flexible extensions all of which can effectively reduce the learning cost and help users quickly design and develop programmable logic devices The development board includes two GPIO ports and two LVDS ports These provide users with a hardware evaluation and testing platform that offers a high integration level and stable perfo...

Page 11: ...er boards Motion control systems can also be designed by combining the development board with AD DA industrial daughter boards while human computer interface and image processing can be realized by combining the development board with the display daughter board 2 2 A Development Board Kit A development board suite includes the following items DK_START_GW1N LV4LQ144C6I5_V1 1 V1 1 5V power adapter 2...

Page 12: ...2Development Board Description 2 3PCB Components DBUG353 1 06E 5 25 2 3 PCB Components Figure 2 3 PCB Components ...

Page 13: ... X4 X4 X4 X4 Key 20PIN LVDS Header 20PIN LVDS Header X1 2 5 Features The structure and features of the development board are as follows 1 FPGA LQFP144 package Embedded flash data not easily lost if power down Abundant LUT4 resources Multiple modes and capacities of BSRAM Supports LV 2 FPGA Configuration Mode JTAG AUTO BOOT MSPI 3 Clock Resources 50MHz clock crystal oscillator SMA external clock in...

Page 14: ...d 3 Power Supply Provide DC 5V input 3 3 V 2 5V and 1 2 V output via LDO circuit Input power 5V Provide power for FPGA download circuit and other circuits via 5V 3 3 V circuit Provide power for FPGA via 5V 2 5V circuit Provide power to FPGA core via 3 3 V 1 2 V circuit 4 Slide Switches Available for testing 4 5 Key Switches Available for testing 4 6 Reset button Reset for FPGA 1 7 LED Test indicat...

Page 15: ...tection USB interface ESD protection Power interface Inverse current and over current protection USB interface ESD protection 15kV non contact discharge 8kV contact discharge Schottky diode is connected between positive and negative anodes of power outlet 2A self recovery fuses are connected at power inlet 13 Voltage Input range 2 7V 5 5V 14 Humidity 95 15 Temperatur e Operating range 20 70 ...

Page 16: ...W1N series of FPGA Products Package and Pinout 3 2 Download Interface 3 2 1 Overview The development board provides an USB download interface The data stream file can be downloaded to the internal SRAM internal flash or external flash as needed Note When downloaded to SRAM the data stream file will be lost if the device is power down and it will need to be downloaded again after power on If downlo...

Page 17: ...e mode is independent of the values of MODE0 and MODE1 Internal Flash Power on and download After downloading the data stream file successfully power down to reset and load the bit file from the internal Flash and when the Done indicator lights up to denote that the download has been successful Note Before downloading the bit file and the internal starting FLASH MODE0 and MODE1 need to set to 00 E...

Page 18: ...LASH signals configuration VCCO1 MSPI_DI_A 95 1 FLASH signals configuration VCCO1 MSPI_DO 96 1 FLASH signals configuration VCCO1 Note The VCCO1 of GW1N 4 can only be supplied with 3 3V or 2 5V optional 3 3 Power Supply 3 3 1 Overview The DC5V input power interface has overcurrent and inverse current protection The overcurrent limit is 2A The TI LDO power supply chip is used to step down voltage fr...

Page 19: ... 1 2V 2A VCCO1 FPGA VCCO2 FPGA VCCO3 FPGA VCCX FPGA VCC FPGA LED 4 3 3 3 Power Pins Distribution Table 3 2 GW1N 4 FPGA Power Pins Distribution Signal Name FPGA Pins No BANK Description I O Voltage VCCO0 109 127 0 I O Bank Voltage 3 3V 2 5V 1 2V VCCO1 77 91 1 I O Bank Voltage 3 3V 2 5V VCCO2 37 55 2 I O Bank Voltage 3 3V 2 5V 1 2V VCCO3 5 19 3 I O Bank Voltage 3 3V 2 5V 1 2V VCCX 31 103 Auxiliary V...

Page 20: ...LL input pin This can be employed as the input clock for the PLL in FPGA and the output clock as needed via multiplication and division of the PLL frequency To facilitate testing a SMA socket is reserved on the development board as the clock input interface The clock signal is connected to the FPGA global clock pin 3 4 2 Clock Reset Figure 3 3 Clock Reset 6 56 92 KEY5 50MHz ADM811 JC3 660 046 3 3V...

Page 21: ...optional 3 5 LED 3 5 1 Overview Four green LEDs are incorporated into the development board and are used to display the required status In addition two LEDs are reserved to signify power supply and FPGA loading status Users can test the LEDs in the following ways If the output signal of related pins is logic low LED is on If logic is high LED is off 3 5 2 LED Circuit Figure 3 4 LED Circuit D3 47 D...

Page 22: ...re used to control input during testing 3 6 2 Key Switch Circuit Figure 3 5 Key Switch Circuit SW4 68 SW5 69 SW6 79 SW7 80 VCCO2 U6 F_SW1 F_SW2 F_SW3 F_SW4 3 6 3 Pins Distribution Table 3 5 Clock Circuit Pins Distribution Signal Name Pin No BANK Description I O F_SW1 68 2 Slide Switch1 3 3V 2 5V 1 2V F_SW2 69 2 Slide Switch2 3 3V 2 5V 1 2V F_SW3 79 1 Slide Switch3 3 3V 2 5V F_SW4 80 1 Slide Switch...

Page 23: ... 3 7 2 Key Circuit Figure 3 6 Key Circuit Diagram 3 7 3 Pins Distribution Table 3 6 Key Pins Distribution Signal Name Pin No BANK Description I O F_KEY1 43 2 KEY1 3 3V 2 5V 1 2V F_KEY2 44 2 KEY2 3 3V 2 5V 1 2V F_KEY3 45 2 KEY3 3 3V 2 5V 1 2V F_KEY4 46 2 KEY4 3 3V 2 5V 1 2V 3 8 GPIO 3 8 1 Overview Two 2 54mm DC3 40P sockets are reserved on the development board for user function extension and testi...

Page 24: ...2 14 16 18 20 21 23 25 27 29 22 24 26 28 30 31 33 35 37 39 32 34 36 38 40 H_B_IO1 VCC3P3 VCC5 H_B_IO3 H_B_IO5 H_B_IO7 H_B_IO9 H_B_IO11 H_B_IO13 H_B_IO15 H_B_IO17 H_B_IO19 H_B_IO21 H_B_IO23 H_B_IO25 H_B_IO27 H_B_IO29 H_B_IO31 H_B_IO33 H_B_IO35 H_B_IO2 H_B_IO4 H_B_IO6 H_B_IO8 H_B_IO10 H_B_IO12 H_B_IO14 H_B_IO16 H_B_IO18 H_B_IO20 H_B_IO22 H_B_IO24 H_B_IO26 H_B_IO28 H_B_IO30 H_B_IO32 H_B_IO34 H_B_IO36...

Page 25: ... H_A_IO17 9 19 3 General I O VCCO3 H_A_IO18 10 20 3 General I O VCCO3 H_A_IO19 11 21 3 General I O VCCO3 H_A_IO20 12 22 3 General I O VCCO3 H_A_IO21 15 23 3 General I O VCCO3 H_A_IO22 23 24 3 General I O VCCO3 H_A_IO23 24 25 3 General I O VCCO3 H_A_IO24 25 26 3 General I O VCCO3 H_A_IO25 26 27 3 General I O VCCO3 H_A_IO26 27 28 3 General I O VCCO3 H_A_IO27 28 29 3 General I O VCCO3 H_A_IO28 29 30 ...

Page 26: ...O12 117 14 0 General I O VCCO0 H_B_IO13 116 15 0 General I O VCCO0 H_B_IO14 115 16 0 General I O VCCO0 H_B_IO15 114 17 0 General I O VCCO0 H_B_IO16 113 18 0 General I O VCCO0 H_B_IO17 112 19 0 General I O VCCO0 H_B_IO18 111 20 0 General I O VCCO0 H_B_IO19 110 21 0 General I O VCCO0 H_B_IO20 106 22 1 General I O VCCO1 H_B_IO21 104 23 1 General I O VCCO1 H_B_IO22 102 24 1 General I O VCCO1 H_B_IO23 ...

Page 27: ...nd data communication 3 9 2 LVDS Circuit Figure 3 8 LVDS Circuit 1 3 5 7 9 2 4 6 8 10 11 13 15 17 19 12 14 16 18 20 F_LVDS_A1_P F_LVDS_A2_P F_LVDS_A3_P F_LVDS_A4_P F_LVDS_A5_P F_LVDS_A1_N F_LVDS_A2_N F_LVDS_A3_N F_LVDS_A4_N F_LVDS_A5_N J10 1 3 5 7 9 2 4 6 8 10 11 13 15 17 19 12 14 16 18 20 F_LVDS_B1_P F_LVDS_B2_P F_LVDS_B3_P F_LVDS_B4_P F_LVDS_B5_P F_LVDS_B1_N F_LVDS_B2_N F_LVDS_B3_N F_LVDS_B4_N F...

Page 28: ...tial Channel 5 2 5V F_LVDS_A5_N 63 18 2 Differential Channel 5 2 5V GND 19 GND 20 Table 3 10 J10 FPGA Pin Distribution Signal Name Pin No 40P Socket Pin No BANK Description I O F_LVDS_B1_P 64 1 2 Differential Channel 1 2 5V F_LVDS_B1_N 65 2 2 Differential Channel 1 2 5V GND 3 GND 4 F_LVDS_B2_P 66 5 2 Differential Channel 2 2 5V F_LVDS_B2_N 67 6 2 Differential Channel 2 2 5V GND 7 GND 8 F_LVDS_B3_P...

Page 29: ...3FPGA Circuits 3 9LVDS DBUG353 1 06E 22 25 Signal Name Pin No 40P Socket Pin No BANK Description I O F_LVDS_B5_N 78 18 2 Differential Channel 5 2 5V GND 19 GND 20 ...

Page 30: ...into the LVDS Port As the output port the corresponding terminating resistors are removed in the LVDS interface 4 Input DC5V power supply via USB download interface or power socket Input via the power socket if the SW1 switch is pressed input via the USB download interface if the SW1 switch pops up 5 The value of download speed configured in Project should be no less than 5MHz as shown in below Fi...

Page 31: ...4Notes 3 9LVDS DBUG353 1 06E 24 25 VCCO0 VCCO2 and VCCO3 can be set as 3 3V 2 5V and 1 2V using jumpers The pins of J10 and J11 LVDS support TLVDS output input test ...

Page 32: ...5 Gowin Software DBUG353 1 06E 25 25 5 Gowin Software For the details you can see SUG100 Gowin Software User Guide ...

Page 33: ......

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