3FPGA Circuits
3.4Clock, Reset
DBUG353-1.06E
13(25)
Note!
The VCCO1 of GW1N-4 can only be supplied with 3.3V or 2.5V, optional.
3.4
Clock, Reset
3.4.1
Overview
A 50MHz crystal oscillator is provided in the development board that
connects to the PLL input pin. This can be employed as the input clock for
the PLL in FPGA, and the output clock as needed via multiplication and
division of the PLL frequency.
To facilitate testing, a SMA socket is reserved on the development
board as the clock input interface. The clock signal is connected to the
FPGA global clock pin.
3.4.2
Clock, Reset
Figure 3-3 Clock, Reset
6
56
92
KEY5
50MHz
ADM811
JC3.660.046
3.3V
FPGA_RST_N
F_CLK_SMA
FPGA_CLK
U6
U7
J7
X2
