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Desktop Transceiver SFX-TAP4_2/C, V0.1, Technical Description
5.2.4 Inline Resistor
The Inline resistors are applied to all TAP outputs (TCK, TMS, TDO and /TRST) with the same
value. Following values can be selected (see figure 13):
•
Tristate --> the driver stays in tristate mode during test execution
•
33
Ω
•
22
Ω
(default)
•
15
Ω
These resistors form with possibly existing resistors on the UUT voltage divider
and can affect the operation. Those cases can be compensated by increasing the
output voltage.
5.2.5 Pull Down Resistor
The Pull Down resistor affects the TDI input only. The following values can be set:
•
Open --> no Pull down
•
1k
Ω
(default)
•
330
Ω
•
220
Ω
5.2.6 Power Relays
The Power Relays is activated by the Checkbox Power relay (see figure 14). With activation, all
power relays are controlled to the on-state with execution start. The following delay parameter
ensures stable relay contact position and power-up of the UUT before the test itself starts. Since
the delay time can be defined per TAP individually, the largest time determines the starting time
of the test when using more than one TAP. After finishing the test, the relays return to the off
state. For further information about Power Relays refer to chapter 4.6.
5.2.7 ADYCS II™
ADYCS™ (Active Delay Compensation) allows data transmission along the TAP cable
independent from the distance to UUT. The UUT and cable design determine the maximum
TCK frequency. The Feature ADYCS™ II is supported by all types of SCANFLEX controllers.
For correct setting, notify the time delay of the UUT. Enter the value in
Delay
below
EH
, see
figure 13.
Delay
corresponds to t
delay
in figure 14. The inaccuracy / tolerance of the time delay
(
∆
t) is entered in the text field
TCK TDO delay delta
. That value is global for all TAPs.
For better understanding see the timing diagram in figure 14.
Summary of Contents for SFX-TAP2/C
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