Gigabyte AMD EPYC 7002 Series, User Manual

Page: 92 / 141

BIOS Setup - 92 -
Parameter Description
NBIO RAS Common Options
Press [Enter] for more options.
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NBIO RAS Global Control
– Options available: Manual/Auto. Default option is Auto .
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NBIO RAS Control
– 0 = Disabled, 1 = MCA, 2 = Legacy.
– Options available: Disabled/MCA/Legacy. Default option is MCA .
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Egress Poison Severity High
– Enter a value. Each bit set to 1 enables high severity on the
associated IOHC egress port. A bit of 0 indicates low severity.
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Egress Poison Severity Low
– Enter a value. Each bit set to 1 enables high severity on the
associated IOHC egress port. A bit of 0 indicates low severity.
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NBIO SyncFlood Generation
– This value may be used to mask SyncFlood caused by NBIO RAS
options. When set to TRUE SyncFlood from NBIO is masked.
When set to FALSE NBIO is capable of generating SyncFlood.
– Options available: Enabled/Disabled/Auto. Default option is Auto .
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NBIO SyncFlood Reporting
– This value may be used to enable SyncFlood reporting to APML.
When set to TRUE SyncFlood will be reported to APML. When set
to FALSE that reporting will be disabled.
– Options available: Enabled/Disabled. Default option is Disabled .
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Egress Poison Mask High
– Enter a value. These set the enable mask for masking of errors
logged in EGRESS_POISON_STATUS. For each bit set to 1,
errors are masked. For each bit set to 0, errors trigger response
actions.
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Egress Poison Mask Low
– Enter a value. These set the enable mask for masking of errors
logged in EGRESS_POISON_STATUS. For each bit set to 1,
errors are masked. For each bit set to 0, errors trigger response
actions.
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Uncorrected Converted to Poison Enable Mask High
– Enter a value. These set the enable mask for masking of
uncorrectable parity errors on internal arrays. For each bit set to
1, a system fatal error event is triggered for UCP errors on arrays
associated with that egress port. For each bit set to 0, errors are
masked.
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Uncorrected Converted to Poison Enable Mask Low
– Enter a value. These set the enable mask for masking of
uncorrectable parity errors on internal arrays. For each bit set to
1, a system fatal error event is triggered for UCP errors on arrays
associated with that egress port. For each bit set to 0, errors are
masked.