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GS1572 

 

A Guide to Designing with the GS1572 (EB1572)

Reference Design

1 of 18

Proprietary & Confidential

GS1572 A Guide to Designing with the GS1572 
(EB1572)
Reference Design
46282 - 1

November 2009

www.gennum.com

Summary of Contents for EB1572

Page 1: ...572 A Guide to Designing with the GS1572 EB1572 Reference Design 1 of 18 Proprietary Confidential GS1572 A Guide to Designing with the GS1572 EB1572 Reference Design 46282 1 November 2009 www gennum c...

Page 2: ...4 2 1 1 Isolation Methods 4 2 2 Serial Digital Outputs 5 2 3 VCO Power 6 3 Evaluation Board User s Guide 7 3 1 Power 7 3 2 Inputs 7 3 3 Outputs 8 3 4 Modes of Operation 9 3 5 External Control Interfac...

Page 3: ...ng with the GS1572 2 A user s guide to the GS1572 evaluation board including information on how to use the board and detailed schematic and board layout information An example of a board design includ...

Page 4: ...B6 and C6 C7 C8 2 1 8V DIGITAL supplying power to the following pins on the GS1572 CORE_VDD CORE_GND pins A5 E1 G10 K8 and B5 C5 D5 E2 E5 E6 E7 F4 F5 F6 F7 G9 J8 3 3 3V ANALOG supplying power to the...

Page 5: ...ORL matching network The cutouts under the pull up resistors attached to the output pins are necessary and are used to reduce the capacitance and provide better matching to the 75 transmission line A...

Page 6: ...3 3V ANALOG connection to CP_VDD pin A10 and CP_GND pin B10 of the GS1572 Figure 2 3 shows the connection to the VCO supply and Figure 2 4 shows the recommended PCB layout and component placement Note...

Page 7: ...allows the board to easily be reset 3 1 Power The GS1572 evaluation board requires a 5V power supply and a ground connection Power regulation to 3 3V and 1 8V is done on board see Figure 3 1 Power su...

Page 8: ...ats TheLOCKLEDontheGS1572indicatesthestatusoftheLOCKEDpinontheGS1572 The LED will be on whenever the GS1572 PLL is locked to PCLK Figure 3 2 Parallel Input Bus 3 3 Outputs The GS1572 contains an integ...

Page 9: ...encoding Table 3 1 gives a description of the GS1572 jumper settings in each mode NOTE The jumpers correspond directly to pins on the GS1572 Please see the GS1572 Data Sheet for a more detailed expla...

Page 10: ...nternal registers the GSPI or JTAG test operation please see the GS1572 Data Sheet Figure 3 5 JTAG HOST Interface Block SMPTE and DVB_ASI jumper leads Install two jumpers HORIZONTALLY in SMPTE mode In...

Page 11: ...On DVB_ASI SD HDb SMPTE_BYPASSb RESET_TRSTb SCLK_TCK SDIN_TDI CSb_TMS SDOUT_TDO DATA_IN 19 0 3 3V 1 8V R12 0R GND GND GND_A GND GND_A Input Power DATA_IN17 DATA_IN16 DATA_IN12 DATA_IN14 DATA_IN13 DATA...

Page 12: ...SWITCHED PCLK SCLK_TCK R58 10K SDIN_TDI DATA_IN15 R65 75R L2 5N6 R60 75R L1 5n6 1 2 C75 4u7 1 8V 1 2 C72 4u7 R66 22k SDO SDO R and L form the Output Return Loss compensation Network SUBJECT TO CHANGE...

Page 13: ...e Design 46282 1 November 2009 13 of 18 Proprietary Confidential 5 Board Layout The following illustrations show the top ground power and bottom layers of the GS1572 evaluation board Figure 5 1 Layer...

Page 14: ...2 A Guide to Designing with the GS1572 EB1572 Reference Design 46282 1 November 2009 14 of 18 Proprietary Confidential Figure 5 3 Layer 3 Power Plane Negative Image Figure 5 4 Layer 4 Bottom Routing L...

Page 15: ...F 3 C45 C46 C86 1 F 4 C55 C57 C59 C61 100nF 3 C56 C60 C71 10 F 1 C62 0 25pF 1 C63 4 7 F 1 C66 10nF 1 C67 4 7 F 1 C68 0 25pF 1 C69 33 F 3 C70 C87 C89 10nF 2 C72 C75 4 7 F 1 C73 10nF 3 C76 C77 C78 NP 4...

Page 16: ...2 2k 4 R26 R54 R55 R70 0 1 R56 3 3 1 R57 7 1 R58 10k 4 R60 R62 R64 R65 75 1 R61 750 1 R66 22k 3 R67 R68 R69 NP 1 R71 1k 1 S1 B3S_1002 5 TP1 TP2 TP3 TP4 TP5 HEADER2MM_1_1X1 TP_0 2 TP6 TP7 Test Points 1...

Page 17: ...unreliable when biased at more than a volt The capacitance drops to about 1 4 of its value Ceramic Various For values below 1uF X7R or NPO depending on what is available for that value Inductors 0402...

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