PC104P-SIO4BX User Manual, Revision: 0
General Standards Corporation
8302A Whitesburg Drive Huntsville, AL 35802, Phone: (256) 880-8787
4.1.2 Local Configuration Registers
The Local Configuration registers give information on the Local side implementation. These include the required
memory size. The SIO4 memory size is initialized to 4k Bytes. All other Local Registers initialize to the default
values described in the PCI9080 Manual.
4.1.3 Runtime Registers
The Runtime registers consist of mailbox registers, doorbell registers, and a general-purpose control register. The
mailbox and doorbell registers are not used and serve no purpose on the SIO4BX. All other Runtime Registers
initialize to the default values described in the PCI9080 Manual.
4.1.4 DMA Registers
The Local DMA registers are used to setup the DMA transfers to and from the on-board FIFOs. DMA is
supported only to the four FIFO locations. The SIO4BX supports both Demand (DREQ# controlled) and Non-
Demand mode DMA. Both Channel 0 and Channel 1 DMA are supported.
4.1.4.1 DMA Channel Mode Register: (PCI 0x80 / 0x94)
The DMA Channel Mode register must be setup to match the hardware implementation
Bit
Description
Value
Notes
D1:0
Local Bus Width
11 = 32 bit
00 = 8 bit
Although the serial FIFOs only contain 8 bits
of data, the register access is still a 32bit
access. It is possible to “pack” the data by
setting the Local Bus Width to 8, but this is
only guaranteed to work with Non-Demand
Mode DMA
D5:2
Internal Wait States
0000 = Unused
D6
Ready Input Enable
1 = Enabled
D7
Bterm# Input Enabled
0 = Unused
D8
Local Burst Enable
1 = Supported
Bursting allows fast back-to-back accesses to
the FIFOs to speed throughput
D9
Chaining Enable (Scatter
Gather DMA)
X
DMA source addr, destination addr, and byte
count are loaded from memory in PCI Space.
D10
Done Interrupt Enable
X
DMA Done Interrupt
D11
Local Addressing Mode
1 = No Increment
DMA to/from FIFOs only
D12
Demand Mode Enable
X
Demand Mode DMA is supported for FIFO
accesses on the SIO4BX.
(See Section 3.3)
D13
Write & Invalidate Mode
X
D14
DMA EOT Enable
0 = Unused
D15
DMA Stop Data Transfer
Enable
0 = BLAST
terminates DMA
D16
DMA Clear Count Mode
0 = Unused
D17
DMA Channel Interrupt
Select
X
D31:18
Reserved
0
