PC104P-SIO4BX User Manual, Revision: 0
General Standards Corporation
8302A Whitesburg Drive Huntsville, AL 35802, Phone: (256) 880-8787
2.2
Universal Serial Controller Registers
The internal registers of the Zilog Z16C30 Universal Serial Controller (USC) are memory mapped into Local
Address space. It is beyond the scope of this manual to provide comprehensive USC programming information.
For detailed programming information, please refer to the Zilog High Speed Communication Controller Product
Specifications Databook for the Z16C30 and the Zilog Z16C30USC User’s Manual. These manuals may be
obtained directly from Zilog (
www.zilog.com
), or copies of these manuals may be downloaded from the General
Standards website (
www.generalstandards.com
).
Some specific setup information may be needed for a driver to interface to the USC. Typically, the driver will
handle the hardware specific characteristics and the end user will only need to be concerned with the driver interface
- the following hardware setup information may be safely ignored. If you aren’t sure if you need this information,
you probably don’t.
2.2.1 USC Reset
The four serial channels are implemented in two Z16C30 Universal Serial Controllers – Channels 1 and 2 share one
USC, and Channels 3 and 4 share the other. This implementation is important to realize since resetting a Z16C30
chip will have an effect on two serial channels. Since the USC chips are typically reset upon initialization, this
means a “Reset USC” for Channel 1 will also “Reset USC” for Channel 2. In addition to making the second reset
redundant and unnecessary, a Reset USC on one channel may inadvertently adversely affect normal operation on the
second channel. Therefore, care must be exercised when resetting a USC (USC Reset bit in the Board Control
Register), especially in multithreaded environments.
Since the USC Reset physically resets the USC, the first access to the USC following the reset must reinitialize the
BCR in the USC. To complete the Reset process, the user should write data 0x00 to USC base address offset 0x100
or 0x300 to correctly initialize the BCR. Following this initial byte write, the USC may be accessed normally.
Due to the ability for a USC Reset to affect two channels, it is recommended that a single USC Channel be Reset via
the RTReset bit of the USC Channel Command/Address Register (CACR).
2.2.2 8-Bit USC Register Access
As the USC has a configurable bus interface, the USC must be set to match the 8-bit non-multiplex interface
implementation of the SIO4BX. This setup information must be programmed into the USC Bus Configuration
Register (BCR) upon initial power up and following every hardware reset of the USC. The BCR is accessible only
following a USC hardware reset – the first write to the USC following a USC Reset programs the BCR. Even
though the Zilog manual states the BCR has no specific address, the driver must use the channel USC base address –
0x100 for Ch 1 & Ch 2, 0x300 for Ch 3 & Ch 4 – as the BCR address. Failure to do so may result in improper setup.
Since the user interface to the USC is an 8 bit interface, the software only needs to set the lower byte to 0x00
(hardware implementation will program the upper byte of the BCR).
2.2.3 USC Data Transfer
Although the Z16C30 USC contains 32 byte internal FIFOs for data transfer, these are typically not used on the
SIO4BX. Since the SIO4BX has much deeper external FIFOs (or internal FPGA FIFOs), the internal USC FIFOs
are setup to immediately transfer data to/from the external FIFOs. Immediate transfer of received data to the
external FIFOs eliminates the possibility of data becoming “stuck” in the USC internal receive FIFOs, while
bypassing the USC internal transmit FIFOs ensures better control of the transmit data.
In order to automatically transfer data to and from the external FIFOs, the USC should use DMA to request a data
transfer whenever one byte is available in the USC internal FIFOs. This “DMA” should not be confused with the
DMA of data from the SIO4BX external FIFOs to the PCI interface. To accomplish the USC-to-External FIFO
