PC104P-SIO4BX User Manual, Revision: 0
General Standards Corporation
8302A Whitesburg Drive Huntsville, AL 35802, Phone: (256) 880-8787
2.1.10 Interrupt Registers
There are 32 on-board interrupt sources (in addition to USC interrupts and PLX interrupts) which may be
individually enabled. Four interrupt registers control the on-board interrupts – Interrupt Control, Interrupt Status,
Interrupt Edge/Level, and Interrupt Hi/Lo. The 32 Interrupt sources are:
IRQ #
Source
Default Level
Alternate Level
IRQ0
Channel
1 Sync Detected
Rising Edge
NONE
IRQ1
Channel
1 Tx FIFO Almost Empty
Rising Edge
Falling Edge
IRQ2
Channel
1 Rx FIFO Almost Full
Rising Edge
Falling Edge
IRQ3
Channel
1 USC Interrupt
Level Hi
NONE
IRQ4
Channel
2 Sync Detected
Rising Edge
NONE
IRQ5
Channel
2 Tx FIFO Almost Empty
Rising Edge
Falling Edge
IRQ6
Channel
2 Rx FIFO Almost Full
Rising Edge
Falling Edge
IRQ7
Channel
2 USC Interrupt
Level Hi
NONE
IRQ8
Channel
3 Sync Detected
Rising Edge
NONE
IRQ9
Channel
3 Tx FIFO Almost Empty
Rising Edge
Falling Edge
IRQ10
Channel
3 Rx FIFO Almost Full
Rising Edge
Falling Edge
IRQ11
Channel
3 USC Interrupt
Level Hi
NONE
IRQ12
Channel
4 Sync Detected
Rising Edge
NONE
IRQ13
Channel
4 Tx FIFO Almost Empty
Rising Edge
Falling Edge
IRQ14
Channel
4 Rx FIFO Almost Full
Rising Edge
Falling Edge
IRQ15
Channel
4 USC Interrupt
Level Hi
NONE
IRQ16
Channel
1 Tx FIFO Empty
Rising Edge
Falling Edge
IRQ17
Channel
1 Tx FIFO Full
Rising Edge
Falling Edge
IRQ18
Channel
1 Rx FIFO Empty
Rising Edge
Falling Edge
IRQ19
Channel
1 Rx FIFO Full
Rising Edge
Falling Edge
IRQ20
Channel
2 Tx FIFO Empty
Rising Edge
Falling Edge
IRQ21
Channel
2 Tx FIFO Full
Rising Edge
Falling Edge
IRQ22
Channel
2 Rx FIFO Empty
Rising Edge
Falling Edge
IRQ23
Channel
2 Rx FIFO Full
Rising Edge
Falling Edge
IRQ24
Channel
3 Tx FIFO Empty
Rising Edge
Falling Edge
IRQ25
Channel
3 Tx FIFO Full
Rising Edge
Falling Edge
IRQ26
Channel
3 Rx FIFO Empty
Rising Edge
Falling Edge
IRQ27
Channel
3 Rx FIFO Full
Rising Edge
Falling Edge
IRQ28
Channel
4 Tx FIFO Empty
Rising Edge
Falling Edge
IRQ29
Channel
4 Tx FIFO Full
Rising Edge
Falling Edge
IRQ30
Channel
4 Rx FIFO Empty
Rising Edge
Falling Edge
IRQ31
Channel
4 Rx FIFO Full
Rising Edge
Falling Edge
For all interrupt registers, the IRQ source (IRQ31:IRQ0) will correspond to the respective data bit (D31:D0) of each
register. (D0 = IRQ0, D1 = IRQ1, etc.)
All FIFO interrupts are edge triggered active high. This means that an interrupt will be asserted (assuming it is
enabled) when a FIFO Flag transitions from FALSE to TRUE (rising edge triggered) or TRUE to FALSE (falling
edge). For example: If Tx FIFO Empty Interrupt is set for Rising Edge Triggered, the interrupt will occur when the
FIFO transitions from NOT EMPTY to EMPTY. Likewise, if Tx FIFO Empty Interrupt is set as Falling Edge
Triggered, the interrupt will occur when the FIFO transitions from EMPTY to NOT EMPTY.
All Interrupt Sources share a single interrupt request back to the PCI9080 PLX chip. Likewise, all USC interrupt
sources share a single interrupt request back to the interrupt controller and must be further qualified in the USC chip.
See Section
3.4 Interrupts
for further interrupt programming information.
