GE PCIE-5565PIORC* Hardware Reference Manual Download Page 41

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Programming 41

Table 3-31 Device Status Register Bit Definition

Device Status Register Bit Definition: Offset 0x08A

Bit(s)

Field

Description

R/W

15:6

Reserved

Transactions Pending When set to one, indicates that this function

has issued non-posted request packets
which have not yet been completed.

Aux Power Detected

Aux power not required. Hardwired to 0

Unsupported Request
Detected

1 = Error Detected
0 = Error Not Detected

RW1C

Fatal Error Detected

1 = Error Detected
0 = Error Not Detected

RW1C

Non-Fatal Error
Detected

1 = Error Detected
0 = Error Not Detected

RW1C

Correctable Error
Detected

1 = Error Detected
0 = Error Not Detected

RW1C

Table 3-32 Link Capabilities Register Bit Definition

Link Capabilities Register Bit Definition: Offset 0x08C

Bit(s)

Field

Description

R/W

31:24

Port Number

Hardwired to 0x01

23:18

Reserved

Hardwired to 000000

17:15

L1 Exit Latency

More than 64 micro seconds. Hardwired to 111 R

14:12

L0s Exit Latency

More than 4 micro seconds. Hardwired to 111 R

11:10

Active Stake Link PM
Support

L0s entry supported. Hardwired to 01

9:4

Maximum Link Width

X4. Hardwired to 000100

3:0

Maximum Speed

2.5 Gb/s Hardwired to 0001

Table 3-33 Link Control Register Bit Definition

Link Control Register Bit Definition: Offset 0x090

Bit(s)

Field

Description

R/W

15:8

Reserved

Hardwired to 000

Extended Sync

1 = 4096 FTS Ordered Sets during L0s state and 1024
TS1 Ordered Sets prior to entering the recovery state
0 = Do not use extended FTS and TS1 ordered sets

R/W

Common Clock
Configuration

1 = Uses common clock on both ends of link
0 = Uses separate clocks on each end of link

R/W

Retrain link

1 = Retrain Link
0 = Do not Retrain Link

R/W

Link Disable

1 = Disable Link
0 = Do not Disable Link

R/W

Read Completion
Boundary Control

0 = 64 Byte
1 = 128 Byte

R/W

Reserved

1:0

Active State PM
Control

00 = Disabled
01 = L0s Entry Enabled
10 = L1 Entry Enabled
11 = L0s and L1 Entry Enabled

R/W

Summary of Contents for PCIE-5565PIORC*

Page 1: ...75565 000 Rev A Hardware Reference PCIE 5565PIORC Ultrahigh Speed Fiber Optic Reflective Memory with Interrupts THE PCIE 5565PIORC IS DESIGNED TO MEET THE EUROPEAN UNION EU RESTRICTION OF HAZARD OUS SUBSTANCE ROHS DIRECTIVE 2002 95 EC CURRENT REVISION ...

Page 2: ...Document History Hardware Reference Manual Document Number 500 9367875565 000 Rev A September 23 2011 ...

Page 3: ...s 25 2 6 Network Interrupts 27 2 7 Redundant Transfer Mode of Operation 27 2 8 Rogue Packet Removal Operation 28 3 Programming 29 3 1 PCI Configuration Registers 30 3 2 Local Configuration Registers 43 3 3 RFM Control and Status Registers 49 3 3 1 Board Revision Register 50 3 3 2 Board ID Register 50 3 3 3 Board Revision Build Register 50 3 3 4 Node ID Register 50 3 3 5 Local Control and Status Re...

Page 4: ...3 4 Example of a Block DMA Operation for RFM 5565 61 3 5 Example of a Scatter Gather DMA Operation for RFM 5565 62 3 6 Example of a PCI PIO Sliding Window Operation for RFM 5565 64 3 7 Example of Network Interrupt Handling 66 3 7 1 Setup 66 3 7 2 Servicing Network Interrupts 66 Maintenance 67 Compliance Information 68 ...

Page 5: ...5PIORC 18 Figure 1 2 Installing the PCIE 5565PIORC 19 Figure 1 3 Low Profile and Standard Front Panels of the PCIE 5565PIORC 20 Figure 1 4 LC Type Fiber Optic Cable Connector 22 Figure 1 5 Example Six Node Ring Connectivity PCIE 5565PIORC 22 Figure 2 1 Interrupt Circuitry Block Diagram 26 Figure 3 1 Block Diagram of the Network Interrupt Reception Circuitry 60 ...

Page 6: ...le 3 14 PCI Base Address Register 3 for Access to Reflective Memory 36 Table 3 15 PCI Base Address Register 4 36 Table 3 16 PCI Base Address Register 5 36 Table 3 17 PCI Cardbus CIS Pointer Register 37 Table 3 18 PCI Subsystem Vendor ID Register 37 Table 3 19 PCI Subsystem ID Register 37 Table 3 20 PCI Expansion ROM Base Register 37 Table 3 21 PCI Capability Pointer Register 37 Table 3 22 PCI Inte...

Page 7: ...5 DMA Channel 0 Transfer Size Bytes Register 47 Table 3 46 DMA Channel 0 Descriptor Pointer Register 47 Table 3 47 DMA Channel 0 Command Status Register 47 Table 3 48 DMA Channel 0 PCI Dual Address Cycles Upper Address 48 Table 3 49 PCI PIO Direct Slave Local Address Range 48 Table 3 50 PCI PIO Direct Slave Local Base Address Remap 48 Table 3 51 Memory Map of the Local Control and Status Registers...

Page 8: ...d circuitry automatically performs the data transfer to all other nodes with little or no involvement of any host processor A block diagram of the PCIE 5565PIORC is shown in Figure 1 on page 9 Features Features include High speed easy to use fiber optic network 2 12 Gbaud serially x4 lane PCI Express 1 No host processor involvement in the operation of the network Selectable Redundant Mode of Opera...

Page 9: ...565 which is GE s board type Subsystem Vendor ID and Subsystem ID The PCI Configuration register reserved for the subsystem vendor ID has the value of 1556 which designates PLD Applications The PCI Configuration register reserved for the subsystem ID has the value of 0080 which is the PLD Applications PCI X core identification number Block Diagram Figure 1 Block Diagram of PCIE 5565PIORC 133 MHz M...

Page 10: ... Network PCI WorkStation with PCI 5565PIORC NODE 1 PCI 5565PIORC VMEbus Chassis with PMC 5565PIORC NODE 255 Up to 300m between nodes for multimode VMEbus Chassis with VMIVME 5565 NODE 0 VM IVME VM IVME 5565 5565 VMIVME 5565 PMC 5565PIORC Up to 10km between nodes for single mode ...

Page 11: ...Overview 11 References PCI Express Card Electromechanical Specification Revision 1 1 March 28 2005 PCI Express Base Specification Revision 1 1 March 28 2005 ...

Page 12: ...stallation describes unpacking and installation of the hardware Chapter 2 Theory of Operation describes the product s features and functionality Chapter 3 Programming describes PCI Configuration Registers and other registers for programming and installation Maintenance provides GE s contact information relative to the care and maintenance of the unit Compliance provides the applicable information ...

Page 13: ...onstitutes a definite safety hazard Keep Away from Live Circuits Operating personnel must not remove product covers Component replacement and internal adjustments must be made by qualified maintenance personnel Do not replace components with power cable connected Under certain conditions dangerous voltages may exist even with the power cable removed To avoid injuries always disconnect power and di...

Page 14: ...r death to personnel CAUTION CAUTION denotes a hazard It calls attention to an operating procedure practice or condition which if not correctly performed or adhered to could result in damage to or destruction of part or all of the system NOTE NOTE denotes important information It calls attention to a procedure practice or condition which is essential to highlight TIP Tip denotes a bit of expert in...

Page 15: ...nts damaged printed circuit board s heat damage and other visible contamination All claims arising from shipping damage should be filed with the carrier and a complete report sent to GE Technical Support 1 2 Handling Precaution Some of the components assembled on GE s products may be sensitive to electrostatic discharge and damage may occur on boards that are subjected to a high energy electrostat...

Page 16: ...r more nodes are configured with Rogue Master 0 enabled and that data will be lost NOTE No more than one node on the ring should be configured with Rogue Master 1 enabled Certain packets will be removed from the ring when two or more nodes are configured with Rogue Master 1 enabled and that data will be lost Prior to installing the RFM 5565 in the host system switch S1 must be configured for the a...

Page 17: ...10 16 OFF OFF OFF OFF ON OFF OFF OFF 8 8 OFF OFF OFF OFF OFF ON OFF OFF 4 4 OFF OFF OFF OFF OFF OFF ON OFF 2 2 OFF OFF OFF OFF OFF OFF OFF ON 1 1 OFF OFF OFF OFF OFF OFF OFF OFF 0 0 Factory Default S2 positions 1 through 8 OFF Table 1 2 Switch S1 Configuration RFM 5565 Position 1 OFF non redundant mode Position 1 ON redundant mode Position 2 OFF higher performance achievable Position 2 ON low netw...

Page 18: ...18 PCIE 5565PIORC Reflective Memory Board Figure 1 1 S1 and S2 Location PCIE 5565PIORC S1 S2 ...

Page 19: ...tion Also setup the board for the desired mode of operation See Section Switch S1 and S2 Configuration on page 16 2 Install the PCIE 5565PIORC firmly into the PCIe connector refer to Figure 1 2 on page 19 for installation of the PCIE 5565PIORC Install the screw to secure the PCIE 5565PIORC to the chassis 3 Close the system chassis apply power Figure 1 2 Installing the PCIE 5565PIORC This PCIE 5565...

Page 20: ...ransmitter The PCIE 5565PIORC uses LC type fiber optic cables Figure 1 3 Low Profile and Standard Front Panels of the PCIE 5565PIORC CAUTION When fiber optic cables are not connected the supplied dust caps need to be installed to keep dust and dirt out of the optics Do not power up the PCIE 5565PIORC without the fiber optic cables installed This could cause eye injuries STATUS RX RECEIVER CONNECTI...

Page 21: ...re 1 4 on page 22 is an illustration of the LC type multimode or singlemode fiber optic connector 1 6 1 Connector Specification Singlemode and Multimode Compatible with LC standard and JIS C 5973 compliant Ceramic ferrule Temperature range 20 C to 85 C Table 1 3 LED Descriptions LED Color Description Status Red User defined board status indicator SIG DET Yellow Indicates optical network connection...

Page 22: ... 21 23 0 49 1 25 Dimensions inches mm 4 5mm Node 1 Node 2 Node 6 Node 5 Node 3 STATUS SIG DET TX RX OWN DATA STATUS SIG DET TX RX PCIE5565 PIORC OWN DATA STATUS SIG DET TX RX OWN DATA STATUS SIG DET TX RX OWN DATA STATUS SIG DET TX RX OWN DATA STATUS SIG DET TX RX OWN DATA Node 4 PCIE5565 PIORC PCIE5565 PIORC PCIE5565 PIORC PCIE5565 PIORC PCIE5565 PIORC ...

Page 23: ... simple as a PIO target write or it can be due to a DMA cycle by the resident DMA engine While the write to the SDRAM is occurring circuitry on the RFM 5565 automatically writes the data and other pertinent information into the transmit FIFO From the transmit FIFO the transmit circuit retrieves the data and puts it into a variable length packet of 4 to 64 bytes that is transmitted over the fiber o...

Page 24: ...ase Address Register 0 has the starting address for register memory space accesses and Base Address Register 1 has the starting address for register IO space accesses Some Local Configuration Registers pertinent to the RFM 5565 s operation include the Interrupt Control and Status Register INTCSR and the DMA Control Registers RFM Control and Status Registers The RFM Control and Status Registers imp...

Page 25: ...upt Input LINTi The primary tier interrupt source 1 is used during DMA cycles and must be configured in the DMA registers The other primary tier interrupt source 2 is the Local Interrupt Input LINTi All secondary tier interrupts are funneled through the LINTi Second tier interrupts include several operational status bits faults and network interrupts The second tier interrupts are selected and mon...

Page 26: ...R Offset 10 RFM Fault Status Events LINT Second Tier Interrupts Interrupt Control and Status Register INTSCR Offset 68 Bits 11 and 15 DMA 0 Done Bits 18 and 21 Primary Tier Interrupts Host Interrupt INTA RFM Control and Status Registers per Base Address Register 2 Offset 14 RFM Control and Status Registers per Base Address Register 0 or 1 Local Interrupt Enable Register LIER ...

Page 27: ...stead it sets a bit in the LISR register which will result in a PCI interrupt if enabled The actual board reset should be performed by the host system in an orderly fashion However the user application could use this network interrupt for any purpose 2 7 Redundant Transfer Mode of Operation The RFM 5565 is capable of operating in a redundant transfer mode The board is configured for redundant mode...

Page 28: ...operation in an overly harsh environment Normally the solution is to isolate and replace the malfunctioning board and or improve the environment However some users prefer to tolerate sporadic rogue packets rather than halt the system for maintenance provided the rogue packets are removed from the network To provide tolerance for rogue packet faults the RFM 5565 contains circuitry that allows it to...

Page 29: ...e Reflective Memory The location of the register sets and the Reflective Memory varies from system to system and can even vary from slot to slot within a system For operations beyond the basic setup such as enabling or disabling interrupts or performing DMA cycles the user must know the specific bit assignments of the registers within the three register sets That information is provided in this ch...

Page 30: ... registers can be accessed as either Byte Word or Double word request Table 3 1 PCI Configuration Registers Address Hex 31 24 23 16 15 8 7 0 00 Device ID Vendor ID 04 Status Register Command Register 08 Class Code Revision ID 0C BIST Header Type Latency Timer Cache Line Size 10 Base Address Register 0 14 Base Address Register 1 18 Base Address Register 2 1C Base Address Register 3 20 Base Address ...

Page 31: ... No 0 4 Reserved N A N A 0 5 VGA Palette Snoop Not Supported Yes No 0 6 Parity Error Response Writing a zero 0 indicates parity error is ignored and the operation continues Writing a one 1 indicates parity checking is enabled Yes Yes 0 7 Wait Cycle Control Controls whether a device does address data stepping A zero 0 indicates the device never does stepping A one 1 indicates the device always does...

Page 32: ... No 0 11 Target Abort When set to one 1 indicates the Reflective Memory has signaled a Completer Abort Writing a one 1 clears this bit to zero 0 Yes Yes Clr 0 12 Received Target Abort When set to one 1 indicates the Reflective Memory has received a Completer Abort Writing a one 1 clears this bit to zero 0 Yes Yes Clr 0 13 Received Master Abort When set to one 1 indicates the Reflective Memory has ...

Page 33: ...NOTE This register can be altered by the system BIOS during the system boot process Table 3 8 PCI Latency Timer Register PCI Latency Timer Offset 0D Bit Description Read Write Value after PCI Reset 7 0 PCI Bus Latency Timer Not applicable to PCI Express Yes Yes 00 NOTE This register can be altered by the system BIOS during the system boot process Table 3 9 PCI Header Type Register PCI Header Type ...

Page 34: ...rol and Status Yes Yes 0 7 BIST Support Returns a one 1 if device supports BIST Returns a zero 0 if device is not BIST compatible Yes No 0 Table 3 11 PCI Base Address Register 0 for Access to Local Configuration Registers PCIBAR0 Offset 10 Bit Description Read Write Value after PCI Reset 0 Memory Space Indicator Writing zero 0 indicates the register maps into Memory Space Writing a one 1 indicates...

Page 35: ...ers Yes Yes 0 NOTE This register will be altered by the system BIOS during the system boot process I O Accesses not supported Table 3 13 PCI Base Address Register 2 for Access to RFM Control and Status Registers PCIBAR2 Offset 18 Bit Description Read Write Value after PCI Reset 0 Memory Space Indicator A zero 0 indicates the register maps into Memory Space A one 1 indicates the register maps into ...

Page 36: ...pace Yes No 0 2 1 Register Location Values 00 Locate anywhere in 32 bit Memory Address Space 01 Locate below 1 MByte Memory Address Space 10 Locate anywhere in 64 bit Memory Address Space 11 Reserved If I O Space Bit 1 is always 0 and Bit 2 is included in the base address Yes Mem No I O Bit 1 no Bit 2 yes 00 3 Prefetchable If Memory Space Writing a one 1 indicates there are no side effects on read...

Page 37: ...lication PCI X core Table 3 20 PCI Expansion ROM Base Register PCI Expansion ROM Base Offset 30 Bit Description Read Write Value after PCI Reset 0 Address Decode Enable A one 1 indicates a device accepts accesses to the Expansion ROM address A zero 0 indicates a device does not accept accesses to Expansion ROM space Should be set to zero 0 if there is no Expansion ROM Works in conjunction with ERO...

Page 38: ...nly INTA 1 INTA 2 INTB 3 INTC 4 INTD Yes No 1 Table 3 24 MSI Capability Structure Offset 31 16 15 8 7 0 0x050 Message Control 0x78 next cap ptr 0x05 capability ID 0x054 Message Address 0x058 Message Upper Address 0x05C Reserved Message Data Table 3 25 Message Control bit definition Message Control bit definition Offset 0x050 Bit s Field Description R W 15 9 Reserved R W 8 Mask Capability Not Suppo...

Page 39: ...ber Not Supported Hardwired to 0 R 8 Slot Implemented Not Supported Hardwired to 0 R 7 4 Device Port type Indicates the PCIe logical device type 0001 Legacy PCI Express Endpoint R 3 0 Capability Version 0x1 R Table 3 29 Device Capabilities Register Bit Definition Device Capabilities Register Bit Definition Offset 0x084 Bit s Field Description R W 31 28 Reserved R 27 26 Captured Slot Power Limit Sc...

Page 40: ...Byte 100 2K Byte 101 4K Byte R W 11 Enable No Snoop 1 Enable 0 Disable R W 10 Aux Power PM Enable Not Supported Hardwired to 0 R 9 Phantom Functions Enable Not Supported Hardwired to 0 R 8 Extended Tag Field Enable Not Supported Hardwired to 0 R 7 5 Max payload Size 000 128 Byte 001 256 Byte R W 4 Enable Relaxed Ordering 1 Enable 0 Disable R W 3 Unsupported Request Reporting Enable 1 Enable 0 Disa...

Page 41: ...00 R 17 15 L1 Exit Latency More than 64 micro seconds Hardwired to 111 R 14 12 L0s Exit Latency More than 4 micro seconds Hardwired to 111 R 11 10 Active Stake Link PM Support L0s entry supported Hardwired to 01 R 9 4 Maximum Link Width X4 Hardwired to 000100 R 3 0 Maximum Speed 2 5 Gb s Hardwired to 0001 R Table 3 33 Link Control Register Bit Definition Link Control Register Bit Definition Offset...

Page 42: ... 15 13 Reserved Hardwired to 0x00 R 12 Slot Clock Configuration 1 The card uses the reference clock provided on the connector R 11 Link Training 1 Link Training in process 0 Link Training done R 10 Link Training Error 1 Link Training Error Occurred 0 Link Successfully Trained R 9 4 Negotiated Link Width 000001 x1 000010 x2 000100 x4 R 3 0 Link Speed 0001 2 5 Gb s R ...

Page 43: ...s write zero 0 to all unused bits Table 3 35 Local Configuration and DMA Control Registers PCI Offset from Base Address Register Name Writable 00 07 Reserved N A 08 MARBR same as AC Y 0C Big Little Endian Descriptor Y 10 67 Reserved N A 68 INTCSR Y 70 Reserved N A 74 PCI H Rev Y 78 Reserved N A 80 DMA Channel 0 Mode Y 84 DMA Channel 0 PCI Address Y 88 DMA Channel 0 Local Address Y 8C DMA Channel 0...

Page 44: ...t Description Read Write Value after PCI Reset 4 0 Reserved Yes No 00 5 PCI PIO RFM Address Space Big Endian Mode Address Invariance Writing a one 1 specifies use of Big Endian data ordering for PCI accesses to the RFM Address Space Writing a zero 0 specifies Little Endian ordering Yes Yes 0 6 Reserved Yes No 0 7 DMA Channel 0 Big Endian Mode Address Invariance Writing a one 1 specifies use of Big...

Page 45: ... Interrupt Yes Yes 0 14 12 Reserved Yes No 0 15 Local Interrupt Input Active When set to a one 1 indicates the Local interrupt input is active Yes No 0 16 Reserved Yes No 1 17 Reserved Yes No 0 18 Local DMA Channel 0 Interrupt Enable Writing a one 1 enables DMA Channel 0 interrupts Clearing the DMA status bit also clears the interrupt Yes Yes 0 20 19 Reserved Yes No 0 21 DMA Channel 0 Interrupt Ac...

Page 46: ...catter Gather mode is enabled For Scatter Gather mode the DMA descriptors are loaded from memory in PCI Address space Writing zero 0 indicates DMA Block mode is enabled Yes Yes 0 10 Done Interrupt Enable A one 1 enables an interrupt when done Yes No 1 16 11 Reserved Yes No 00 17 DMA Channel 0 Interrupt Select A one 1 routes the DMA Channel 0 interrupt to the PCI bus interrupt Yes No 1 31 18 Reserv...

Page 47: ...nel 0 First Descriptor Address This field holds bits 31 4 of the first DMA descriptor address The first descriptor address must be aligned on a 16 byte boundary i e address bits 3 0 are considered to be 0 Yes Yes 0 Table 3 47 DMA Channel 0 Command Status Register DMACSR0 BAR0 1 Offset A8 Bit Description Read Write Value after PCI Reset 0 Channel 0 Enable Writing a one 1 enables channel to transfer...

Page 48: ...one 1 to all bits that must be included in decode and zero 0 to all others Used in conjunction with PCIBAR3 Yes No FFE0000 for 2 MB FF00000 for 16 MB FC00000 for 64 MB F800000 for 128 MB F000000 for 256 MB NOTE LAS1RR range must be power of 2 The LAS1RR range value is two s complement of the range Table 3 50 PCI PIO Direct Slave Local Base Address Remap LAS1BA BAR0 1 Offset F4 Bit Description Read...

Page 49: ...me bits reserved Some bits read only 17 14 LIER Local Interrupt Enable Reg read write 1B 18 NTD Network Target Data read write 32 Data bits for network target 1C NTN Network Target Node read write Target node ID for network Int 1D NIC Network Interrupt Command read write Select Int type and initiate interrupt 1F 1E Reserved 23 20 ISD1 Int 1 Sender Data read only 127 loc By 32 bit FIFO for network ...

Page 50: ...he node ID of the board This register reflects the setting of the onboard switch S2 and is read only Each board on a network must have a unique node ID 3 3 5 Local Control and Status Register 1 Local Control and Status Register 1 LCSR1 BAR2 Offset 08 A 32 bit register containing Reflective Memory control and status bits is described below Table 3 52 Local Control and Status Register 1 LCSR1 BAR2 O...

Page 51: ...7 Local Memory Parity Enable When this bit is set high 1 parity checking is enabled when reading from the RFM 5565 SDRAM Note that parity works only on 32 bit and 64 bit accesses Byte 8 bit Word 16 bit and 24 bit memory write accesses are inhibited while parity is enabled Bit 26 Redundant Mode Enabled When this bit is set high 1 redundant mode of network transfers has been enabled This bit is read...

Page 52: ...twork Offset 1 and Offset 0 will apply an offset to the network address as it is sent or received over the network The offset does not appear on local access to the memory and the offset does not alter network packets as they pass through the board Offset 1 and Offset 0 provide four possible binary increments of 64 MByte each through the 256 MByte network address range When the address and offset ...

Page 53: ... Status Register Bit 03 Latched Sync Loss A logic high 1 indicates the receiver circuitry has detected the loss of a valid signal at least once since the last time the flag has been cleared Under normal operating conditions this event should not occur and may indicate a loss of data A logic high may indicate the receiver s link was intentionally or unintentionally disconnected Bit 02 RX Signal Det...

Page 54: ...egister Bit Definitions Bits 31 through 16 Reserved These bits are reserved Bit 15 Auto Clear Flag This bit is a read only status indicator of the corresponding bit in the LIER Register When this bit is high 1 the Global Interrupt Enable Bit 14 will automatically be cleared as this register LISR is being read Clearing the Global Interrupt Enable de asserts the LINTi and in turn releases the PCI In...

Page 55: ...re times This bit is latched Once set it must be cleared by writing a zero to this bit location The assertion of the Latched Sync Loss usually indicates the receiver link was or is disconnected either intentionally or unintentionally and data may have been lost This event will also occur if the upstream node tied to the receiver is powered off or is disabled Bit 10 RX FIFO Full When this bit is hi...

Page 56: ...gnostic purposes only Bit 04 Reserved This bit is reserved Bit 03 Reset Node Request When this bit is high 1 another node on the network has requested that the local PCI bus master reset this board The RFM 5565 does not reset itself automatically Bit 02 Pending Net Int 3 When this bit is high 1 one or more type 3 network interrupts have been received To see the sender data and sender node ID s rea...

Page 57: ... register does not initiate the actual network interrupt This register is both read and write accessible The NTN register can be written or read with the Network Interrupt Command Register as a single 16 bit word Table 3 54 Local Interrupt Enable Register LIER BAR2 Offset 14 Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Reserved Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 Res...

Page 58: ...Interrupt 1 Sender ID FIFO Interrupt 1 Sender ID FIFO SID1 BAR2 Offset 24 An 8 bit FIFO containing the Node ID corresponding to the data in ISD1 Each time one node issues a network interrupt it includes its own node ID as part of the packet At each other network node the interrupt packet is evaluated If the network interrupt is directed to that node and if the network interrupt is of type 1 then t...

Page 59: ...ta FIFO Interrupt 3 Sender Data FIFO ISD3 BAR2 Offset 30 A 32 bit FIFO functioning just like ISD1 except it responds only to type 3 network interrupts 3 3 15 Interrupt 3 Sender ID FIFO Interrupt 3 Sender ID FIFO SID3 BAR2 Offset 34 An 8 bit FIFO functioning just like SID1 except it responds only to type 3 network interrupts 3 3 16 Interrupt 4 Sender Data FIFO Interrupt 4 Sender Data FIFO ISD4 BAR2...

Page 60: ...Interrupt 1 Data FIFO 127 Loc x 32 Bits Network Interrupt 2 Data FIFO 127 Loc x 32 Bits Network Interrupt 3 Data FIFO 127 Loc x 32 Bits Interrupt Detection and Routing Circuitry PCI Interrupt Interface Read Address Pointer 1 Read Address Pointer 2 Read Address Pointer 3 Read Address Pointer 4 Host Interrupt Transmitter Circuitry Receiver Circuitry Network Input Network Output Network Interrupt 4 S...

Page 61: ... waits for the interrupt to occur 4 After the DMA is finished clear the DMA completion bit with a write to DMACSR0 as follows This is necessary when using DMA interrupts DMA channel 0 Command Status register DMACSR0 at PCIBAR0 offset A8 Write 8 to clear the DMA completion bit before attempting another DMA DMA channel 0 mode setting Bit 9 set to 0 indicates the use of normal Block DMA not Scatter G...

Page 62: ...y For best performance each descriptor block should be aligned on a 16 byte or 8 byte boundary A descriptor chain must be created in PCI 32 bit memory space before starting a Scatter Gather DMA Each descriptor in the chain has this format 1st Dword Lower 32 bit PCI Address for Data each page must be aligned on an 8 byte boundary 2nd Dword Upper 32 bit PCI Address for Data 0 for 32 bit addressing 3...

Page 63: ...ACSR0 at PCIBAR0 offset A8 Write 8 to clear the DMA completion bit before attempting another DMA DMA channel 0 mode setting Bit 9 set to 1 indicates the use of Scatter Gather DMA not normal Block mode DMAMODE0 at PCIBAR0 offset 80 DMA channel 0 PCI starting address This register is unused during Scatter Gather DMA DMAPADR0 at PCIBAR0 offset 84 DMA channel 0 local starting address Set to the starti...

Page 64: ...sizes Bits 20 and 21 of RFM register LCSR1 PCIBAR2 Offset 08 indicate the full installed memory size Bit 19 of LCSR1 is connected to S1 switch position 3 and bit 22 of LCSR1 is connected to S1 switch position 4 Both bits 19 and 22 can be read by software 1 when on 0 when off The table below lists the number of PCI PIO window selections available with various RFM 5565 memory options Two registers i...

Page 65: ... taken effect and subsequent memory accesses will be to the new memory window In summary register LAS1RR is the range register corresponding to the size of the PCI window and is read only Register LAS1BA is the writeable base address register It is used to remap or offset the PCI PIO window to access other sections of the installed memory The RFM 5565 firmware prevents the user from entering an in...

Page 66: ...rite operation if other sources in the LISR are to remain unchanged 7 Using a read modify write operation set Bit 8 and Bit 11 high 1 in the INTCSR register at PCIBAR0 offset 68 Bit 8 is the PCI Interrupt Enable and Bit 11 is the Local Interrupt Input LINTi Enable 3 7 2 Servicing Network Interrupts Read the INTCSR register at PCIBAR0 offset 68 Verify that the Local Interrupt Input Active Bit 15 is...

Page 67: ... board from the chassis 8 Quality of cables and I O connections If products must be returned contact GE for a Return Material Authorization RMA Number This RMA Number must be obtained prior to any return RMA request forms can be obtained from www ge ip com rma GE Technical Support is available at 1 800 433 2682 in North America or 1 780 401 7700 for international calls Requests for Technical Suppo...

Page 68: ...e requirements for compliance to the following standards EN55024 EN55022 Class A EN60950 1 2006 International Compliance It has also met the following international levels European Union EN 55024 1998 A1 2001 A2 2003 ITE EN 55022 2006 A1 2007 Class A EN 60950 1 2006 United States FCC 47 CFR Part 15 Class A UL 60950 1 2nd Edition Australia New Zealand AS NZS CISPR 22 2006 Class A ITE EN55022 2006 A...

Page 69: ...al environment This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instruction manual may cause harmful interference to radio communications Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense CAUTION Chan...

Page 70: ...ARE PROVIDED AS IS WITH NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED INCLUDING BUT NOT LIMITED TO WARRANTIES OF DESIGN MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ALL OTHER LIABILITY ARISING FROM RELIANCE UPON ANY INFORMATION CONTAINED HEREIN IS EXPRESSLY DISCLAIMED GE Intelligent Platforms Information Centers Americas 1 800 322 3616 or 1 256 880 0444 Asia Pacifi...

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