GE PACSystems RX7i, Cpu Programmer'S Reference Manual

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Chapter 4. Ladder Diagram (LD) Programming
GFK-2950C February 2018 71
Memory Required for Bit Sequencer
Each bit sequencer uses a three-word array of control block information. The control block can be a
symbolic variable or it can be located in %R, %W, %L, or %P memory:
Word 1 current step number
Word 2 length of sequence (in bits)
Word 3 control word
Note: Do not write to the control block memory registers from other functions.
Word 3 (the control word) stores the state of the Boolean inputs and outputs of its associated
function in the following format:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
OK (status input
Reserved
EN (enable input
Notes:
Bits 0 through 13 are not used.
In the N operand, bits are entered as 1 through 16, not 0 through 15.
Operands for Bit Sequencer
Warning
Do not write to the Control Block memory with other instructions.
Overlapping references may cause erratic operation of BIT_SEQ.
Parameter Description Allowed Operands Optional
Address
(????) Beginning address of the Control Block, which is a three-word
array:
Word 1: current step number
Word 2: length of sequence in bits
Word 3: control word, which tracks the status of the last enabling
power flow and the status of the power flow to the right. Symbolic variables,
variables located in
%R, %W, %P, or %L No
Length (??) The number of bits in the bit sequencer, ST, that BIT_SEQ will
step through. 1

Length

256.
Constants No
R When R is energized, the step number of BIT_SEQ is set to the
value in N (default = 1), and the bit sequencer, ST, is filled with
zeroes, except for the current step number bit. Flow No
DIR (Direction) When DIR is energized, the step number of BIT_SEQ is
incremented prior to the shift. Otherwise, it is decremented. Flow No