Gage CompuGen 1100, Hardware Manual And Driver Installation Manual

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62 CompuGen 3250
The connector, JP1, is a 10-pin dual-in-line IDC header. The pinout of JP1 is shown below:
Pin Function Pin Function
1 GND 2 GND
3 CLK_IN 4 +5V
5 GND 6 GND
7 +5V 8 CLK_OUT
9 GATE 10 TRIGGER
A Master/Slave Timing Module links the CompuGen 3250 Master/Slave cards (see page 67 for more
information on installing Master/Slave cards).
Pin layout on CG3250 connector
1 CLK 35 GND
2 D0 36 GND
3 D1 37 GND
4 D2 38 GND
5 D3 39 GND
6 D4 40 GND
7 D5 41 GND
8 D6 42 GND
9 D7 43 GND
10 D8 44 GND
11 D9 45 GND
12 D10 46 GND
13 D11 47 GND
14 D12 48 GND
15 D13 49 GND
16 D14 50 GND
17 D15 51 GND
18 D16 52 GND
19 D17 53 GND
20 D18 54 GND
21 D19 55 GND
22 D20 56 GND
23 D21 57 GND
24 D22 58 GND
25 D23 59 GND
26 D24 60 GND
27 D25 61 GND
28 D26 62 GND
29 D27 63 GND
30 D28 64 GND
31 D29 65 GND
32 D30 66 GND
33 D31 67 GND
34 TRIG IN 68 GND
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