Future Electronics Microsemi Avalanche, User Manual

Page: 8 / 30

8
2.2 Block Diagram
The following block diagram shows all the components of the Avalanche Board.
Figure 1 - Avalanche Block Diagram
2.3 Board Overview
The Avalanche Board features a PolarFire MPF300TS-1FCG484EES FPGA with the following
capabilities:

20-Kb dual-port or two-port LSRAM block with a built-in single error correct double
error detect (SECDED) capability

64 × 12 two-port μSRAM block implemented as an array of latches

18 × 18 multiply-accumulate (MACC) block with a pre-adder, a 48-bit accumulator, and
an optional 16 deep × 18 coefficient RO

Built-in μPROM, modifiable at program time and readable at run time, for user data
storage

Digest integrity check for FPGA, μPROM, and sNVM

Low-power features:
o
Low device static power
o
Low inrush current
o
Low power transceivers
o
Unique Flash*Freeze mode

High-performance communication interfaces