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4
Board Components and Operations
This section describes the key components of the Avalanche Board and provides information
about important board operations.
4.1
DDR3 Memory Interface
One 4-Gb DDR3 SDRAM chip is provided to serve as flexible volatile memory for user
applications. The DDR3 interface is implemented in HSIO bank0 and bank1.
The DDR3 SDRAM specifications for the PolarFire device are:
One AS4C256M16D3A-12BIN chip connected in fly-by topology.
Density: 512 MB
Data rate: DDR3 16-bit up to 133 MHz clock rate
The DDR3 memory can operates up to 1066 MHz with gearing 1:4 for the 133-MHz PolarFire
fabric implementing a RISC-V system per example. The default board assembly available for
the DDR3 standard has RC terminations.
Figure 4 - DDR3 Memory Interface
For more information, see the Board Level Schematics document (provided separately).
4.2
SPI Serial Flash
The SPI flash specifications for the PolarFire device are:
Density: 64 Mb
Voltage: 2.7 V to 3.6 V (SST26VF064B)
Frequency: 104 MHz
Quantity: 1
SPI mode support : Modes 0 and 3
Dedicated bank: Bank3
