16
4.3.2
XCVR1 Interface
The XCVR1 interface has one lane that is connected to the SFP+ connector. The signals are
routed in the PCB as follows:
Lanes 0 is directly routed to the SFP+ connector.
The XCVR0 reference clock can be used with the XCVR1 interface.
The following figure shows the XCVR1 interface of the Avalanche Board.
Figure 7 - XCVR1 Interface
4.3.3
125-MHz Transceiver Reference Clock
A 125-MHz clock oscillator with an accuracy of +/-50 ppm is available on the board. This clock
oscillator is connected to the FPGA fabric to provide transceiver reference clock.
The transceiver supports reference clock connected as follows:
XCVR 0A reference clock is connected the on-board 125-MHz oscillator.
The following figure shows the XCVR reference clock interface of the Avalanche Board.
Figure 8 - Transceiver Reference Clock
PolarFire FPGA
Controls
Lane 0 / RXD
Lane 0 / TXD
XCVR_0A-REFCLK
125 MHz
Clock
SFP+
Controls
TX
RX
PolarFire FPGA
XCVR_0A-REFCLK
125 MHz
Clock
