1. Circuit Description
3
T
o
L
C
D Un
it
T
o
L
C
D Un
it
T
o
P
N
L
U
n
it
F
rom
Pers
on
al
Co
m
p
ute
r, Be
aco
n
Re
ce
iv
er
F
ro
m
Buil
t-
in
Be
aco
n Re
ce
iv
er
Progra
m
RO
M
(F
la
sh
R
O
M
)
8 Mbit
U
16
CR7
#26
#30,#41
#27
#31
MP
U
T
M
P68301
#43
#50-
52
DA
T
A
1
DA
T
A
3
#40
#41
#44
RS
-232C (
5
V
),
RS
-422 (
0
V
)
DA
T
A
2
J3
MO
B I
N
R
XD
T
XD
U
29 #18,U
30 #4
#14
#1
1
CH A
CH B
SI
O
RS
-232C(
U
29)
RS
-422(
U
30)
Se
le
ct
or
U
29,U
30
U
23
+
12 V
+5 V
-
20.5 V
DA
T
A
4
PO
W
E
R
A
ddr
es
s
G/
A
A
C
R
T
C Co
ntr
o
ll
er
,
L
C
D I
/F
, K
E
Y I
/F
16 MH
z
8 MH
z
U
15
RA
M
2 Mbit
CG
RO
M
4 Mbit
VI
DE
O
RA
M
3 Mbit
6.2 MH
z
A
ddr
es
s D
ata
AC
R
T
C
U5
Key
Data
P
ict
u
re Dat
a
←
L
at/L
o
n
g
,S
P
D
/CRS
,T
im
e D
ate
,e
tc
+5
V
G
P
S
IN
IT
IA
L
S
E
T
T
IN
G
→
U
12, U
13
U
21, U
27
U
14
U
24
U
25
U
26
CF
L
Re
g
u
la
to
r
C
o
n
trast
A
d
ju
st
er
.
#6
JP1
BT
1
#3
B
A
T V
O
L
T
De
te
ct
or
U
22
#2
V
B
AK
(+3V
)
T
o
ut1
Co
nne
cte
d
to
te
m
p
er
atur
e s
ens
ing
re
si
st
er(2
.7
V a
t a
b
ou
t 2
0
°C)
V
o
(
-16 V
to
–
20 V
)
J4
J1
0
14
J9
J1
1
T
o
G
PS
RECEI
V
ER
2
1, 4
5
3, 4
1, 2
1, 2
3, 4
1
3
2
3
3
1
1, 2
Br
il
li
ance
and Co
ntr
ast
A
d
juste
r. (
D
/A
CO
N
V
.)
U2
T
XD
R
XD
11
- 14
1 -
10
U3
Q
6
,Q
7,T
1
,U
1
J2
ON/
OF
F
S
w
itching
Re
g
u
la
to
r
C
o
n
troller
S
w
itching
Re
g
u
la
to
r
Q
16
U8
U
38
T
XD
R
XD
R
XD
T
XD
JP4
, JP5
CONT
A
C
T
S
IG.
GE
N
Fig
.1.
2 Block
diag
ra
m
of
NP boar
d