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4.7 Servo Control

4.7 Servo Control

The actuator motor and the spindle motor are submitted to servo control. The
actuator motor is controlled for moving and positioning the head to the track
containing the desired data. To turn the disk at a constant velocity, the actuator
motor is controlled according to the servo data that is written on the data side
beforehand.

4.7.1 Servo control circuit

Figure 4.6 is the block diagram of the servo control circuit. The following
describes the functions of the blocks:

Head

Spindle

motor

CSR

VCM

Position Sense

VCM current

CSR: Current Sense Resister
VCM: Voice Coil Motor

(1)

MPU/HDC/RDC

(2)

Servo

burst

capture

(3)

DAC

(4)

SVC

Power

Amp

(5)

Spindle

motor

control

(6)

Driver

(7)

MPU

core

Figure 4.6 Block diagram of servo control circuit

C141-E249

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Summary of Contents for MHW2040BS

Page 1: ...C141 E249 01EN MHW2120BS MHW2100BS MHW2080BS MHW2060BS MHW2040BS DISK DRIVES PRODUCT MANUAL ...

Page 2: ...ncidental or consequential damages arising therefrom FUJITSU DISCLAIMS ALL WARRANTIES REGARDING THE INFORMATION CONTAINED HEREIN WHETHER EXPRESSED IMPLIED OR STATUTORY FUJITSU reserves the right to make changes to any products described herein without further notice and without obligation This product is designed and manufactured for use in standard applications such as office work personal device...

Page 3: ...Revision History 1 1 Edition Date Revised section 1 Added Deleted Altered Details 01 2006 08 20 1 Section s with asterisk refer to the previous edition when those were deleted C141 E249 ...

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Page 5: ...This chapter gives an overview of the disk drive and describes their features CHAPTER 2 Device Configuration This chapter describes the internal configurations of the disk drive and the configuration of the systems in which they operate CHAPTER 3 Installation Conditions This chapter describes the external dimensions installation conditions and switch settings of the disk drive CHAPTER 4 Theory of ...

Page 6: ...entered followed below by the indented message A wider line space precedes and follows the alert message to show where the alert message begins and ends The following is an example Example Data corruption Avoid mounting the disk drive near strong magnetic sources such as loud speakers Ensure that the disk drive is not affected by external magnetic fields The main alert messages in the text are als...

Page 7: ... this manual and forward it to the address described in the sheet Liability Exception Disk drive defects refers to defects that involve adjustment repair or replacement Fujitsu is not liable for any other disk drive defects such as those caused by user misoperation or mishandling inappropriate operating environments defects in the power supply or cable problems of the host system or other causes o...

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Page 9: ...edure correctly Task Alert message Page Normal Operation Data corruption Avoid mounting the disk near strong magnetic sources such as loud speakers Ensure that the disk drive is not affected by external magnetic fields Damage Do not press the cover of the disk drive Pressing it too hard the cover and the spindle motor contact which may cause damage to the disk drive Static When handling the device...

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Page 11: ...L C141 E249 This manual Device Overview Device Configuration Installation Conditions Theory of Device Operation Interface Operations MHW2120BS MHW2100BS MHW2080BS MHW2060BS MHW2040BS DISK DRIVES MAINTENANCE MANUAL C141 F083 Maintenance and Diagnosis Removal and Replacement Procedure C141 E249 vii ...

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Page 13: ...ifications 1 9 1 5 Acoustic Noise 1 10 1 6 Shock and Vibration 1 10 1 7 Reliability 1 11 1 8 Error Rate 1 12 1 9 Media Defects 1 12 1 10 Load Unload Function 1 12 1 10 1 Recommended power off sequence 1 13 1 11 Advanced Power Management APM 1 13 1 12 Interface Power Management IPM 1 15 1 12 1 Host initiated interface power management HIPM 1 15 1 12 2 Device initiated interface power management DIP...

Page 14: ...ction 3 11 3 3 5 Note about SATA interface cable connection 3 11 CHAPTER 4 Theory of Device Operation 4 1 4 1 Outline 4 2 4 2 Subassemblies 4 2 4 2 1 Disk 4 2 4 2 2 Spindle 4 2 4 2 3 Actuator 4 2 4 2 4 Air filter 4 3 4 3 Circuit Configuration 4 3 4 4 Power on Sequence 4 6 4 5 Self calibration 4 8 4 5 1 Self calibration contents 4 8 4 5 2 Execution timing of self calibration 4 9 4 5 3 Command proce...

Page 15: ... 5 13 5 2 Logical Interface 5 14 5 2 1 Communication layers 5 15 5 2 2 Outline of the Shadow Block Register 5 16 5 2 3 Outline of the frame information structure FIS 5 17 5 2 4 Shadow block registers 5 24 5 3 Host Commands 5 29 5 3 1 Command code and parameters 5 29 5 3 2 Command descriptions 5 32 1 RECALIBRATE X 10 to X 1F 5 33 2 READ SECTOR S X 20 or X 21 5 34 3 WRITE SECTOR S X 30 or X 31 5 36 ...

Page 16: ...5 103 26 IDENTIFY DEVICE X EC 5 104 27 IDENTIFY DEVICE DMA X EE 5 105 28 SET FEATURES X EF 5 119 29 SECURITY SET PASSWORD X F1 5 126 30 SECURITY UNLOCK X F2 5 128 31 SECURITY ERASE PREPARE X F3 5 130 32 SECURITY ERASE UNIT X F4 5 131 33 SECURITY FREEZE LOCK X F5 5 132 34 SECURITY DISABLE PASSWORD X F6 5 134 35 READ NATIVE MAX ADDRESS X F8 5 136 36 SET MAX X F9 5 137 37 READ SECTOR S EXT X 24 5 143...

Page 17: ...mmand protocol 5 175 5 4 5 DMA data out command protocol 5 176 5 4 6 Native Command Queuing protocol 5 177 5 5 Power on and COMRESET 5 180 CHAPTER 6 Operations 6 1 6 1 Reset and Diagnosis 6 2 6 1 1 Response to power on 6 2 6 1 2 Response to COMRESET 6 4 6 1 3 Response to a software reset 6 7 6 2 Power Save 6 8 6 2 1 Power save mode 6 8 6 2 2 Power commands 6 10 6 3 Power Save Controlled by Interfa...

Page 18: ...Contents 6 5 1 Cache operation 6 20 Glossary GL 1 Acronyms and Abbreviations AB 1 Index IN 1 xiv C141 E249 ...

Page 19: ... configuration 4 5 Figure 4 3 Power on operation sequence 4 7 Figure 4 4 Read write circuit block diagram 4 10 Figure 4 5 Frequency characteristic of programmable filter 4 11 Figure 4 6 Block diagram of servo control circuit 4 13 Figure 4 7 Physical sector servo configuration on disk surface 4 16 Figure 4 8 Servo frame format 4 17 Figure 5 1 Interface signals 5 2 Figure 5 2 Example of the circuit ...

Page 20: ...out command protocol 5 176 Figure 5 18 READ FP DMA QUEUED command protocol 5 178 Figure 5 19 WRITE FP DMA QUEUED command protocol 5 179 Figure 5 20 Power on sequence 5 180 Figure 5 21 COMRESET sequence 5 181 Figure 6 1 Response to power on when the host is powered on earlier than the device 6 2 Figure 6 2 Response to power on when the device is powered on earlier than the host 6 3 Figure 6 3 Respo...

Page 21: ... 5 8 Operation of DOWNLOAD MICROCODE 5 45 Table 5 9 Example of rewriting procedure of data 512K Bytes 80000h Bytes of microcode 5 46 Table 5 10 Features Field values subcommands and functions 5 56 Table 5 11 Format of device attribute value data 5 60 Table 5 12 Format of guarantee failure threshold value data 5 60 Table 5 13 Off line data collection status 5 63 Table 5 14 Self test execution statu...

Page 22: ...res field values and settable modes 5 119 Table 5 36 Write Read Verify feature sector counts 5 125 Table 5 37 Contents of SECURITY SET PASSWORD data 5 126 Table 5 38 Relationship between combination of Identifier and Security level and operation of the lock function 5 126 Table 5 39 Contents of security password 5 134 Table 5 40 Data format of Read Log Ext log page 10h 5 149 Table 5 41 Tag field i...

Page 23: ...a Defects 1 10 Load Unload Function 1 11 Advanced Power Management APM 1 12 Interface Power Management IPM Overview and features are described in this chapter and specifications and power requirement are described The disk drive is 2 5 inch hard disk drives with built in disk controllers These disk drives use the SATA interface protocol which has a high speed interface data transfer rate C141 E249...

Page 24: ...has an internal data rate up to 61 3 MB s The disk drive supports an external data rate 1 5Gbps 150MB s Serial ATA Generation 1 And the disk drive realizes a high performance by high speed transfer rate combined with Native Command Queuing NCQ 5 Average positioning time Use of a rotary voice coil motor in the head positioning mechanism greatly increases the positioning speed The average positionin...

Page 25: ...g 3 Read ahead cache system After the execution of a disk read command the disk drive automatically reads the subsequent data block and writes it to the data buffer read ahead operation This cache system enables fast data access The next disk read command would normally cause another disk access But if the read ahead data corresponds to the data requested by the next read command the data in the b...

Page 26: ...A ATAPI 8 SATA I High Speed Serialized AT Attachment 1 0a SATA II Ext to SATA1 0a SATA II Electrical Spec 1 0 Data Transfer Rate 2 To From Media To From Host 61 3MB s Max 1 5 Gbps 150 MB s Data Buffer Size 3 8 MB 8 388 608 bytes Physical Dimensions Height Width Depth 9 5 mm 100 0 mm 70 0 mm 4 Weight 101 g Max 1 Capacity under the LBA mode 2 1 GB is equal to 1 000 000 000 bytes and 1 MB is equal to...

Page 27: ...pond to the product number as listed in Table 1 2 since some models have been customized and have specifications that are different from those for the standard model If a disk drive is ordered as a replacement drive the product number must be the same as that of the drive being replaced Table 1 2 Examples of model names and product numbers Model Name Capacity user area Mounting screw Order No MHW2...

Page 28: ...ximum 100 mV peak to peak Frequency DC to 1 MHz 3 Slope of an input voltage at rise The following figure shows the restriction of the slope which is 5 V input voltage at rise The permissible range of 5 V slope is from 1V 20 µsec to 1V 20 msec under the voltage range is between 2 0V and 4 5V Figure 1 1 Permissible range of 5V rise slope 1 6 C141 E249 ...

Page 29: ...re isn t to occur at 5 V when power is turned off and a thing with no ringing Permissible level 0 2 V Voltage V 5 0 100 200 300 400 500 600 700 800 Time ms 4 3 2 1 0 1 Figure 1 2 The example of negative voltage waveform at 5 V when power is turned off C141 E249 1 7 ...

Page 30: ...0 0075 W GB rank E MHW2080BS 0 0100 W GB rank D MHW2060BS 0 0150 W GB rank D MHW2040BS 1 Maximum current and power at starting spindle motor 2 Current and power level when the operation command that accompanies a transfer of 63 sectors is executed 3 times in 100 ms 3 Power requirements reflect typical values for 5 V power 4 Energy efficiency based on the Law concerning the Rational Use of Energy i...

Page 31: ...ions Table 1 4 Environmental specifications Item Specification Temperature Operating Non operating Thermal Gradient 5 C to 55 C ambient 5 C to 60 C disk enclosure surface 40 C to 65 C 20 C h or less Humidity Operating Non operating Maximum Wet Bulb 8 to 90 RH Non condensing 5 to 95 RH Non condensing 29 C Operating 40 C Non operating Altitude relative to sea level Operating Non operating 300 to 3 0...

Page 32: ...p surface 1 6 Shock and Vibration Table 1 6 lists the shock and vibration specification Table 1 6 Shock and vibration specification Item Specification Vibration Swept sine 1 4 octave per minute Operating Non operating 5 to 500 Hz 9 8m s 2 0 peak 1G 0 peak without non recovered errors 5 to 500 Hz 49m s 2 0 peak 5G 0 peak no damage Shock half sine pulse Operating Non operating 2940 m s 2 0 peak 300G...

Page 33: ...upply host system or interface cable 2 Mean time to repair MTTR The mean time to repair MTTR is 30 minutes or less if repaired by a specialist maintenance staff member 3 Service life In situations where management and handling are correct the disk drives requires no overhaul for five years or 30 000 hours of operation whichever occurs first when the DE surface temperature is less than 45 C When th...

Page 34: ...s 1 9 Media Defects Defective sectors are replaced with alternates when the disk drive is formatted prior to shipment from the factory low level format Thus the hosts see a defect free device Alternate sectors are automatically accessed by the disk drive The user need not be concerned with access to alternate sectors 1 10 Load Unload Function The Load Unload function is a mechanism that loads the ...

Page 35: ... Head Unload Standby Immediate command execution 3 Wait Status Checking whether bit 7 of the status register was set to 0 wait to complete STANDBY IMMEDIATE command 4 HDD power supply cutting 1 11 Advanced Power Management APM The disk drive automatically shifts to the power saving mode according to the setting of the APM mode under the idle condition The APM mode can be chosen with a Sector Count...

Page 36: ...ommands has been exceeded Mode 0 Mode shifts from Active condition to Active Idle in 3 4 seconds and to Low Power Idle in 15 minutes Mode 1 Mode shifts from Active condition to Active Idle in 3 4 seconds and to Low Power Idle in 10 40 seconds Mode 2 Mode shifts from Active condition to Active Idle in 3 4 seconds and to Low Power Idle in 10 40 seconds Remark The default values of these settings are...

Page 37: ...IPM modes automatically under the Idle condition 1 Partial mode PMREQ_P is sent when the disk drive requests the Partial mode 2 Slumber mode PMREQ_S is sent when the disk drive requests the Slumber mode I F power states 1 Active state The SATA interface is active and data can be sent and received 2 Partial state The SATA interface is in the Power Down state In this state the interface is switched ...

Page 38: ...9 Table 1 8 Interface power management IPM Mode I F power state Return time to active I F condition Active Active State Active Partial Partial State 5 to 10 µs maximum Power Down Slumber Slumber State 5 to 10 ms maximum Power Down ...

Page 39: ...ice Configuration 2 1 Device Configuration 2 2 System Configuration This chapter describes the internal configurations of the hard disk drives and the configuration of the systems in which they operate C141 E249 2 1 ...

Page 40: ...less DC motor 4 Actuator The actuator uses a revolving voice coil motor VCM structure which consumes low power and generates very little heat The head assembly at the edge of the actuator arm is controlled and positioned by feedback of the servo information read by the read write head If the power is not on or if the spindle motor is stopped the head assembly stays on the ramp out of the disk and ...

Page 41: ... high performance by integration into LSI 2 2 System Configuration 2 2 1 SATA interface Figure 2 2 shows the SATA interface system configuration The disk drive complies with ATA ATAPI 8 SATA I High Speed Serialized AT Attachment 1 0a SATA II Extensions to Serial ATA 1 0a and SATA II Electrical Spec 1 0 2 2 2 Drive connection Serial ATA Adapter Driver Operating System Application 1 Application 2 Ap...

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Page 43: ... 3 1 Dimensions 3 2 Mounting 3 3 Connections with Host System This chapter gives the external dimensions installation conditions surface temperature conditions cable connections and switch settings of the hard disk drives C141 E249 3 1 ...

Page 44: ...ot included in these dimensions 2 Dimension from the center of the user tap to the base of the connector pins 3 Length of the connector pins 4 Dimension from the outer edge of the user tap to the center of the connector pins 5 Dimension from the outer edge of the user tap to the innermost edge of the connector pins Figure 3 1 Dimensions 3 2 C141 E249 ...

Page 45: ...he HDD disk enclosure DE is zero The mounting frame is connected to Signal Ground SG IMPORTANT Use M3 screw for the mounting screw and the screw length should satisfy the specification in Figure 3 2 The tightening torque must be 0 49N m 5kgf cm When attaching the HDD to the system frame do not allow the system frame to touch parts cover and base other than parts to which the HDD is attached C141 E...

Page 46: ...ended values if it is not possible to satisfy them contact us Screw Screw Details of A 3 0 or less 3 0 or less Frame of system cabinet Frame of system cabinet B PCA A 2 2 5 2 5 2 5 2 5 DE Side surface mounting Bottom surface mounting Figure 3 2 Mounting frame structure 3 4 C141 E249 ...

Page 47: ...er hole mounted to the HDD do not allow this to close during mounting Locating of breather hole is shown as Figure 3 3 For breather hole of Figure 3 3 at least do not allow its around φ 3 to block Figure 3 3 Location of breather C141 E249 3 5 ...

Page 48: ...n the cabinet such that the PCA side in particular receives sufficient cooling To check the cooling efficiency measure the surface cover temperatures of the DE Regardless of the ambient temperature this surface cover temperature must meet the standards listed in Table 3 1 Figure 3 4 shows the temperature measurement point 1 Figure 3 4 Surface cover temperature measurement points Table 3 1 Surface ...

Page 49: ...d speakers Ensure that the disk drive is not affected by external magnetic fields Damage Do not press the cover of the disk drive Pressing it too hard the cover and the spindle motor contact which may cause damage to the disk drive Static When handling the device disconnect the body ground 500 kΩ or greater Do not touch the printed circuit board but hold it by the edges 6 Handling cautions Please ...

Page 50: ... avoid falling down Do not drop Figure 3 6 Handling cautions Installation 1 Please use the driver of a low impact when you use an electric driver HDD is occasionally damaged by the impact of the driver 2 Please observe the tightening torque of the screw strictly M3 0 49N m 5 kgf cm Recommended equipments Contents Model Maker Wrist strap JX 1200 3056 8 SUMITOMO 3M ESD ESD mat SKY 8A Color Seiden Ma...

Page 51: ... 3 3 1 Device connector The disk drive has the SATA interface connectors listed below for connecting external devices Figure 3 7 shows the locations of these connectors and terminals SATA interface and power connectors PCA Figure 3 7 Connector locations C141 E249 3 9 ...

Page 52: ...tor specifications for the host system Segment Name Model Manufacturer SATA interface and power supply Host receptacle 67492 0220 Molex or compatibles IMPORTANT The above connector specifications for the host system indicate only that its mating with the SATA interface connecter is confirmed Accordingly the number connecter insertion extractions including hot plugging is not guaranteed The connect...

Page 53: ...tion Take note of the following precaution about plugging a SATA interface cable into the SATA interface connector of the disk drive and plugging the connector into a host receptacle When plugging together the disk drive SATA interface connector and the host receptacle or SATA interface cable connector do not apply more than 10 kgf of force in the connection direction once they are snugly and secu...

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Page 55: ...guration 4 4 Power on Sequence 4 5 Self calibration 4 6 Read write Circuit 4 7 Servo Control This chapter explains basic design concepts of the disk drive Also this chapter explains subassemblies of the disk drive each sequence servo control and electrical circuit blocks C141 E249 4 1 ...

Page 56: ...n outer diameter of 65 mm and an inner diameter of 20 mm Servo data is recorded on each cylinder total 134 Servo data written at factory is read out by the read head For servo data see Section 4 7 4 2 2 Spindle The spindle consists of a disk stack assembly and spindle motor The disk stack assembly is activated by the direct drive sensor less DC spindle motor which has a speed of 5 400 rpm 1 The sp...

Page 57: ...SI with MCU and HDC The PreAMP consists of the write current switch circuit that flows the write current to the head coil and the voltage amplifier circuit that amplitudes the read output from the head The RDC is the read demodulation circuit using the Modified Extended Partial Response MEEPR and contains the Viterbi detector programmable filter adaptable transversal filter times base generator da...

Page 58: ...d data transfer control Data buffer management Sector format control Defect management ECC control Error recovery and self diagnosis S DRAM SVC 3 3V Generator Circuit 1 2V Generator Circuit MCU HDC RDC Integration 3V Generator Circuit PreAMP 5 0V 3 3V 3 0V 1 2V Figure 4 1 Power supply configuration 4 4 C141 E249 ...

Page 59: ... Circuit Configuration MCU HDC RDC HDC MCU RDC Data Buffer SDRAM SVC Crystal R W Pre Amp Thermistor VCM HEAD SP Motor Media DE PCA Serial ATA I F Shock Sensor Figure 4 2 Circuit configuration C141 E249 4 5 ...

Page 60: ...e self diagnosis terminates successfully the disk drive starts the spindle motor c The disk drive executes self diagnosis data buffer read write test d After confirming that the spindle motor has reached rated speed the head assembly is loaded on the disk e The disk drive positions the heads onto the SA area and reads out the system information f The drive becomes ready The host can issue commands...

Page 61: ...e spindle motor starts Self diagnosis 2 Data buffer write read test b Confirming spindle motor speed c Load the head assembly Drive ready state command waiting state g Execute self calibration f Initial on track and read out of system information e End SATA I F Initialization d Figure 4 3 Power on operation sequence C141 E249 4 7 ...

Page 62: ...ng by the cylinder the disk is divided into 13 areas from the innermost to the outermost circumference and the compensating value is measured at the measuring cylinder on each area at factory calibration The measured values are stored in the SA cylinder In the self calibration the compensating value is updated using the value in the SA cylinder 2 Compensating open loop gain Torque constant value o...

Page 63: ...ands The number of retries to write or seek data reaches the specified value The error rate of data reading writing or seeking becomes lower than the specified value 4 5 3 Command processing during self calibration This enables the host to execute the command without waiting for a long time even when the disk drive is performing self calibration The command execution wait time is about maximum 72 ...

Page 64: ...nt in writing Each channel is connected to each data head and PreAMP switches channel by serial I O In the event of any abnormalities including a head short circuit or head open circuit the write unsafe signal is generated so that abnormal write does not occur 4 6 2 Write circuit The write data is transferred from the hard disk controller HDC to the RDC in LSI The write data is sent to the PreAMP ...

Page 65: ...amplifier output is maintained at a constant level even when the head output fluctuates due to the head characteristics or outer inner head positions 2 Programmable filter circuit The programmable filter circuit has a low pass filter function that eliminates unnecessary high frequency noise component and a high frequency boost up function that equalizes the waveform of the read signal Cut off freq...

Page 66: ...tes data according to the survivor path sequence 4 6 4 Digital PLL circuit The drive uses constant density recording to increase total capacity This is different from the conventional method of recording data with a fixed data transfer rate at all data area In the constant density recording method data area is divided into zones by radius and the data transfer rate is set so that the recording den...

Page 67: ...olled according to the servo data that is written on the data side beforehand 4 7 1 Servo control circuit Figure 4 6 is the block diagram of the servo control circuit The following describes the functions of the blocks Head Spindle motor CSR VCM Position Sense VCM current CSR Current Sense Resister VCM Voice Coil Motor 1 MPU HDC RDC 2 Servo burst capture 3 DAC 4 SVC Power Amp 5 Spindle motor contr...

Page 68: ...e the head position from the servo data on the data surface From the servo area on the data area surface via the data head the burst signals of EVEN1 ODD EVEN2 are output as shown in Figure 4 8 in subsequent to the servo mark gray code that indicates the cylinder position and index information The servo signals do A D convert by Fourier demodulator in the servo burst capture circuit At that time t...

Page 69: ... servo format Figure 4 7 describes the physical layout of the servo frame The three areas indicated by 1 to 3 in Figure 4 7 are described below 1 Inner guard band This area is located inside the user area and the rotational speed of the VCM can be controlled on this cylinder area for head moving 2 Data area This area is used as the user data area and SA area 3 Outer guard band This area is located...

Page 70: ...Ln 1 CYLn CYLn 1 n even number W R Recovery Servo Mark Gray Code W R Recovery Servo Mark Gray Code W R Recovery Servo Mark Gray Code EVEN1 ODD EVEN2 Post code MHW2120BS only PAD Diameter direction Figure 4 7 Physical sector servo configuration on disk surface 4 16 C141 E249 ...

Page 71: ...ad recovery This area is used to absorb the write read transient and to stabilize the AGC 2 Servo mark This area generates a timing for demodulating the gray code and position demodulating the burst signal by detecting the servo mark 3 Gray code including sector address bits This area is used as cylinder address The data in this area is converted into the binary data by the gray code demodulation ...

Page 72: ...e head is stopped at the reference cylinder from there Track following control starts 2 Seek operation Upon a data read write request from the host the MPU confirms the necessity of access to the disk If a read write instruction is issued the MPU seeks the desired track The MPU feeds the VCM current via the D A converter and power amplifier to move the head The MPU calculates the difference speed ...

Page 73: ...hase U phase to W phase and V phase to W phase after that repeating this order The above operations mean the generation of rotational magnetic field d During phase switching the spindle motor starts rotating in low speed and generates a back electromotive force The SVC detects this back electromotive force and reports to the MPU using a PHASE signal for speed detection e The MPU is waiting for a P...

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Page 75: ...rface 5 1 Physical Interface 5 2 Logical Interface 5 3 Host Commands 5 4 Command Protocol 5 5 Power on and COMRESET This chapter gives details about the interface and the interface commands and timings C141 E249 5 1 ...

Page 76: ...log front end GND Figure 5 1 Interface signals An explanation of each signal is provided below TX TX These signals are the outbound high speed differential signals that are connected to the serial ATA cable RX RX These signals are the inbound high speed differential signals that are connected to the serial ATA cable TxData Serially encoded 10b data attached to the high speed serial differential li...

Page 77: ...MWAKE out of band signal is being detected COMRESET COMINIT Host Signal from the out of band detector that indicates the COMINIT out of band signal is being detected Device Signal from the out of band detector that indicates the COMRESET out of band signal is being detected 5VDC GND 5VDC 5 V power supply to the disk drive GND Ground for each signal and 5 V power supply C141 E249 5 3 ...

Page 78: ... During OOB signaling transmissions the differential and common mode levels of the signal lines shall comply with the same electrical specifications as for in band data transmission specified as follows COMRESET COMINIT 106 7 ns 320 ns COMWAKE 106 7 ns 106 7 ns 5 4 C141 E249 ...

Page 79: ...he transmitter does not have the next payload data ready for transmission HOLD is also transmitted on the backchannel when a receiver is not ready to receive additional payload data HOLDA Hold acknowledge This primitive is sent by a transmitter as long the HOLD primitive is received by its companion receiver PMNAK Power management denial Sent in response to a PMREQ_S or PMREQ_P when a receiving no...

Page 80: ...ent node host or device is ready to receive payload SOF Start of frame Start of a frame Payload and CRC follow to EOF SYNC Synchronization Synchronizing primitive always idle WTRM Wait for frame termination After transmission of any of the EOF the transmitter will transmit WTRM while waiting for reception status from receiver X_RDY Transmission data ready Current node host or device has payload re...

Page 81: ... 6667 666 4333 670 2333 ftol TX Frequency Long Term Stability ppm 350 350 fSSC Spread Spectrum Modulation Frequency kHz 30 33 SSCtol Spread Spectrum Modulation Deviation ppm 5000 0 Vcm dc DC Coupled Common Mode Voltage mV 250 200 450 Vcm ac coupled AC Coupled Common Mode Voltage mV 0 2000 Zdiff Nominal Differential Impedance ohm 100 Cac coupling AC Coupling Capacitance nF 12 tsettle cm Common Mode...

Page 82: ...TX TX Differential Output Voltage mVppd 500 400 600 Differential nominal measured at Serial ATA connector on transmit side 250mV differential seria l ATA connector t20 80TX TX Rise Fall Time ps UI 0 15 20 80 0 41 20 80 Rise 20 80 at transmitter Fall 80 20 at transmitter tskewTX TX Differential Skew ps 20 TJ at Connector Data Data 5UI UI 0 355 DJ at Connector Data Data 5UI UI 0 175 TJ at Connector ...

Page 83: ... Vthresh OOB Signal Detection Threshold mVppd 100 50 200 UIOOB UI During OOB Signaling ps 666 67 646 67 686 67 COMINIT COMRESET and COMWAKE Transmit Burst Length UIOOB 160 COMINIT COMRESET Transmit Gap Length UIOOB 480 COMWAKE Transmit Gap Length UIOOB 160 Units May detect Shall detect Shall not detect Comments COMWAKE Gap Detection Windows ns 55 T 175 101 3 T 112 T 55 or 175 COMINIT COMRESET Gap ...

Page 84: ...charge 2nd mate P8 V5 5 V power P9 V5 5 V power P10 Gnd 2nd mate P11 Staggered Spin up Mode Ready LED Staggered Spin up mode detect for input Ready LED drive for output For the specification of P11 see Section 5 1 5 in next page When the host system does not use these function the corresponding pin to be mated with P11 in the power cable receptacle connector shall be grounded P12 Gnd 1st mate P13 ...

Page 85: ... after successful Phy initialization at power on Default setting b P11 Grounded 0 8 V or less Staggered Mode Disable The disk drive spins up at power on c P11 High level The P11 line in the host system is pulled up by resistor recommended value 1 to 5 1 kΩ to power supply in the host system Recommended voltage 2V 3 3V or less Staggered Mode Enable The drive does not spin up until after successful ...

Page 86: ...Interface Figure 5 2 Example of the circuit for driving Ready LED 5 12 C141 E249 ...

Page 87: ...valent circuit of 5V power supply at Hot Plugging is in the following figure It is necessary to choose pre charge resistor RL value which is in permissible range of 5V power supply specification at the host system Refer to the equivalent circuit when the optimized value of pre charge resistor RL It is recommended to choose the minimum value which is in permissible range of 5V power supply specific...

Page 88: ...ice and between layers at the same level that link the host and device Figure 5 3 is a conceptual diagram of the communication layers Host Software control Buffer Memory DMA engine s Host located layers Physical Layer Link Layer Transport Layer Device located layers Physical Layer Link Layer Transport Layer Device Software control Buffer memory DMA engine s Application layer 4 Transport layer 3 Li...

Page 89: ...uests between the host system and device Encodes serial data as 10 or 8 bit data then converts it into DWORD data Inserts auxiliary signals SOF CRC and EOF deletes auxiliary signals and communicates with the transport and physical layers Transport layer Exchanges data in communication with the link layer and builds the frame information structure FIS Contains a Shadow Block Register Reflects the F...

Page 90: ...unt exp Sector Count Sector Number exp Sector Number Sector Number exp Sector Number Cylinder Low exp Cylinder Low Cylinder Low exp Cylinder Low Cylinder High exp Cylinder High Cylinder High exp Cylinder High Device Head Status Command Control Block registers Alternate Status Device Control Note Each of the Sector Count Sector Number Cylinder Low and Cylinder High fields has a higher order field u...

Page 91: ...or Host to Device Bidirectional DMA Setup Set Device Bits Device to Host SetDB BIST Active Bidirectional BIST Active PIO Setup Device to Host PIO Setup Data Host to Device or Device to Host Bidirectional DATA 5 2 3 2 Register Host to Device The Register Host to Device FIS has the following layout 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 ...

Page 92: ...d 0 Sector Count exp Sector Count 3 Reserved 0 Reserved 0 Reserved 0 Reserved 0 4 Figure 5 5 Register Device to Host FIS layout The Register Device to Host FIS is used when information concerning the Shadow Register Block in the host adapter is updated This FIS indicates that the device has completed a command operation Furthermore this is a mechanism for changing information concerning the Shadow...

Page 93: ...igure 5 7 DMA Setup Device to Host or Host to Device FIS layout The DMA Setup Device to Host or Host to Device FIS communicates the start of a first party DMA access to the host system This FIS is used to request the host system or device to set up the DMA controller before the start of a DMA data transfer A Auto Active bit If this bit is cleared 0 is set for the bit it indicates that a DMA Active...

Page 94: ...IS can be sent by either the host system or device The following combinations of pattern definitions are supported Table 5 5 BIST combinations T A S L F P V SC Reg Contents 1 1 09h SATA Phy Analog Loopback Mode 1 10h Far End Retimed Loopback Mode 1 1 C0h No ALIGN Transmit_only Mode Scramble ON 1 1 1 1 E0h No ALIGN Transmit_only Mode Scramble OFF 1 1 1 C4h No ALIGN Transmit_only with primitive Mode...

Page 95: ...Type 5Fh 0 Dev Head Cyl High Cyl Low Sector Number 1 Reserved 0 Cyl High exp Cyl Low exp Sector Num exp 0 2 E_Status Reserved 0 Sector Count exp Sector Count 3 Reserved 0 Transfer Count 4 Figure 5 10 PIO Setup Device to Host FIS layout The PIO Setup FIS is a device to host FIS FIS Type 5Fh The PIO Setup FIS is used by the device to provide the host adapter with the data transfer count and DRQ bloc...

Page 96: ...lock E_Status Contains the new value of the status register of the task file block for correct synchronization of data transfers to host Error Contains the new value of the Error register of the Command Block at the conclusion of all subsequent Data to Device frames I Interrupt bit This bit reflects the interrupt bit line of the device R Reserved 0 Sector Count Holds the contents of the sector cou...

Page 97: ...f both the BSY bit and the DRQ bit in the shadow Status register are zero when the frame is received Error Contains the new value of the Error register of the Shadow Register Block Status Hi Contains the new value of bits 6 5 and 4 of the Status register of the Shadow Register Block Status Lo Contains the new value of bits 2 1 and 0 of the Status register of the Shadow Register Block SActive The S...

Page 98: ...ble error and SB not found Or SATA Frame Error Write SFRW This bit indicates that a SATA communication error has been encountered during the write process In this case bit4 and bit2 are set both Bit 3 SATA Frame Error Read SF RR This bit indicates that a SATA communication error has been encountered during the read process In this case bit3 and bit2 are set both Bit 2 Aborted Command ABRT This bit...

Page 99: ... number of remaining sectors that the data has not been transferred due to the error However as of the last sector of PIO transfer SC 1 indicates the normal completion The contents of this field also have other definitions Refer to 5 4 4 Sector Number Field exp The contents of this field indicates the starting sector number for the subsequent command The sector number should be between X 01 and th...

Page 100: ...of this field indicate the device and the head number When executing INITIALIZE DEVICE PARAMETERS command the contents of this field defines the number of heads minus 1 a maximum head No Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X L X X HS3 HS2 HS1 HS0 Bit 7 Unused Bit 6 L 0 for CHS mode and 1 for LBA mode Bit 5 Unused Bit 4 Unused Bit 3 HS3 CHS mode head address 3 23 bit 27 for LBA mode Unu...

Page 101: ...e Ready DRDY bit This bit indicates that the device is capable to respond to a command The IDD checks its status when it receives a command If an error is detected not ready state the IDD clears this bit to 0 This is cleared to 0 at power on and it is cleared until the rotational speed of the spindle motor reaches the steady speed Bit 5 Device Write Fault DF bit This bit indicates that a device fa...

Page 102: ...quired to execute the DASP handshake 11 E_Status Field This field is in the PIO Setup FIS The field contents are the same as those described in 8 Status Field However the values in the Status field are those before a PIO data transfer and the values in the E_Status field are those when a PIO data transfer is completed 12 DMA Buffer Offset Field This field is in the DMA Setup FIS representing byte ...

Page 103: ...eters Table 5 6 lists the supported commands command code and the related fields to be written necessary parameters at command execution Table 5 6 Command code and parameters 1 3 COMMAND CODE Bit PARAMETER USED COMMAND NAME 7 6 5 4 3 2 1 0 FR SC SN CY DH RECALIBRATE 0 0 0 1 X X X X N N N N D READ SECTOR S 0 0 1 0 0 0 0 R N Y Y Y Y WRITE SECTOR S 0 0 1 1 0 0 0 R N Y Y Y Y WRITE VERIFY 0 0 1 1 1 1 0...

Page 104: ... 0 0 N N N N D FLUSH CACHE 1 1 1 0 0 1 1 1 N N N N D WRITE BUFFER 1 1 1 0 1 0 0 0 N N N N D IDENTIFY DEVICE 1 1 1 0 1 1 0 0 N N N N D IDENTIFY DEVICE DMA 1 1 1 0 1 1 1 0 N N N N D SET FEATURES 1 1 1 0 1 1 1 1 Y N N N D SECURITY SET PASSWORD 1 1 1 1 0 0 0 1 N N N N D SECURITY UNLOCK 1 1 1 1 0 0 1 0 N N N N D SECURITY ERASE PREPARE 1 1 1 1 0 0 1 1 N N N N D SECURITY ERASE UNIT 1 1 1 1 0 1 0 0 N N N ...

Page 105: ...D FLUSH CACHE EXT 1 1 1 0 1 0 1 0 N N N N D WRITE MULTIPLE FUA EXT 1 1 0 0 1 1 1 0 N Y Y Y D WRITE DMA FUA EXT 0 0 1 1 1 1 0 1 N Y Y Y D READ FP DMA QUEUED 0 1 1 0 0 0 0 0 Y Y Y Y D WRITE FP DMA QUEUED 0 1 1 0 0 0 0 1 Y Y Y Y D CY cylinder field DH device head field FR features field SC sector count field SN sector number field R Retry at error 1 Without retry 0 With retry Y Necessary to set param...

Page 106: ... 8 SN EXP LBA 31 24 SN EXP LBA 31 24 SN Start sector No LBA 7 0 SN End sector No LBA 7 0 SC EXP Transfer sector count 15 8 SC EXP X 00 SC Transfer sector count 7 0 SC X 00 FR EXP xx FR xx ER Error information CH EXP Cylinder High Field EXP CL EXP Cylinder Low Field EXP CM Command Field DH Device Head Field ER Error Field FR EXP Features Field EXP L LBA Logical Block Address setting bit SN EXP Sect...

Page 107: ...ditions 1 An error was detected during head positioning ST 51h ER 02h 2 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 0 0 0 1 x x x x DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx xx Error information Note Also...

Page 108: ... contain the cylinder head and sector addresses in the CHS mode or logical block address in the LBA mode of the last sector read If an unrecoverable disk read error occurs in a sector the read operation is terminated at the sector where the error occurred Shadow block registers contain the cylinder the head and the sector addresses of the sector in the CHS mode or the logical block address in the ...

Page 109: ...ector No LBA LSB Transfer sector count xx R Retry At command completion Shadow Block Registers contents to be read ST Status information DH x L x x HDNo LBA CH CL SN SC ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 01 1 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred C141 E249 5 35 ...

Page 110: ...es of the last sector written If an disk error occurs during multiple sector write operation the write operation is terminated at the sector where the error occurred Shadow block registers contain the cylinder the head the sector addresses in the CHS mode or the logical block address in the LBA mode of the sector where the error occurred Error reporting conditions 1 A specified address exceeds the...

Page 111: ...LBA LSB Transfer sector count xx R Retry At command completion Shadow Block Registers contents to be read ST Status information DH x L x x HDNo LBA CH CL SN SC ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 00 1 Error information 1 If the command was terminated because of an error the number of sectors for which data has not been written is set in this field C141 E249 5 3...

Page 112: ...ansfer of dummy data ST 51h ER 10h 3 A write fault was detected when the write cache was disabled ST 71h ER 10h 4 While the write cache is enabled if the status indicating a completed transfer STS 50h is returned and a data write operation failed because a write fault was detected during the data write operation Abort will be returned for all subsequent ATA commands ST 71h ER 04h This state is cle...

Page 113: ...n DH x L x x HDNo LBA CH CL SN SC ER Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB 00 1 Error information 1 If the command is terminated because of an error the number of remaining sectors for which data has not been written or verified is set in this register C141 E249 5 39 ...

Page 114: ...e LBA mode of the sector where the error occurred The Sector Count field indicates the number of sectors that have not been verified Error reporting conditions 1 A specified address exceeds the range where read operations are allowed ST 51h ER 10h 2 The range where read operations are allowed will be exceeded by an address during a read operation ST 51h ER 10h 3 An uncorrectable disk read error oc...

Page 115: ...nformation DH x L x x HDNo LBA CH CL SN SC ER Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB 00 1 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register C141 E249 5 41 ...

Page 116: ...e range where the head can be positioned ST 51h ER 10h 2 Head positioning is not possible because an error occurred ST 51h ER 10h 3 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 0 1 1 1 x x x x DH x L x x HD No LBA CH CL SN SC FR Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB xx xx At command completion...

Page 117: ... detected HDC diagnostic error Data buffer diagnostic error Memory diagnostic error Reading the system area is abnormal Calibration abnormal Note The device responds to this command with the result of power on diagnostic test Error reporting conditions 1 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 0 0 1 0 0 0 0 DH x x x x HD No...

Page 118: ...even after soft reset and COMRESET issuance or power save operation regardless of the setting of disabling the reverting to default setting The operation is always performed in CHS mode with the command ignoring any setting of LBA mode Error reporting conditions 1 00h is specified in the SC field ST 51h ER 04h 2 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Reg...

Page 119: ...iting according to Subcommand code Rewriting is also possible simultaneously with the data transfer Refer to Table 5 8 In the data transfer of Subcommand code 01h transfer by which data is divided into multiple times is possible Refer to Table 5 9 After the designation of rewriting by Subcommand code 07h reactivates in the device for the update of the rewriting microcode of the microcode Table 5 8...

Page 120: ...nsfer of 512 KB Firmware rewriting execution Transfer example 3 1 CMD 92h SN SC 0400h FR 07h Transfer of 512 KB and Firmware rewriting execution Transfer example 4 1 CMD 92h SN SC 0100h FR 0lh 2 CMD 92h SN SC 0100h FR 0lh 3 CMD 92h SN SC 0100h FR 0lh 4 CMD 92h SN SC 0100h FR 07h Transfer of 128 KB 0 to 127 KB from the beginning Transfer from 128 to 255 KB Transfer from 256 to 383 KB Transfer from ...

Page 121: ...t support the APS timer function Error reporting conditions 1 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM X 94 or X E0 DH x x x x Xx CH CL SN SC FR xx xx xx xx Xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x Xx CH CL SN SC ER xx xx xx xx Error information C141 E249 5 47 ...

Page 122: ... command does not support the APS timer function Error reporting conditions 1 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM X 95 or X E1 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx xx Error information 5 48 C...

Page 123: ... not emergency load unload guarantee count per the device life Even if the device executes reading look ahead operation or executes writing operation the device unloads the head s to the ramp position as soon as possible when received the IDLE IMMEDIATE command with the Unload Feature When the writing operation is stopped the device keeps the unwritten data And the device keeps the unloaded state ...

Page 124: ... the period specified as the APS timer value the device automatically enters Standby mode If the Sector Count field value is 0 the APS timer is disabled when the command is received Under the standby mode the spindle motor is stopped Thus when the command involving a seek such as READ SECTOR s command is received the device processes the command after driving the spindle motor Error reporting cond...

Page 125: ...dby mode The APS timer is set to prohibition if the Sector Count field s value was 0 when device has received this command The period of timer count is set depending on the value of the Sector Count register as shown below Sector Count field value Point of timer 0 X 00 Timeout disabled 1 to 240 X 01 to X F0 Value 5 seconds 241 to 251 X F1 to X FB Value 240 30 min 252 X FC 21 minutes 253 X FD 8 hrs...

Page 126: ...Interface At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx xx Error information 5 52 C141 E249 ...

Page 127: ...ts the status to the host system Power save mode Sector Count field During moving to Standby mode Standby mode X 00 Idle mode X FF Active mode X FF Error reporting conditions 1 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM X 98 or X E5 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents...

Page 128: ...n the sleep mode the spindle motor is stopped The only way to release the device from sleep mode is to execute a software or COMRESET Error reporting conditions 1 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM X 99 or X E6 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST...

Page 129: ...ylinder Low field and C2h in the Cylinder High field If the key values are incorrect the Aborted Command error is issued If the failure prediction function is disabled the device returns the Aborted Command error to subcommands other than those of the SMART Enable Operations with the Features field set to D8h If the failure prediction function is enabled the device collects and updates data on spe...

Page 130: ...es were saved then the attributes are saved However if the automatic attribute save function is disabled the attributes are not saved Upon receiving this subcommand a device enables or disables the automatic attribute save function and transfers the RegDH then reports the status In this drive this function is enabled at the shipment from the factory X D3 SMART SAVE ATTRIBUTE VALUES When the device...

Page 131: ...ormat See Table 5 22 concerning the SMART selective self test log data format See Table 5 25 concerning the SCT Status Request data format X D6 SMART WRITE LOG A device which receives this sub command when it has prepared to receive data from the host computer it transfers the PIOSU Next it receives data from the host computer and writes the specified log sector in the Sector Number Field SN SC Lo...

Page 132: ...ector Count field specification 00 state This setting is preserved whether the drive s power is switched on or off If 24 hours have passed since the power was switched on or since the last time that off line data were collected off line data collection is performed without relation to any command from the host computer The host must regularly issue the SMART READ DATA subcommand Features field D0h...

Page 133: ...atus C2h 2Ch Key failure prediction status 4Fh F4h xx xx Error information The attribute value information is 512 byte data the format of this data is shown the following Table 5 11 The host can access this data using the SMART READ DATE subcommand Features field D0h The guarantee failure threshold value data is 512 byte data the format of this data is shown the following Table 5 12 The host can a...

Page 134: ...ta collection capability 170 171 Trouble prediction capability flag 172 Error logging capability 173 Self test error detection point 174 Simple self test Quick Test execution time min 175 Comprehensive self test Comprehensive Test execution time min 176 Conveyance self test execution time min 177 to 181 Reserved 182 to 1FE Vendor unique 1FF Check sum Table 5 12 Format of guarantee failure threshol...

Page 135: ...dicates unused attribute data 1 Read Error Rate 2 Throughput Performance 3 Spin Up Time 4 Start Stop Count 5 Reallocated Sector Count 7 Seek Error Rate 8 Seek Time Performance 9 Power On Hours Count 10 Spin Retry Count 12 Drive Power Cycle Count 192 Emergency Retract Cycle Count 193 Load Unload Cycle Count 194 HDA Temperature 195 ECC On the Fly Count 196 Reallocated Event Count 197 Current Pending...

Page 136: ...T is disabled 6 to 15 Reserve bit Current attribute value It indicates the normalized value of the original attribute value The value deviates in a range of 01h to 64h range of 01h to C8h for the Ultra ATA CRC error rate and communication error rate It indicates that the closer the value is to 01h the higher the possibility of a failure The host compares the attribute value with the threshold valu...

Page 137: ...us Table 5 14 Self test execution status Bit Meaning 0 to 3 Remainder of the self test is indicated as a percentage in a range of 0h to 9h corresponding to 0 to 90 4 to 7 Self test execution status 0h Self test has ended successfully or self test has not been executed 1h Self test is suspended by the host 2h Self test is interrupted by a soft reset COMRESET from the host 3h Self test cannot be exe...

Page 138: ...is supported 4 If this bit is 1 it indicates that the SMART Self test function is supported 5 If this bit is 1 it indicates that the SMART Conveyance Self test is supported 6 If this bit is 1 it indicates that the SMART Selective Self test is supported 7 Reserved bits Failure prediction capability flag Table 5 16 Failure prediction capability flag Bit Meaning 0 If this bit is 1 it indicates that t...

Page 139: ...of sector 101 Address 80h Reserved 102 to 13F Address 81h to Address 9Fh 102 and 13F are both the same format as 100 101 140 to 1FF Reserved SMART error logging If the device detects an unrecoverable error during execution of a command received from the host the device registers the error information in the SMART Summary Error Log see Table 5 19 and the SMART Comprehensive Error Log see Table 5 20...

Page 140: ...ld value 34 Sector Count field value 35 Sector Number field value 36 Cylinder Low field value 37 Cylinder High field value 38 Drive Head field value 39 Command field value 3A to 3D Command data structure Elapsed time after the power on sequence unit ms 3E Reserved 3F Error field value 40 Sector Count field value 41 Sector Number field value 42 Cylinder Low field value 43 Cylinder High field value ...

Page 141: ...tus register when an error occurs Total number of drive errors Indicates total number of errors registered in the error log Checksum Two s complement of the lower byte obtained by adding 511 byte data one byte at a time from the beginning Status Bits 0 to 3 Indicates the drive status when received error commands according to the following table Bits 4 to 7 Vendor unique Status Meaning 0 Unclear st...

Page 142: ...A 1C3 5 th Error Log Data Structure5 Error Log Data Structure 5n 5 1C4 1C5 Total number of drive errors Reserved 1C6 1FE Reserved Reserved 1FF Check sum Check sum n indicates sector number in the Error Log The first sector is 0 SMART Self Test The host computer can issue the SMART Execute Off line Immediate sub command Features field D4h and cause the device to execute a self test When the self te...

Page 143: ...1F9 Self test log 2 to 21 Each log data format is the same as that in byte 02 to 19 1FA 1FB Vendor unique 1FC Self test index 1FD 1FE Reserved 1FF Check sum Self test number Indicates the type of self test executed Self test execution status Same as byte 16Bh of the attribute value Self test index If this is 00h it indicates the status where the self test has never been executed Checksum Two s com...

Page 144: ...der Unique 1Ech 1F3h Current LBA under test 1F4h 1F5h Current Span under test 1F6h 1F7h Feature Flags 1F8h Offline Execution Flag 1F9h Selective Offline Scan Number 1FAh 1FBh Vender Unique Reserved 1FCh 1FDh Selective Self test pending time min 1FEh 1FFh Checksum Test Span Selective self test log provides for the definition of up to five test spans If the starting and ending LBA values for a test ...

Page 145: ...or specific unused 3 When set to one off line scan after selective test is pending 4 When set to one off line scan after selective test is active 5 15 Reserved Bit l shall be written by the host and returned unmodified by the device Bit 3 4 shall be written as zeros by the host and the device shall modify them as the test progress Selective Self test pending time min The selective self test pendin...

Page 146: ...and and the Key Sector Format data of 512 bytes is received from the host and a device execute the specific operation for which the action code For information about the format of the Key Sector Format see Table 5 28 to Table 5 31 X E1 X D5 SCT READ DATA A device that received this subcommand transfers the data table of the number of sectors specified with Sector Count field to the host It is nece...

Page 147: ...Table 5 25 of the device At command issuance Shadow Block Registers setting CM 1 0 1 1 0 0 0 0 DH x x x DV Xx CH CL SN SC FR Key C2h Key 4Fh E0h 01h D5h At command completion Shadow Block Registers contents to be read ST Status information DH x x x DV xx CH CL SN SC ER xx xx xx xx Error information C141 E249 5 73 ...

Page 148: ...ET MAX EXT DCO 1 A WRITE SAME command to all logical blocks has completed without error 00Ah Drive State 00h Active 01h not support Standby 02h not support Sleep 03h DST executing in background 04h SMART Off line Data collection executing in background 05h SCT command executing in background 06h FFh Reserved 00Bh to 00Dh Reserved 00Eh 00Fh Extended Status Code Status of last SCT command issued See...

Page 149: ...of SCT command executing in background 030h to 0C7h Reserved 0C8h HDA Temp C Current drive HDA temperature 0C9h Reserved 0CAh Max Temp C Maximum HDA temperature this power cycle 0CBh Reserved 0CCh Life Max Temp C Maximum HDA temperature the life of the device 0CDh to 1DFh Reserved 1E0h to 1FFh Vender specific C141 E249 5 75 ...

Page 150: ...09h Background SCT command was terminated because of unrecoverable error 000Ah Invalid function code in LONG SECTOR ACCESS command 000Bh SCT data transfer command was issued without first issuing an SCT command 000Ch Invalid function code in Feature Control command 000Dh Invalid Feature Code in Feature Control command 000Eh Invalid New State in Feature Control command 000Fh Invalid Option Flag in ...

Page 151: ...d executes each function to show in Table 5 28 to Table 5 31 28 bit command At command issuance Shadow Block Registers setting CM 1 0 1 1 0 0 0 0 DH x x x DV Xx CH CL SN SC FR Key C2h Key 4Fh E0h 01h D6h At command completion Shadow Block Registers contents to be read ST Status information DH x x x DV xx CL SN ER xx xx xx CH SC xx Error information C141 E249 5 77 ...

Page 152: ...ic 0000h Reserved 0006h to BFFFh Table 5 28 WRITE SAME 1 2 Byte Name Value Description 000h 001h Action Code 0002h WRITE SAME 0001h Repeat Write Pattern It initializes it by data pattern of 32bit specified with byte 014h 017h 0002h Repeat Write data block It initializes it by data pattern of 1sct transfer by the SCT Write data Repeat Write Pattern Foreground 002h 003h Function Code 0102h Repeat Wr...

Page 153: ...e Description 000h 001h Action Code 0003h ERROR RECOVERY CONTROL 0001h Set New Value The retry processing when making an error in the specified timer 002h 003h Function Code 0002h Return Current Value The timer value of the error recovery being set now is displayed in SN SC field 0001h Read Timer 005h Selection Code 0002h Write Timer 006h 007h Value 2 byte Set to Timer Value x 100 ms Minimum value...

Page 154: ... Set Feature command 0002h Force Write Cache enabled 0003h Force Write Cache disable Feature Code 0002h Set Write Reordering 0001h Enable Write Reordering 0002h Disable Write Reordering 006h 007h New State 2 byte Feature Code 0003h Set time interval 0000h Invalid 0001h FFFFh Logging interval in minutes ex 0001h Temperature data collection interval is 1min 000Fh Temperature data collection interval...

Page 155: ...1h Action Code 0005h SCT DATA TABLE 002h 003h Read Data Table Function Code 0001h 0000h Invalid 0001h Reserved 0002h HAD Temperature History Table See Table 5 32 0003h to CFFFh Reserved 004h 005h Table ID D000h to FFFFh Vender Specific 006h to 1FFh Reserved Reserved C141 E249 5 81 ...

Page 156: ... 006h Max Operation Limit C 007h Over Limit C 008h Min Operation Limit C 009h Under Limit C Reserved to 01Fh 020h 021h Index of temperature log 022h to 0A1h Temperature log 128 data Entry 80h temperature log at Power cycle and default value is 80h 022h Temp Log No 0 023h Temp Log No 1 to 0A1h Temp Log No 127 0A2h 1FFh Reserved 00Ah to 01Dh 01Eh Number of logs that can be recorded in temperature lo...

Page 157: ...tting CM 1 0 1 1 0 0 0 0 x DV Xx CH CL SN SC FR Key C2h Key 4Fh E1h xx D5h DH x x At command completion Shadow Block Registers contents to be read ST Status information DH x x x DV xx CH CL SN xx SC ER xx xx xx Error information SCT READ DATA Command issue procedure 1 Issue the SCT set command of action code 0005h 2 Issue the SCT READ DATA command and receive the HDA temperature data from the devi...

Page 158: ...egisters setting 0 1 1 1 1 1 1 x DV Xx CH CL SN SC FR Key C2h Key 4Fh E1h xx D6h CM 1 DH x x At command completion Shadow Block Registers contents to be read ST Status information DH x x x DV CL SC ER xx xx xx Error information xx CH SN xx SCT WRITE DATA Command issue procedure 1 Issue the SCT set command of action code 0002h and function code 0002h 2 Issue the SCT write command and the write data...

Page 159: ...d command error is posted FR field Command C1h DEVICE CONFIGURATION FREEZE C2h DEVICE CONFIGURATION IDENTIFY DEVICE CONFIGURATION SET 00h BFh C4h FFh Reserved C0h DEVICE CONFIGURATION RESTORE C3h At command issuance Shadow Block Registers setting contents CM 1 0 1 1 0 0 0 1 DH x x x x xx CH CL SN SC xx xx xx xx FR C0h C1h C2h C3h At command completion Shadow Block Registers contents to be read ST ...

Page 160: ...3 The SET MAX ADDRESS EXT command F9h 37h has been specified with a value in the Host Protected Area ST 51h ER 04h 4 A SATA communication error occurred ST 51h ER 14h DEVICE CONFIGURATION FREEZE LOCK Features Field C1h The DEVICE CONFIGURATION FREEZE LOCK command prevents accidental modification of the Device Configuration Overlay settings After successful execution of a DEVICE CONFIGURATION FREEZ...

Page 161: ...in IDENTIFY information When the bits in these words are cleared the device no longer supports the indicated command mode or feature set If a bit is set in the overlay transmitted by the device that is not set in the overlay received from a DEVICE CONFIGURATION IDENTIFY command no action is taken for that bit After execution of this command the settings are kept regardless of the power on COMRESET...

Page 162: ... Bit 1 1 Ultra DMA mode 1 and below are supported Bit 0 1 Ultra DMA mode 0 is supported 3 to 6 Maximum LBA address Reflected in IDENTIFY information WORD60 61 WORD100 103 7 X 79CF Command set feature set supported Reflected in IDENTIFY information WORD82 87 Bit 15 Reserved Bit 14 1 Write Read Verify feature supported Bit 13 1 SMART Conveyance self test supported Bit 12 1 SMART Selective self test ...

Page 163: ...2 1 Interface power management supported Bit 1 1 Non zero buffer offsets in DMA Setup FIS supported 9 X 0000 Reserved for Serial ATA X 0000 Reserved 21 X 2000 Bits 15 14 Reserved Bit 13 Write uncorrectable is allowed Bit 12 0 Reserved 22 to 254 X 0000 Reserved 255 X xxA5 Bits 15 8 Check sum code This is obtained by calculating the sum of all upper bytes and lower bytes in WORD 0 to 256 and the byt...

Page 164: ...en transferred including the error sector and either the cylinder head and sector addresses of the error sector CHS mode or the logical block address of the error sector LBA mode are set in the Shadow Block Register READ MULTIPLE command specifies Number of requested sectors 9 Sector Count register 9 If the number of requested sectors is not divided evenly having the same number of sectors block c...

Page 165: ...R 40h 1 A specified address exceeds the range where read operations are allowed ST 51h ER 10h 2 The range where read operations are allowed will be exceeded by an address during a read operation ST 51h ER 10h 4 The sync byte indicating the beginning of a sector was not found ST 51h ER 01h 5 The READ MULTIPLE command is disabled ST 51h ER 04h 6 A SATA communication error occurred ST 51h ER 0Ch 7 An...

Page 166: ...completion Shadow Block Registers contents to be read ST Status information DH x L x x HDNo LBA CH CL SN SC ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 1 Error information 1 If the command is completed normally the number of remaining sectors is set in this field If the command is terminated because of an error the number of sectors for which data has not been transfer...

Page 167: ...write operation has been attempted for the transferred blocks and partial block The write operation stops at the sector where the error occurred even if the write operation has not reached the end of the block At this time the number of remaining sectors the error sector and subsequent sectors and either cylinder head and sector addresses of the error sector CHS mode or the logical block address o...

Page 168: ... Transfer sector count xx R Retry At command completion Shadow Block Registers contents to be read ST Status information DH x L x x HDNo LBA CH CL SN SC ER Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB 00 1 Error information 1 If the command was terminated because of an error the number of sectors for which data has not been written is set in this field 5 94 C141 E249...

Page 169: ... If the value of the Sector Count register is not a supported block count an ABORTED COMMAND error is posted and the READ MULTIPLE and WRITE MULTIPLE commands are disabled If the contents of the Sector Count field is 0 when the SET MULTIPLE MODE command is issued the READ MULTIPLE and WRITE MULTIPLE commands are disabled When the SET MULTIPLE MODE command operation is completed the device reports ...

Page 170: ...Interface At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx Sector count block Error information 5 96 C141 E249 ...

Page 171: ...fer stops after all data including the data of the sector where the error was detected is transferred The device notifies the host of the status by sending the RegDH FIS At this time the number of remaining sectors including the sector where the error was detected and either cylinder head and sector addresses CHS mode or the logical block address LBA mode of the sector where the error was detected...

Page 172: ...B Transfer sector count xx At command completion Shadow Block Registers contents to be read ST Status information DH x x L x HDNo LBA CH CL SN SC ER Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB 00 1 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register 5 98 C141 E249 ...

Page 173: ...or was detected and either cylinder head and sector addresses CHS mode or the logical block address LBA mode of the sector where the error was detected are stored in the Shadow Block Register A host system can select the following transfer mode using the SET FEATURES command however the transfer speed does not change Ultra DMA transfer mode 0 to 5 1 A specified address exceeds the range where writ...

Page 174: ... Start cylinder No LSB LBA xx At command completion Shadow Block Registers contents to be read ST Status information DH x L HDNo LBA x x CL SN SC ER Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB 00 1 Error information CH 1 If the command was terminated because of an error the number of sectors for which data has not been written is set in this field 5 100 C141 E249 ...

Page 175: ...ost system can read up to 512 bytes of data from the buffer Error reporting conditions 1 A SATA communication error occurred ST 51h ER 0Ch At command issuance Shadow Block Registers setting contents CM 1 1 0 1 0 1 0 0 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x xx x x CH CL SN xx xx SC ER xx xx Error info...

Page 176: ...n case a non recoverable disk write error has occurred while the data is being read the error generation address is put into the shadow block register before ending the command This error sector is deleted from the write cache data Error reporting conditions 1 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 0 0 1 1 1 DH x x x x...

Page 177: ...is transferred from the host and the device writes the data to the buffer then reports the status Error reporting conditions 1 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 0 1 0 0 0 x x x x xx CH CL SN SC FR xx xx xx xx xx DH At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx...

Page 178: ...he parameter information including a 512 byte date Table 5 34 shows the values of the parameter words and the meaning in the buffer Error reporting conditions 1 A SATA communication error occurred ST 51h ER 0Ch At command issuance Shadow Block Registers setting contents CM 1 1 1 0 1 1 0 0 DH x x x x xx CL SN SC xx xx xx xx xx CH FR At command completion Shadow Block Registers contents to be read S...

Page 179: ...de this command functions in the same way as the Identify Device command Error reporting conditions 1 A SATA communication error occurred ST 51h ER 0Ch CM 1 1 1 0 1 1 1 0 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx xx Error information C141 E249 5 105 ...

Page 180: ... 27 46 Set by a device Model name ASCII code 40 characters left 47 X 8010 Maximum number of sectors per block on READ WRITE MULTIPLE command 48 X 0000 Reserved X 2F00 Capabilities 4 50 X 4000 Capabilities 5 51 X 0200 PIO data transfer mode 6 52 X 0200 Reserved 53 X 0007 Enable disable setting of words 54 58 and 64 70 88 7 54 Variable Number of current Cylinders 55 Variable Number of current Head 5...

Page 181: ...n number 11 81 X 0021 Minor version number 82 X 346B Support of command sets 12 83 X 7F09 Support of command sets 13 84 X 61xx Support of command sets function 14 85 15 Valid of command sets function 15 86 16 Valid of command sets function 16 87 17 Default of command sets function 17 88 X xx3F Ultra DMA transfer mode 18 89 Set by a device Security Erase Unit execution time 1 LSB 2 min 19 90 X 0000...

Page 182: ...tatus 23 129 159 X xxxx Undefined 160 205 X 0000 Reserved 206 X 003D SCT Command sets supported 30 207 209 X 0000 Reserved 210 211 X xxxx Write Read Verify Sector Count Mode 3 Only 31 212 213 X xxxx Write Read Verify Sector Count Mode 2 Only 32 214 221 X 0000 Reserved 222 X 100F Transport major version number 223 X 0021 Transport minor version number 224 254 X 0000 Reserved 255 X xxA5 Check sum Th...

Page 183: ...nce in order to spin up The Identify information is incomplete 8C73h The device requires the SET FEATURES sub command after the power on sequence in order to spin up The Identify information is incomplete C837h The device requires the SET FEATURES sub command after the power on sequence in order to spin up The Identify information is incomplete Others Reserved 4 Word 49 Capabilities Bits 15 14 Res...

Page 184: ... the word 54 58 8 Word 59 Transfer sector count currently set by READ WRITE MULTIPLE command Bits 15 9 Reserved Bit 8 1 Enable the multiple sector transfer Bits 7 0 Transfer sector count currently set by READ WRITE MULTIPLE command without interrupt supports 2 4 8 and 16 sectors 9 Word 63 Multiword DMA transfer mode Bits 15 11 Reserved Bit 10 1 multiword DMA mode 2 is selected Bit 9 1 multiword DM...

Page 185: ...WORD 75 X 001F 32 12 WORD 76 Bits 15 11 Reserved Bit 10 1 Supports the PHY event counter Bit 9 1 Supports the Power Management initiation request from the host system Bit 8 1 Supports the Native command queueing Bits 7 4 Reserved Bit 3 Reserved for SATA Bit 2 1 Supports the Gen 2 signaling speed Bit 1 1 Supports the Gen 1 signaling speed 1 5Gbps Bit 0 Reserved C141 E249 5 111 ...

Page 186: ...d Bit 6 1 Enables the software settings preservation Bit 5 Reserved Bit 4 1 Enables the in order data delivery Bit 3 1 Enables the Power Management initiation function from Bit 2 1 Enables the Auto Activate optimization function in the DMA Setup FIS Bit 1 1 Enables the non zero buffer offset function in the DMA Setup FIS Bit 0 Reserved 15 WORD 80 Bits 15 9 Reserved Bit 8 1 ATA ATAPI 8 ACS ST suppo...

Page 187: ...power management feature set Bit 2 1 Supports the Removable Media feature set Bit 1 1 Supports the Security Mode feature set Bit 0 1 Supports the SMART feature set 17 WORD 83 Bit 15 0 Bit 14 1 Bit 13 1 Supports the FLUSH CACHE EXT command Bit 12 1 Supports the FLUSH CACHE command Bit 11 1 Supports the Device Configuration Overlay feature set Bit 10 1 48 bit LBA feature set Bit 9 1 Automatic Acoust...

Page 188: ...RITE MULTIPLE FUA EXT commands Bit 5 1 Support the General Purpose Logging feature Bits 4 2 Reserved Bit 1 1 Supports the SMART SELF TEST Bit 0 1 Supports the SMART Error Logging 19 WORD 85 Bit 15 Undefined Bit 14 1 Supports the NOP command Bit 13 1 Supports the READ BUFFER command Bit 12 1 Supports the WRITE BUFFER command Bit 11 Undefined Bit 10 1 Supports the Host Protected Area function Bit 9 ...

Page 189: ...e Media Status Notification function Bit 3 1 Enables the Advanced Power Management function Bits 2 0 Same definition as WORD 83 21 WORD 87 Bit 5 1 Supports the Mode 5 Bit 15 0 The device always returns the fixed value indicated on the left Bit 14 1 The device always returns the fixed value indicated on the left Bits 13 0 Same definition as WORD 84 22 WORD 88 Bit 15 8 Currently used Ultra DMA trans...

Page 190: ...e mode BF 80 Acoustic mode 00 Acoustic management is unused it It is same as FE CO 25 WORD 100 103 When 48 bit LBA of the option customize is supported same number of LBA as WORD 60 61 is displayed 26 WORD 106 Bit 15 0 The device always returns the fixed value indicated on the left Bit 14 1 The device always returns the fixed value indicated on the left Bit 13 1 Each device has several logical sec...

Page 191: ...erify feature set is enabled 0 Write Read Verify feature set is disabled Bit 0 1 Clearing DRQ bit to zero when error bit is set is enabled The drive doesn t execute the dummy transferring 0 Clearing DRQ bit to zero when error bit is set is disabled The drive executes the dummy transferring 29 WORD 128 Bits 15 9 Reserved Bit 8 Security level 0 High 1 Maximum Bits 7 6 Reserved Bit 5 1 Enhanced secur...

Page 192: ...or Access supported Bit 0 1 SCT Command Transport supported 31 WORD 210 211 Write Read Verify Sector Count Mode 3 Only Optional The number of sectors to be verified If Write Read Verify feature set is enabled Mode 3 Value 0x400 0x40000 sector 32 WORD 212 213 Write Read Verify Sector Count Mode 2 Only Optional The number of sectors to be verified If Write Read Verify feature set is enabled Mode 2 V...

Page 193: ...4 Enables the automatic reassign Note 1 X 05 Enables the advanced power management function 2 X 06 Enables the Power Up In Standby function Note 1 X 07 Spin up the Power Up In Standby status device Note 1 X 0B Enable Write Read Verify feature set 5 X 10 Enables the Serial ATA function 3 X 33 Undefined Note 1 X 42 Enables the Acoustic management function 4 X 54 Undefined Note 1 X 55 Disables the re...

Page 194: ...e 2 Note 1 Although there is a response to the command nothing is done Note 2 Although there is a response to the command and this command reflects on Identify Device information DRQ bit is always cleared to zero when error is occurred in PIO read command This drive always doesn t the dummy transferring At power on the default mode is set as follows Write cache function Enabled Transfer mode PIO M...

Page 195: ...on error occurred ST 51h ER 14h At command issuance Shadow Block O registers setting contents CM 1 1 1 0 1 1 1 1 DH x x x x xx CH CL SN SC FR xx xx xx xx or 1 3 See Table 5 6 At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC E xx xx xx xx Error information C141 E249 5 121 ...

Page 196: ... 88 in IdentifyDevice information However the actual data transfer rate depends on the serial ATA signaling rate in WORD 76 in IdentifyDevice information Transfer mode Sector Count file 00000 000 X 00 00001 000 X 08 Mode 0 00001 001 X 09 Mode 1 00001 010 X 0A Mode 2 00001 011 X 0B Mode 3 00001 100 X 0C Mode 4 00010 000 X 10 Mode 0 00010 001 X 11 Mode 1 00010 010 X 12 Mode 2 00100 000 X 20 Mode 0 0...

Page 197: ...ent level shifts is from Active Idle to Low Power Idle The Mode 0 level requires the longest shifting time depending on the APM level settings The settings of the APM level revert to their default values Mode 1 when power on or COMRESET occurs for the drive APM Level Sector Count Field Mode 0 Active Idle Low Power Idle Mode 1 Active Idle Low Power Idle Mode 2 Active Idle Low Power Idle Reserve Sta...

Page 198: ...der Data Delivery 04h 1 05h 1 Software Settings Preservation 06h 4 Asynchronous Notification 1 The device normally responds to the command but performs no operation 2 This feature is disabled when power is on While this function is enabled the device does not return the DMA Activate FIS for the first data sector after the WRITE FP DMA QUEUED command is issued 3 This feature is disabled when power ...

Page 199: ...nd low speed seek by which the seek sound is suppressed operates as for Acoustic mode Setting the seek mode by this command is applied to the seek operation in all command processing 5 Write Read Verify feature optional Table 5 36 Write Read Verify feature sector counts SC SN Description 00h Mode 0 Enabled Always 01h Mode 1 The first 65 536 logical sectors written by the host after every spin up o...

Page 200: ...alue is valid only when Word 0 Bit 0 is set to one 18 to 255 Reserved 0 Control Table 5 38 Relationship between combination of Identifier and Security level and operation of the lock function Identifier Level Description User High The specified password is set as a new user password The lock function is enabled after the device is turned off and then on LOCKED MODE can be canceled using the user p...

Page 201: ...1h ER 04h 3 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 1 0 0 0 1 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Register contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx xx Error information C141 E249 5 127 ...

Page 202: ...ed with the user password already set If the passwords are the same LOCKED MODE is canceled Otherwise the Aborted Command error is returned If the password comparison fails the device decrements the UNLOCK counter The UNLOCK counter initially has a value of five When the value of the UNLOCK counter reaches zero this command or the SECURITY ERASE UNIT command causes the Aborted Command error until ...

Page 203: ...5 3 Host Commands At command completion Shadow Block Register contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx xx Error information C141 E249 5 129 ...

Page 204: ... then the SECURITY ERASE UNIT command The SECURITY ERASE PREPARE command prevents data from being erased unnecessarily by the SECURITY ERASE UNIT command Error reporting conditions 2 A SATA communication error occurred ST 51h ER 14h CM 1 1 1 1 1 0 0 1 x x x xx CH CL SN xx SC FR xx xx xx xx DH x At command completion Shadow Block Registers contents to be read ST Status information DH x x xx x x CH ...

Page 205: ...idates the user password the master password is retained To recover the master password issue the SECURITY SET PASSWORD command and reset the user password Error reporting conditions 1 An incorrect password is specified ST 51h ER 04h 2 The Security Erase Prepare command did not complete normally beforehand ST 51h ER 04h 3 The device is in Security Frozen mode ST 51h ER 04h 4 A SATA communication e...

Page 206: ...n the power is turned off If this command is reissued in FROZEN MODE the command is completed and FROZEN MODE remains unchanged The following medium access commands return the Aborted Command error when the device is in LOCKED MODE READ DMA EXT READ MULTIPLE EXT WRITE DMA EXT READ SECTORS EXT READ VERIFY SECTORS EXT WRITE MULTIPLE EXT WRITE SECTORS EXT WRITE VERIFY SECURITY DISABLE PASSWORD SECURI...

Page 207: ...g conditions 1 The device is in Security Locked mode ST 51h ER 04h 2 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 1 1 0 1 0 DH x x x x xx CH CL SN FR xx SC xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx xx Error information C141 E249 5 ...

Page 208: ...aster password is retained To recover the master password issue the SECURITY SET PASSWORD command and reset the user password If the user password or master password transferred from the host does not match the Aborted Command error is returned Issuing this command while in LOCKED MODE or FROZEN MODE returns the Aborted Command error The section about the SECURITY FREEZE LOCK command describes LOC...

Page 209: ...Security Frozen mode ST 51h ER 04h 4 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 1 1 0 0 1 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx xx Error information C141 E249 5 135 ...

Page 210: ...hen reports the status to the host system Error reporting conditions 1 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 1 1 0 0 0 DH x L x x xx CH CL SN xx SC FR xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x Max head LBA MSB CH CL SN SC ER CYL No MSB LBA CYL No LSB ...

Page 211: ... command is held even after power on When the VV bit is 0 the value set by this command becomes invalid when the power is turned on and the maximum address returns to the value most lately set when VV bit 1 When the command with VV 1 has not issued before the maximum address returns to the default value When the READ NATIVE MAX ADDRESS command has been issued immediately preceding this command thi...

Page 212: ...ck Registers setting contents CM 1 1 1 1 1 0 0 1 DH x L x x HD No LBA CH CL CYL No MSB LBA CYL No LSB LBA SCT No LBA LSB SC xx VV FR xx SN At command completion Shadow Block Registers contents to be read ST Status information x x x x xx CH CL SN SC ER CYL No MSB LBA CYL No LSB LBA xx SCT No LBA LSB Error information DH SET MAX SET PASSWORD Features Field 01h This command requests a transfer of 1 s...

Page 213: ...ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 1 1 0 0 1 x x x x xx CH CL SN SC FR xx xx xx xx 01 DH At command completion Shadow Block Registers contents to be read ST Status information DH CH CL SC SN ER xx xx xx xx xx Error information Password information Words Contents 0 Reserved 1 to 16 Password 32 bytes 17 to 255 Reserved C141 E249 5 139 ...

Page 214: ...il a power cycle or the acceptance of SET MAX UNLOCK or SET MAX FREEZE LOCK command Error reporting conditions 1 The device is in Set Max Locked mode or Set Max Freeze Locked mode ST 51h ER 04h 2 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents 1 1 1 1 1 0 1 DH x x x x xx CH CL SN SC FR xx xx xx xx 02 CM 0 At command completion Shadow Bl...

Page 215: ...er reaches zero then SET MAX UNLOCK command returns command aborted until a power cycle If the password compare matches then the device makes a transition to the Set Max Unlocked state and all SET MAX commands will be accepted Error reporting conditions 1 The device is in Set Max Locked mode or Set Max Freeze Locked mode ST 51h ER 04h 2 The device is in Set Max Unlocked mode ST 51h ER 04h 3 A SATA...

Page 216: ...SET PASSWORD SET MAX LOCK SET MAX UNLOCK 1 The device is in Set Max Locked mode or Set Max Freeze Locked mode ST 51h ER 04h At command issuance Shadow Block Registers setting contents SET MAX FREEZE LOCK Error reporting conditions 2 A SATA communication error occurred ST 51h ER 14h CM 1 1 1 1 1 0 0 1 DH x x x x xx CL SN FR xx xx xx CH SC xx 04 At command completion Shadow Block Registers contents ...

Page 217: ...was issued in CHS mode ST 51h ER 04h The other error reporting conditions are the same as those of the READ SECTOR S command At command issuance Shadow Block Registers setting contents CM 0 0 1 0 0 0 1 0 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx At command completion Shadow Block...

Page 218: ...d in CHS mode ST 51h ER 04h The other error reporting conditions are the same as those of the READ DAM command At command issuance Shadow Block Registers setting contents CM 0 0 1 0 0 1 0 1 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx At command completion Shadow Block Registers con...

Page 219: ...SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 0 0 1 0 0 1 1 1 DH 1 L 1 xx x CH EXP CH FR EXP xx CL EXP CL SN EXP SN SC EXP SC FR xx xx xx xx xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER Native max address LBA 47 40 Native...

Page 220: ...issued in CHS mode ST 51h ER 04h The other error reporting conditions are the same as those of the READ MULTIPLE command At command issuance Shadow Block Registers setting contents CM 0 0 1 0 1 0 0 1 DH 1 L CH CL EXP SN EXP SN SC EXP SC FR EXP FR LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx 1 x xx CH EXP CL At command completion Shadow Block Reg...

Page 221: ...n be read by specifying Sector offset 00h Sector count 01h and Log address 10h For the data format of Read Log Ext log page 10h see Table 5 40 The events of the PHY level on an interface are collected and it registers with Read Log Extend page 11h This Read Log Ext log page can be read by specifying Sector offset 00h Sector count 01h and Log address 11h For the data format of Read Log Ext log page...

Page 222: ...SN EXP SN SC EXP SC FR EXP FR xx xx Sector offset 15 8 Sector offset 7 0 xx Log address Sector count 15 8 Sector count 7 0 xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH EXP CH CL SC EXP xx CL EXP SN EXP SN SC ER xx xx xx xx xx xx xx Error information 5 148 C141 E249 ...

Page 223: ...8 Sector Number Exp field value 09 Cylinder Low Exp field value 0A Cylinder High Exp field value 0B Sector Count field value Sector Count Exp field value 0E to FF Reserved 100 to 1FE Vendor Unique 1FF Check sum 00 Tag field Reserved 0C 0D Table 5 41 Tag field information Bit Description 0 4 6 7 If bit 7 is 0 this field has an error tag number 5 Reserved If this bit is 0 the field consisting of bit...

Page 224: ...mand failed due to an ICRC error 2 Data FIS R_ERR ending status transmitted and received 3 Data FIS R_ERR ending status transmitted 4 Data FIS R_ERR ending status received 5 Non data FIS R_ERR ending status transmitted and received 6 Non data FIS R_ERR ending status transmitted 8 Non data FIS retries transmitted Transitions from drive PhyRdy to drive PhyNRdy A Signature Device to Host Register FIS...

Page 225: ...tting CM 0 0 1 0 1 1 1 1 DH 1 L DV 1 xx CH EXP CH CL EXP xx CL SN EXP SN SC EXP SC FR EXP FR xx 00h 00h xx E0h 00h 01h xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x DV xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER xx xx xx xx xx xx xx xx Error information C141 E249 5 151 ...

Page 226: ...ing CM 0 0 1 0 1 1 1 1 DH 1 L 1 DV xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR xx xx 00h 00h xx E1h xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x DV xx CH EXP CH CL EXP CL xx SN EXP SN SC EXP SC ER xx xx xx xx xx xx xx Error information 5 152 C141 E249 ...

Page 227: ... was issued in CHS mode ST 51h ER 04h The other error reporting conditions are the same as those of the WRITE SECTOR S command At command issuance Shadow Block Registers setting contents CM 0 0 1 1 0 1 0 0 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx At command completion Shadow Blo...

Page 228: ...ed in CHS mode ST 51h ER 04h The other error reporting conditions are the same as those of the WRITE DMA command At command issuance Shadow Block Registers setting contents CM 0 0 1 1 0 1 0 1 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx At command completion Shadow Block Registers c...

Page 229: ...e command with VV 1 has not issued before the maximum address returns to the default value After power on the host can issue this command only once when VV bit 1 If this command with VV bit 1 is issued twice or more any command following the first time will result in an ID Not Found error When the SET MAX ADDRESS EXT command is executed SET MAX ADDRESS command is aborted The address value returns ...

Page 230: ...MAX LBA 39 32 SET MAX LBA 15 8 SET MAX LBA 31 24 SET MAX LBA 7 0 xx SC xx VV FR EXP FR xx xx At command completion Shadow Block Registers contents to be read ST Status information DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER SET MAX LBA 47 40 SET MAX LBA 23 16 SET MAX LBA 39 32 SET MAX LBA 15 8 SET MAX LBA 31 24 SET MAX LBA 7 0 xx xx Error information 5 156 C141 E249 ...

Page 231: ... was issued in CHS mode ST 51h ER 04h The other error reporting conditions are the same as those of the WRITE MULTIPLE command At command issuance Shadow Block Registers setting contents CM 0 0 1 1 1 0 0 1 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx At command completion Shadow Blo...

Page 232: ... the Aborted Command error occurs Error reporting conditions 1 An error was detected during power on processing ST 51h ER 04h 2 An error was detected during wake up processing in cases where wake up processing is required before execution of this command ST 51h ER 04h 3 A write fault was detected while the write cache was disabled ST 71h ER 10h 4 While the write cache is enabled if the status indi...

Page 233: ... SN EXP SN SC EXP SC FR EXP FR xx xx Sector offset 15 8 Sector offset 7 0 xx Log address Sector count 15 8 Sector count 7 0 xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER xx xx xx xx xx xx xx xx Error information C141 E249 5 159 ...

Page 234: ... CM 0 0 1 1 1 1 1 1 DH 1 L 1 DV xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR xx xx 00h 00h xx E0h 00h 01h xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x DV xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER xx xx xx xx xx xx xx xx Error information 5 160 C141 E249 ...

Page 235: ...ting CM 0 0 1 1 0 0 0 0 DH 1 L 1 DV xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR xx xx 00h 00h xx E1h xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x DV xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER xx xx xx xx xx xx xx xx Error information C141 E249 5 161 ...

Page 236: ...nd was issued in CHS mode ST 51h ER 04h The other error reporting conditions are the same as those of the READ VERIFY SECTOR S command At command issuance Shadow Block Registers setting contents CM 0 1 0 0 0 0 1 0 DH 1 L 1 x Xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx At command completion Sh...

Page 237: ...ommunication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 0 1 0 1 0 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR xx xx xx xx xx xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER xx xx xx xx xx xx xx xx Error information...

Page 238: ...the WRITE MULTIPLE EXT command At command issuance Shadow Block Registers setting contents CM 1 1 0 0 1 1 1 0 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx At command completion Shadow Block Registers contents to be read ST Status information DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP ...

Page 239: ... the WRITE DMA EXT command At command issuance Shadow Block Registers setting contents CM 0 0 1 1 1 1 0 1 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx At command completion Shadow Block Registers contents to be read ST Status information DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN S...

Page 240: ...A 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 xx SC TAG xx FR EXP FR xx xx CM At command completion Shadow Block Registers contents to be read ST Status information DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER xx xx xx xx xx xx xx xx Error information FUA If this bit is 1 the device always reads data from media regardless of whether the data requested by the host is in the cac...

Page 241: ... EXP CL SN EXP SN SC EXP LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 xx SC TAG xx FR EXP FR xx xx At command completion Shadow Block Registers contents to be read ST Status information DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER xx xx xx xx xx xx xx xx Error information FUA If this bit is 1 the device always reports the status after data is written to a medium TAG Number ...

Page 242: ...V V V V DOWNLOAD MICROCODE V V V V V STANDBY IMMEDIATE V V V V V IDLE UNLOAD IMMEDIATE V V V V V STANDBY V V V V V IDLE V V V V V CHECK POWER MODE V V V V V SLEEP V V V V V V V V V V V DEVICE CONFIGURATION V V V V V V V V V V V V V WRITE MULTIPLE V V V V V V SET MULTIPLE MODE V V V V V READ DMA V V V V V V V WRITE DMA V V V V V V READ BUFFER V V V V V FLUSH CACHE V V V V V V WRITE BUFFER V V V V V...

Page 243: ...READ NATIVE MAX ADDRESS EXT V V V V V READ MULTIPLE EXT V V V V V V V WRITE LOG EXT V V V V V V WRITE SECTOR S EXT V V V V V V WRITE DMA EXT V V V V V V SET MAX ADDRESS EXT V V V V V V WRITE MULTIPLE EXT V V V V V V READ LOG EXT V V V V V V V READ VERIFY SECTOR S EXT V V V V V V V FLUSH CACHE EXT V V V V V V WRITE MULTIPLE FUA EXT V V V V V V V V V V V V V V V V V V V WRITE FP DMA QUEUED V V V V V...

Page 244: ... this section FIS Frame Information Structure type Abbreviation Register Host to Device RegHD Register Device to Host RegDH DMA Active Device to Host DMA Active DMA Setup Device to Host or Host to Device Bidirectional DMA Setup Set Device Bits Device to Host SetDB BIST Active Bidirectional BIST Active PIO Setup Device to Host PIO Setup Data Host to Device or Device to Host Bidirectional DATA 5 4 1...

Page 245: ...S SECURITY ERASE PREPARE SECURITY FREEZE LOCK FLUSH CACHE EXT SLEEP DEVICE CONFIGRATION RESTORE FREEZE LOCK The following is the protocol for command execution without data transfer 1 The device receives a non data command with the RegHD FIS 2 The device executes the received command 4 The device reports the completion of command execution by sending to the host the RegDH FIS with 1 set in the I b...

Page 246: ...quested data is read from the last sector to be processed the device sets 0 in both the BSY bit and DRQ bit of the E_Status field Otherwise the device sets 1 in the BSY bit and 0 in the DRQ bit of the E_Status field SMART READ DATA SMATR READ LOG SECTOR DEVICE CONFIGRATION IDENTIFY Data of one or more sectors is transferred from the device to the host 2 If an error remaining in the device prevents...

Page 247: ...ves data transfers from the host system to the device WRITE SECTOR S EXT WRITE MULTI EXT FUA EXT WRITE BUFFER WRITE VERIFY SMART WRITE LOG SECTOR SECURITY DISABLE PASSWORD SECURITY UNLOCK DEVICE CONFIGRATION SET SECURITY ERASE UNIT SECURITY SET PASSWORD DOWNLOAD MICROCODE WRITE LOG EXT Data of one or more sectors is transferred from the host to the device C141 E249 5 173 ...

Page 248: ...us field of the PIO Setup FIS for a data transfer to the first sector while it sets 1 in the I bit for a data transfer to any sector other than the first sector Then it sends this FIS to the host In the E_Status field the device sets 1 in the BSY bit and 0 in the DRQ bit 5 When all data has been transferred the device sends the RegDH FIS with 1 set in the I bit to complete execution of the command...

Page 249: ...A data in command with the RegHD FIS 2 If an error remaining in the device prevents command execution the device sends the RegDH FIS with 1 set in the I bit 3 When the device is ready to send data it sends the Data FIS to the host 4 When all data has been transferred the device sends the RegDH FIS with 1 set in the I bit to complete execution of the command If any data remains to be sent by the de...

Page 250: ... The completion of the command is reported by an interruption An outline of this protocol is as follows 3 When the device is ready to receive data it sends the DMA Active FIS to the host 4 The device receives the Data FIS from the host 5 When all data has been transferred the device sends the RegDH FIS with 1 set in the I bit to complete execution of the command If any data remains to be received ...

Page 251: ...er of the READ FP DMA QUEUED command it sends to the host the DMA Setup FIS with the settings of TAG D bit 1 I bit 0 and A bit 0 and it then sends the Data FIS to the host The Data FIS is transferred in units of up to 8 KB 5 For the data transfer of the WRITE FP DMA QUEUED command if the DMA Setup Auto Activate function is disabled the device sends to the host the DMA Setup FIS with the settings o...

Page 252: ... The device reports abort for other commands 10 If the device receives the READ LOG EXT command with page 10h specified queued commands are aborted Then after the device sends to the host the SetDB FIS ERR 0 ERRReg 0 I 0 and SActive 0xFFFFFFFF it sends to the host the log data for the READ LOG EXT command with page 10h specified and reports the status of this command Next the command queuing funct...

Page 253: ...5 4 Command Protocol Device Host RegHD RegDH DMA Setup SetDB DATA DMACT Figure 5 19 WRITE FP DMA QUEUED command protocol C141 E249 5 179 ...

Page 254: ...stablished the host sets 0xFFh in the Status field of the Shadow Block Register The device completes the power on sequence within 10 ms so that communication with the SATA interface can be established Device TX Host RX Host TX Device RX Host power on Host ComReset Host releases ComReset Host calibrate Host ComWake Host releases ComWake Host Align Host data Device ComInit Device releases ComInit De...

Page 255: ...Host device on Host ComReset Host releases ComReset Host calibrate Host ComWake Host releases ComWake Host Align Host data Device ComInit Device releases ComInit Device Calibrate Device ComWake Device Align Device data Figure 5 21 COMRESET sequence C141 E249 5 181 ...

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Page 257: ...Operations 6 1 Reset and Diagnosis 6 2 Power Save 6 3 Power Save Controlled by Interface Power Management IPM 6 4 Read ahead Cache 6 5 Write Cache This chapter explains each of the above operations C141 E249 6 1 ...

Page 258: ...ication with the SATA interface is established the host sets 0xFFh in the Status field of the Shadow Block The device establishes communication with the SATA interface PHY Ready within 10 ms The device sends the FIS STS 50h to notify the host that the device is ready Note Figure 6 1 assumes that power is turned on after the power off state continued for more than five seconds Figure 6 1 Response t...

Page 259: ...6 1 Reset and Diagnosis Figure 6 2 Response to power on when the device is powered on earlier than the host C141 E249 6 3 ...

Page 260: ...e when power is turned on and a power on reset is then cancelled The device establishes communication with the SATA interface PHY Ready and sends the RegDH FIS STS 50h to notify the host that the device is ready Then the COMRESET sequence is completed Figure 6 3 Response to COMRESET 6 4 C141 E249 ...

Page 261: ...fer to Section 5 3 2 28 If a device supports software settings preservation the feature shall be enabled by default 6 1 2 2 COMRESET preservation requirements The software settings that shall be preserved across COMRESET are listed below The device is only required to preserve the indicated software setting if it supports the particular feature command the setting is associated with INITIALIZE DEV...

Page 262: ...ment enable disable setting established by the SET FEATURES command with subcommand code of 05h or 85h The advanced power management level established in the Sector Count field when advanced power management is enabled SET FEATURES subcommand code 05h shall also be preserved SET FEATURES Read Look Ahead The read look ahead enable disable setting established by the SET FEATURES command with subcomm...

Page 263: ...reset When a software reset is accepted the device performs a self diagnosis and it sends the RegDH FIS STS 50h to notify the host that the device is ready Then the software reset sequence is completed Figure 6 4 Response to a software reset C141 E249 6 7 ...

Page 264: ...mode all the electric circuit in the device are active or the device is under seek read or write operation A device enters the active mode under the following conditions The media access system is received 2 Active idle mode In this mode circuits on the device is set to power save mode The device enters the Active idle mode under the following conditions After completion of the command execution o...

Page 265: ... the low power idle state APM Mode 2 The time specified by the STANDBY or IDLE command has elapsed after completion of the command A reset is issued in the sleep mode When one of following commands is issued the command is executed normally and the device is still stayed in the standby mode Reset hardware or software STANDBY command STANDBY IMMEDIATE command INITIALIZE DEVICE PARAMETERS command CH...

Page 266: ...Operations 6 2 2 Power commands The following commands are available as power commands IDLE IDLE IMMEDIATE STANDBY STANDBY IMMEDIATE SLEEP CHECK POWER MODE SET FEATURES APM setting 6 10 C141 E249 ...

Page 267: ...ich the device must switch to Active mode from the Interface Power Down state Period in which the device must switch to Active mode Partial mode Maximum 10 µs Slumber mode Maximum 10 ms 1 Active mode The interface is in the Active state and commands can be accepted 2 Partial mode In this mode shallow Power Save mode is set for the interface circuit The device switches to Partial mode when the foll...

Page 268: ...h the PMACK signal The device sends the PMREQ_S signal and the host responds with PMACK signal The device cannot switch to Slumber mode if the following condition is satisfied The device responds with the PMNAK signal because it is not waiting for commands The device returns to Active mode from Slumber mode when the following condition is satisfied The device receives the COMRESET or ComWake signa...

Page 269: ...ccessing the disk media As the result faster data access becomes possible for the host 6 4 1 Data buffer structure This device contains a data buffer This buffer is divided into two areas one area is used for MPU work and the other is used as a read cache for another command See Figure 6 5 Example of 8 MB buffer For MPU work For R W command 8 192 KB 8 388 608 bytes Figure 6 5 Data buffer structure...

Page 270: ...nction is prohibited by the SET FEATURES command the caching operation is not performed 2 Data that is a target of caching The data that is a target of caching are as follows 1 Read ahead data that is read from disk media and saved to the data buffer upon completion of execution of a command that is a target of caching 2 Pre read data that is read from disk media and saved to the data buffer befor...

Page 271: ...RES SECURITY ERASE UNIT DEVICE CONFIGURATION DOWNLOAD MICROCODE UNSUPPORT COMMAND INVALID COMMAND 1 2Commands that partially invalidate caching data READ DMA READ MULTIPLE READ SECTOR S READ DMA EXT READ MULTIPLE EXT READ SECTOR S EXT READ FP DMA QUEUED WRITE DMA WRITE MULTIPLE WRITE SECTOR S WRITE DMA EXT WRITE MULTIPLE EXT WRITE SECTOR S EXT WRITE DMA FUA EXT WRITE MULTIPLE FUA EXT WRITE FP DMA ...

Page 272: ...e requested data reading position Read segment HAP host address pointer DAP disk address pointer 2 During reading of read requested data the request data that has already been read is sent to the host system Read requested data Free space HAP DAP Read requested data is stored until this point 3 When reading of read requested data is completed and transfer of the read requested data to the host sys...

Page 273: ...d data DAP disk address pointer HAP host address pointer 2 During reading of read requested data the request data that has already been read is sent to the host system Cache valid data Free space Read requested data DAP disk address pointer HAP host address pointer 3 When reading of read requested data is completed and transfer of the read requested data to the host system is completed the read ah...

Page 274: ...during the read ahead operation a transfer of the read requested data starts while the read ahead operation is in progress 1 An example is the state shown below where the previous read command is executing sequential reading First HAP is set at the location where hit data is stored HAP It is reset to the hit data location for transfers HAP end location of the previous read command DAP end location...

Page 275: ...T LBA LAST LBA 1 HAP is set at the address where partial hit data is stored and Transfer is started Cache valid data Partial hit data HAP host address pointer 2 DAP and HAP are set at the head of Buffer newly allocated and insufficient data is read Read segment HAP host address pointer DAP disk address pointer 3 When reading the read requested data ends and the transmission of the read requested d...

Page 276: ...aching function is prohibited by the SET FEATURES command 2 Invalidation of cached data If an error occurs during writing onto media write processing is repeated up to as many times as specified for retry processing If retry fails for a sector because the retry limit is reached automatic alternate sector processing is executed for the sector If the automatic alternate sector processing fails the d...

Page 277: ...re reset is received while cached data is stored on the data buffer data of the data buffer is written on the media and reset processing is then performed This is true for both a hard reset and soft reset 6 Cashing function when power supply is turned on The cashing function is invalid until Calibration is done after the power supply is turned on about 10 sec It is effective in Default after that ...

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Page 279: ...s The BIOS of a PC AT cannot make full use of the physical specifications of these drivers To make the best use of these drives a BIOS that can handle the standard parameters of these drives is required Command Commands are instructions to input data to and output data from a drive Commands are written in command registers Connector Connector Plug Host system side It means a host receptacle descri...

Page 280: ...he average time required for a service person to diagnose and repair a faulty drive PIO Programmed input output Mode to transfer data under control of the host CPU Positioning Sum of the seek time and mean rotational delay Power save mode The power save modes are idle mode standby mode and sleep mode In idle mode the drive is neither reading writing nor seeking data In standby mode the spindle mot...

Page 281: ...r in Serial ATA for obtaining greater data transfer speed Slave Device 1 The slave is a second drive that can operate on the AT bus The slave is daisy chained with the first drive operating in conformity with the ATA standard Status The status is a piece of one byte information posted from the drive to the host when command execution is ended The status indicates the command termination state VCM ...

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Page 283: ...t E ECC Error checking and correction ER Error field ERR Error EU European Union F FR Feature field H HA Host adapter HDD Hard disk drive I IDNF ID not found IRQ14 Interrupt request 14 L LED Light emitting diode M MB Mega byte MB S Mega byte per seconds MPU Micro processor unit P PCA Printed circuit assembly PIO Programmed input output R RLL Run length limited RoHS The Restrictions of the use of c...

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Page 285: ...and code and parameter 5 29 attribute ID 5 61 command data structure 5 67 attribute value command description 5 32 current 5 62 command execution status after 5 24 raw 5 62 command field 5 28 worst case 5 62 command for caching 6 14 6 20 automatic acoustic management 5 125 command processing during self calibration 4 9 average positioning time 1 2 command protocol 5 170 B DMA data in 5 175 BIST ac...

Page 286: ...5 71 dimension 3 2 cylinder high field 5 26 DIPM 1 15 cylinder low field 5 25 disk 2 2 4 2 D disk drive outerview 2 2 disk enclosure 2 2 D A converter DAC 4 14 DMA active device to host 5 18 data host to device or device to host bidirectional 5 21 DMA buffer offset field 5 28 DMA data in command protocol 5 175 data area 4 15 DMA data out command protocol 5 176 data assurance in the event of power ...

Page 287: ...ost initiated power management 02h 5 140 interface 1 15 03h 5 141 hot plug 5 13 04h 5 142 C0h 5 86 I C1h 5 86 ID attribute 5 61 C2h 5 87 identifier and security level relationship between 5 125 5 126 C3h 5 87 features field value 5 119 IDENTIFY DEVICE 5 104 filter IDENTIFY DEVICE command information to be read by 5 106 circulation 2 2 FIR circuit 4 12 IDENTIFY DEVICE DMA 5 105 FIS type 5 17 IDLE 5...

Page 288: ...rocode data example of rewriting 5 46 physical sector servo configuration on disk surface 4 16 microprocessor unit MPU 4 14 miss hit 6 16 pinout connector 5 10 mode PIO data in command protocol 5 172 5 173 active 6 8 6 11 active idle 6 8 PIO data out command protocol 5 173 5 174 low power idle 6 8 partial 6 11 PIO setup device to host 5 21 power save 6 8 positioning error 1 12 settable 5 119 post ...

Page 289: ...x 5 69 READ SECTOR S 5 34 self test number 5 69 read segment buffer using 6 16 sensing and compensating for external force 4 8 READ VERIFY SECTOR S EXT 5 162 READ VERIFY SECTOR S 5 40 sequential hit 6 17 read write circuit 2 3 4 3 4 10 serial ATA function 5 124 read write circuit block diagram 4 10 service area 3 7 read write preamplifier PreAMP 4 10 service life 1 11 read ahead cache 6 13 servo b...

Page 290: ...5 24 status field 5 27 status flag 5 62 status report on error occurrence 6 21 status off line data collection 5 62 structure data buffer 6 13 subassembly 4 2 subcommand 5 56 surface temperature measurement point 3 6 surface temperature standard value 3 6 system configuration 2 3 T tag field information 5 149 5 150 temperature range 1 2 temperature ambient 3 6 test span 5 70 theory of device opera...

Page 291: ... Poor General appearance Technical level Organization Clarity Accuracy Illustration Glossary Acronyms Abbreviations Index Comments Suggestions List any errors or suggestions for improvement Page Line Contents Please send this form to the address below We will use your comments in planning future editions Address Fujitsu Learning Media Limited 37 10 Nishikamata 7 chome Oota ku Tokyo 144 0051 JAPAN ...

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Page 293: ...MHW2120BS MHW2100BS MHW2080BS MHW2060BS MHW2040BS DISK DRIVES PRODUCT MANUAL C141 E249 01EN MHW2120BS MHW2100BS MHW2080BS MHW2060BS MHW2040BS DISK DRIVES PRODUCT MANUAL C141 E249 01EN ...

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