Interface
f) When the command execution is completed, the device clears both BSY and
DRQ bits and asserts the INTRQ signal. Then, the host reads the Status
register.
g) The host resets the DMA channel.
Figure 5.7 shows the correct DMA data transfer protocol.
g
d
f
f
d
e
Figure 5.7 Normal DMA data transfer
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Summary of Contents for MHW2040AT - Mobile 40 GB Hard Drive
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