Fujitsu MHW2040AT - Mobile 40 GB Hard Drive, Product Manual, Page: 39 / 278

Share

Page: 39 / 278

Fujitsu MHW2040AT - Mobile 40 GB Hard Drive Product Manual Download Page 39

2.2 System Configuration

(6) Read/write circuit

The read/write circuit uses a LSI chip for the read/write preamplifier. It improves
data reliability by preventing errors caused by external noise.

(7) Controller circuit

The controller circuit consists of an LSI chip to improve reliability. The high-
speed microprocessor unit (MPU) achieves a high-performance AT controller.

2.2 System Configuration

2.2.1 ATA interface

Figures 2.2 and 2.3 show the ATA interface system configuration. The drive has a
44pin PC AT interface connector and supports PIO mode 4 transfer at 16.6 MB/s,
Multiword DMA mode 2 transfer at 16.6 MB/s and also U-DMA mode 5 (100
MB/s).

2.2.2 1 drive connection

MHW2080AT
MHW2060AT
MHW2040AT

Figure 2.2 1 drive system configuration

C141-E250

2-3

«
...
37
38
39
40
41
...
»

Summary of Contents for MHW2040AT - Mobile 40 GB Hard Drive

Page 1: ...C141 E250 01EN MHW2080AT MHW2060AT MHW2040AT DISK DRIVES PRODUCT MANUAL ...

Page 2: ...ncidental or consequential damages arising therefrom FUJITSU DISCLAIMS ALL WARRANTIES REGARDING THE INFORMATION CONTAINED HEREIN WHETHER EXPRESSED IMPLIED OR STATUTORY FUJITSU reserves the right to make changes to any products described herein without further notice and without obligation This product is designed and manufactured for use in standard applications such as office work personal device...

Page 3: ...Revision History 1 1 Edition Date Revised section 1 Added Deleted Altered Details 01 2006 08 31 1 Section s with asterisk refer to the previous edition when those were deleted C141 E250 ...

Page 4: ...This page is intentionally left blank ...

Page 5: ...gives an overview of the disk drive and describes their features CHAPTER 2 Device Configuration This chapter describes the internal configurations of the disk drive and the configuration of the systems in which they operate CHAPTER 3 Installation Conditions This chapter describes the external dimensions installation conditions and switch settings of the disk drive CHAPTER 4 Theory of Device Operat...

Page 6: ...e alert signal is centered followed below by the indented message A wider line space precedes and follows the alert message to show where the alert message begins and ends The following is an example Example Data corruption Avoid mounting the disk drive near strong magnetic sources such as loud speakers Ensure that the disk drive is not affected by external magnetic fields The main alert messages ...

Page 7: ... this manual and forward it to the address described in the sheet Liability Exception Disk drive defects refers to defects that involve adjustment repair or replacement Fujitsu is not liable for any other disk drive defects such as those caused by user misoperation or mishandling inappropriate operating environments defects in the power supply or cable problems of the host system or other causes o...

Page 8: ...This page is intentionally left blank ...

Page 9: ...ge Do not press the cover of the disk drive Pressing it too hard the cover and the spindle motor contact which may cause damage to the disk drive Static When handling the device disconnect the body ground 500 kΩ or greater Do not touch the printed circuit board but hold it by the edges 3 6 Damage Interface cable connection Take note of the following precaution about plugging an interface cable soc...

Page 10: ...This page is intentionally left blank ...

Page 11: ...L C141 E250 This manual Device Overview Device Configuration Installation Conditions Theory of Device Operation Interface Operations MHW2080AT MHW2060AT MHW2040AT DISK DRIVES MAINTENANCE MANUAL C141 F084 Maintenance and Diagnosis Removal and Replacement Procedure C141 E250 vii ...

Page 12: ...This page is intentionally left blank ...

Page 13: ... Requirements 1 6 1 4 Environmental Specifications 1 9 1 5 Acoustic Noise 1 10 1 6 Shock and Vibration 1 10 1 7 Reliability 1 11 1 8 Error Rate 1 12 1 9 Media Defects 1 12 1 10 Load Unload Function 1 12 1 10 1 Recommended power off sequence 1 13 1 11 Advanced Power Management APM 1 13 CHAPTER 2 Device Configuration 2 1 2 1 Device Configuration 2 2 2 2 System Configuration 2 3 2 2 1 ATA interface 2...

Page 14: ...rs 3 10 3 4 2 Factory default setting 3 11 3 4 3 Master drive slave drive setting 3 11 3 4 4 CSEL setting 3 12 3 4 5 Power up in standby setting 3 13 CHAPTER 4 Theory of Device Operation 4 1 4 1 Outline 4 2 4 2 Subassemblies 4 2 4 2 1 Disk 4 2 4 2 2 Spindle 4 2 4 2 3 Actuator 4 2 4 2 4 Air filter 4 3 4 3 Circuit Configuration 4 3 4 4 Power on Sequence 4 6 4 5 Self calibration 4 7 4 5 1 Self calibr...

Page 15: ...als 5 2 5 1 2 Signal assignment on the connector 5 3 5 2 Logical Interface 5 6 5 2 1 I O registers 5 7 5 2 2 Command block registers 5 8 5 2 3 Control block registers 5 13 5 3 Host Commands 5 14 5 3 1 Command code and parameters 5 14 5 3 2 Command descriptions 5 18 1 RECALIBRATE X 10 to X 1F 5 20 2 READ SECTOR S X 20 or X 21 5 21 3 WRITE SECTOR S X 30 or X 31 5 23 4 WRITE VERIFY X 3C 5 25 5 READ V...

Page 16: ...27 IDENTIFY DEVICE DMA X EE 5 77 28 SET FEATURES X EF 5 89 29 SECURITY SET PASSWORD X F1 5 93 30 SECURITY UNLOCK X F2 5 95 31 SECURITY ERASE PREPARE X F3 5 97 32 SECURITY ERASE UNIT X F4 5 98 33 SECURITY FREEZE LOCK X F5 5 99 34 SECURITY DISABLE PASSWORD X F6 5 101 35 READ NATIVE MAX ADDRESS X F8 5 103 36 SET MAX X F9 5 104 37 READ SECTOR S EXT X 24 Option customizing 5 110 38 READ DMA EXT X 25 Op...

Page 17: ...host 5 129 5 4 2 PIO Data transferring commands from host to device 5 132 5 4 3 Commands without data transfer 5 134 5 4 4 Other commands 5 135 5 4 5 DMA data transfer commands 5 135 5 5 Ultra DMA Feature Set 5 137 5 5 1 Overview 5 137 5 5 2 Phases of operation 5 138 5 5 3 Ultra DMA data in commands 5 138 5 5 4 Ultra DMA data out commands 5 143 5 5 5 Ultra DMA CRC rules 5 147 5 5 6 Series terminat...

Page 18: ...2 2 Power commands 6 9 6 3 Defect Processing 6 9 6 3 1 Spare area 6 9 6 3 2 Alternating processing for defective sectors 6 10 6 4 Read ahead Cache 6 12 6 4 1 DATA buffer structure 6 12 6 4 2 Caching operation 6 13 6 4 3 Using the read segment buffer 6 15 6 5 Write Cache 6 19 6 5 1 Cache operation 6 19 Glossary GL 1 Acronyms and Abbreviations AB 1 Index IN 1 xiv C141 E250 ...

Page 19: ... 3 7 Figure 3 7 Connector locations 3 8 Figure 3 8 Cable connections 3 9 Figure 3 9 Power supply connector pins CN1 3 10 Figure 3 10 Jumper location 3 10 Figure 3 11 Factory default setting 3 11 Figure 3 12 Jumper setting of master or slave drive 3 11 Figure 3 13 CSEL setting 3 12 Figure 3 14 Example 1 of cable select 3 12 Figure 3 15 Example 2 of cable select 3 13 Figure 4 1 Power supply configur...

Page 20: ...55 Figure 5 13 Host pausing an Ultra DMA data in burst 5 156 Figure 5 14 Device terminating an Ultra DMA data in burst 5 157 Figure 5 15 Host terminating an Ultra DMA data in burst 5 158 Figure 5 16 Initiating an Ultra DMA data out burst 5 159 Figure 5 17 Sustained Ultra DMA data out burst 5 160 Figure 5 18 Device pausing an Ultra DMA data out burst 5 161 Figure 5 19 Host terminating an Ultra DMA ...

Page 21: ...value data 5 46 Table 5 9 Format of insurance failure threshold value data 5 46 Table 5 10 Off line data collection status 5 49 Table 5 11 Self test execution status 5 49 Table 5 12 Off line data collection capability 5 50 Table 5 13 Failure prediction capability flag 5 50 Table 5 14 Error logging capability 5 51 Table 5 15 Log directory data format 5 51 Table 5 16 Data format of SMART Summary Err...

Page 22: ...le 5 27 Command code and parameters 5 127 Table 5 28 Recommended series termination for Ultra DMA 5 148 Table 5 29 Ultra DMA data burst timing requirements 5 152 Table 5 30 Ultra DMA sender and recipient timing requirements 5 154 ...

Page 23: ... 1 8 Error Rate 1 9 Media Defects 1 10 Load Unload Function 1 11 Advanced Power Management APM Overview and features are described in this chapter and specifications and power requirement are described The disk drive is 2 5 inch hard disk drives with built in disk controllers These disk drives use the AT bus hard disk interface protocol and are compact and reliable C141 E250 1 1 ...

Page 24: ...ve has a formatted capacity of 80 GB MHW2080AT 60 GB MHW2060AT and 40 GB MHW2040AT respectively 4 High speed Transfer rate The disk drive the MHW Series has an internal data rate up to 56 4 MB s The disk drive supports an external data rate up to 100 MB s U DMA mode 5 5 Average positioning time Use of a rotary voice coil motor in the head positioning mechanism greatly increases the positioning spe...

Page 25: ...ad ahead cache system After the execution of a disk read command the disk drive automatically reads the subsequent data block and writes it to the data buffer read ahead operation This cache system enables fast data access The next disk read command would normally cause another disk access But if the read ahead data corresponds to the data requested by the next read command the data in the buffer ...

Page 26: ...of Sectors User 156 301 488 117 210 240 78 140 160 Bytes per Sector 512 bytes Rotational Speed 4 200 rpm 1 Average Latency 7 14 ms Positioning time read and seek Minimum Track Track Average Maximum Full 1 5 ms typ Read 12ms typ 22 ms typ Start time 3 5 sec typ Interface ATA 6 ATA 7 Max Cable length 18inches 0 46 m equipped with expansion function Data Transfer Rate 1 To From Media To From Host 56 ...

Page 27: ...Table 1 2 lists the model names and product numbers of the disk drive The model name does not necessarily correspond to the product number as listed in Table 1 2 since some models have been customized and have specifications that are different from those for the standard model If a disk drive is ordered as a replacement drive the product number must be the same as that of the drive being replaced ...

Page 28: ...re shows the restriction of the slope which is 5 V input voltage at rise The permissible range of 5 V slope is from 1V 20 µsec to 1V 20 msec under the voltage range is between 2 0 V and 4 5 V V T The slope limitation refers only to this range Input Voltage V Time sec 0V 2 0V 4 5V Slope S V T V sec S 1V 20us to 1V 20ms Figure 1 1 Permissible range of 5V rise slope 1 6 C141 E250 ...

Page 29: ...re isn t to occur at 5 V when power is turned off and a thing with no ringing Permissible level 0 2 V Voltage V 5 0 100 200 300 400 500 600 700 800 Time ms 4 3 2 1 0 1 Figure 1 2 The example of negative voltage waveform at 5 V when power is turned off C141 E250 1 7 ...

Page 30: ...k D MHW2080AT 0 0083 W GB rank D MHW2060AT 0 0125 W GB rank D MHW2040AT 1 Maximum current at starting spindle motor 2 Current and power level when the operation command that accompanies a transfer of 63 sectors is executed 3 times in 100 ms 3 Power requirements reflect typical values for 5 V power 4 Energy efficiency based on the Law concerning the Rational Use of Energy indicates the value obtain...

Page 31: ...ions Table 1 4 Environmental specifications Item Specification Temperature Operating Non operating Thermal Gradient 5 C to 55 C ambient 5 C to 60 C disk enclosure surface 40 C to 65 C 20 C h or less Humidity Operating Non operating Maximum Wet Bulb 8 to 90 RH Non condensing 5 to 95 RH Non condensing 29 C Operating 40 C Non operating Altitude relative to sea level Operating Non operating 300 to 3 0...

Page 32: ...the shock and vibration specification Table 1 6 Shock and vibration specification Item Specification Vibration Swept sine 1 4 octave per minute Operating 5 to 500 Hz 9 8m s 2 0 peak 1G 0 peak without non recovered errors Non operating 5 to 500 Hz 49m s 2 0 peak 5G 0 peak no damage Shock half sine pulse Operating 2940 m s 2 0 peak 300G 0 peak 2ms duration without non recovered errors Non operating ...

Page 33: ...TR The mean time to repair MTTR is 30 minutes or less if repaired by a specialist maintenance staff member 3 Service life In situations where management and handling are correct the disk drive requires no overhaul for five years when the DE surface temperature is less than 48 C When the DE surface temperature exceeds 48 C the disk drives requires no overhaul for five years or 20 000 hours of opera...

Page 34: ...try shall occur no more than 10 times in 10 7 seek operations 1 9 Media Defects Defective sectors are replaced with alternates when the disk drive is formatted prior to shipment from the factory low level format Thus the hosts see a defect free device Alternate sectors are automatically accessed by the disk drive The user need not be concerned with access to alternate sectors 1 10 Load Unload Func...

Page 35: ...lush Flush Cache command execution 2 Head Unload Standby Immediate command execution 3 Wait Status Checking whether bit 7 of the status register was set to 0 wait to complete STANDBY IMMEDIATE command 4 HDD power supply cutting 1 11 Advanced Power Management APM The disk drive automatically shifts to the power saving mode according to the setting of the APM mode under the idle condition The APM mo...

Page 36: ...D is waiting for commands has been exceeded Mode 0 Mode shifts from Active condition to Active Idle in 0 2 1 2 and to Low Power Idle in 15 minutes Mode 1 Mode shifts from Active condition to Active Idle in 0 1 0 2 seconds and to Low Power Idle in 10 0 27 5 seconds Mode 2 Mode shifts from Active condition to Active Idle in 0 1 0 2 seconds and to Low Power Idle in 10 0 27 5 seconds After 10 0 40 0 s...

Page 37: ...ice Configuration 2 1 Device Configuration 2 2 System Configuration This chapter describes the internal configurations of the hard disk drives and the configuration of the systems in which they operate C141 E250 2 1 ...

Page 38: ...less DC motor 4 Actuator The actuator uses a revolving voice coil motor VCM structure which consumes low power and generates very little heat The head assembly at the edge of the actuator arm is controlled and positioned by feedback of the servo information read by the read write head If the power is not on or if the spindle motor is stopped the head assembly stays on the ramp out of the disk and ...

Page 39: ...iability The high speed microprocessor unit MPU achieves a high performance AT controller 2 2 System Configuration 2 2 1 ATA interface Figures 2 2 and 2 3 show the ATA interface system configuration The drive has a 44pin PC AT interface connector and supports PIO mode 4 transfer at 16 6 MB s Multiword DMA mode 2 transfer at 16 6 MB s and also U DMA mode 5 100 MB s 2 2 2 1 drive connection MHW2080A...

Page 40: ...he ATA 6 ATA 7 interface At high speed data transfer PIO mode 4 or DMA mode 2 U DMA mode 5 occurrence of ringing or crosstalk of the signal lines AT bus between the HA and the disk drive may be a great cause of the obstruction of system reliability Thus it is necessary that the capacitance of the signal lines including the HA and cable does not exceed the ATA 6 ATA 7 standard and the cable length ...

Page 41: ... chapter gives the external dimensions installation conditions surface temperature conditions cable connections and switch settings of the hard disk drives For information about handling this hard disk drive and the system installation procedure refer to the following Integration Guide C141 E144 C141 E250 3 1 ...

Page 42: ...Installation Conditions 3 1 Dimensions Figure 3 1 illustrates the dimensions of the disk drive and positions of the mounting screw holes All dimensions are in mm Figure 3 1 Dimensions 3 2 C141 E250 ...

Page 43: ...on in Figure 3 2 The tightening torque must be 0 49N m 5kgf cm When attaching the HDD to the system frame do not allow the system frame to touch parts cover and base other than parts to which the HDD is attached 3 Limitation of mounting Note These dimensions are recommended values if it is not possible to satisfy them contact us Side surface mounting 2 5 2 5 Bottom surface mounting 2 5 DE 2 5 2 B ...

Page 44: ...er hole mounted to the HDD do not allow this to close during mounting Locating of breather hole is shown as Figure 3 3 For breather hole of Figure 3 3 at least do not allow its around φ 3 to block Figure 3 3 Location of breather 3 4 C141 E250 ...

Page 45: ...erature from exceeding 60 C Provide air circulation in the cabinet such that the PCA side in particular receives sufficient cooling To check the cooling efficiency measure the surface temperatures of the DE Regardless of the ambient temperature this surface temperature must meet the standards listed in Table 3 1 Figure 3 4 shows the temperature measurement point 1 Figure 3 4 Surface temperature me...

Page 46: ...s loud speakers Ensure that the disk drive is not affected by external magnetic fields Damage Do not press the cover of the disk drive Pressing it too hard the cover and the spindle motor contact which may cause damage to the disk drive Static When handling the device disconnect the body ground 500 kΩ or greater Do not touch the printed circuit board but hold it by the edges 6 Handling cautions Pl...

Page 47: ... falling down Do not drop Figure 3 6 Handling cautions Installation 1 Please use the driver of a low impact when you use an electric driver HDD is occasionally damaged by the impact of the driver 2 Please observe the tightening torque of the screw strictly M3 0 49N m 5 kgf cm Recommended equipments Contents Model Maker Wrist strap JX 1200 3056 8 SUMITOMO 3M ESD ESD mat SKY 8A Color Seiden Mat Achi...

Page 48: ...3 1 Device connector The disk drive has the connectors and terminals listed below for connecting external devices Figure 3 7 shows the locations of these connectors and terminals Connector setting pins PCA Figure 3 7 Connector locations 3 8 C141 E250 ...

Page 49: ...bon cables and not for cables carrying differential signals 3 3 3 Device connection Figure 3 8 shows how to connect the devices Host system DC Power supply Disk Drive 0 Disk Drive 1 ATA cable ATA cable Power supply cable Figure 3 8 Cable connections Damage Interface cable connection Take note of the following precaution about plugging an interface cable socket into the interface connector of the d...

Page 50: ... pin assignment of the power supply connector CN1 Figure 3 9 Power supply connector pins CN1 3 4 Jumper Settings 3 4 1 Location of setting jumpers Figure 3 10 shows the location of the jumpers to select drive configuration and functions Figure 3 10 Jumper location 3 10 C141 E250 ...

Page 51: ...n Figure 3 11 Factory default setting 3 4 3 Master drive slave drive setting Master drive disk drive 0 or slave drive disk drive 1 is selected b Slave drive a Master drive Open Open Short Open A 1 C B D 2 B D 2 A C 1 Figure 3 12 Jumper setting of master or slave drive Note Pins A and C should be open C141 E250 3 11 ...

Page 52: ... interface cables By connecting the CSEL of the master drive to the CSEL Line conducer of the cable and connecting it to ground further the CSEL is set to low level The drive is identified as a master drive At this time the CSEL of the slave drive does not have a conductor Thus since the slave drive is not connected to the CSEL conductor the CSEL is set to high level The drive is identified as a s...

Page 53: ...3 4 Jumper Settings drive drive Figure 3 15 Example 2 of cable select 3 4 5 Power up in standby setting When pin C is grounded the drive does not spin up at power on C141 E250 3 13 ...

Page 54: ...This page is intentionally left blank ...

Page 55: ...guration 4 4 Power on Sequence 4 5 Self calibration 4 6 Read write Circuit 4 7 Servo Control This chapter explains basic design concepts of the disk drive Also this chapter explains subassemblies of the disk drive each sequence servo control and electrical circuit blocks C141 E250 4 1 ...

Page 56: ...n outer diameter of 65 mm and an inner diameter of 20 mm Servo data is recorded on each cylinder total 172 Servo data written at factory is read out by the read head For servo data see Section 4 7 4 2 2 Spindle The spindle consists of a disk stack assembly and spindle motor The disk stack assembly is activated by the direct drive sensor less DC spindle motor which has a speed of 4 200 rpm 1 The sp...

Page 57: ... PreAMP consists of the write current switch circuit that flows the write current to the head coil and the voltage amplifier circuit that amplitudes the read output from the head The RDC is the read demodulation circuit using the Modified Extended Partial Response MEEPR and contains the Viterbi detector programmable filter adaptable transversal filter times base generator data separator circuits R...

Page 58: ...ata transfer control Data buffer management Sector format control Defect management ECC control Error recovery and self diagnosis S DRAM SVC 3 3V Generator Circuit 1 2V Generator Circuit MCU HDC RDC Integration 3V Generator Circuit PreAMP 5 0V 3 3V 3 0V 1 2V Figure 4 1 Power supply configuration 4 4 C141 E250 ...

Page 59: ...Circuit Configuration C141 E250 4 5 MCU HDC RDC HDC MCU RDC Data Buffer SDRAM SVC Resonator R W Pre Amp Thermistor VCM HEAD SP Motor Media DE PCA ATA Interface Shock Sensor Figure 4 2 Circuit configuration ...

Page 60: ...ad assembly is loaded on the disk d The disk drive positions the heads onto the SA area and reads out the system information e The drive becomes ready The host can issue commands f The disk drive executes self calibration This collects data for VCM torque and mechanical external forces applied to the actuator and updates the calibrating value End d Initial on track and read out of system informati...

Page 61: ...n The measured values are stored in the SA cylinder In the self calibration the compensating value is updated using the value in the SA cylinder 2 Compensating open loop gain Torque constant value of the VCM has dispersion for each drive and varies depending on the cylinder that the head is positioned To realize the high speed seek operation the value that compensates torque constant value change ...

Page 62: ...he error rate of data reading writing or seeking becomes lower than the specified value 4 5 3 Command processing during self calibration This enables the host to execute the command without waiting for a long time even when the disk drive is performing self calibration The command execution wait time is about maximum 72 ms When the error rate of data reading writing or seeking becomes lower than t...

Page 63: ... Each channel is connected to each data head and PreAMP switches channel by serial I O In the event of any abnormalities including a head short circuit or head open circuit the write unsafe signal is generated so that abnormal write does not occur 4 6 2 Write circuit The write data is output from the hard disk controller HDC and sent to the RDC The write data is sent to the PreAMP as differential ...

Page 64: ...amplifier output is maintained at a constant level even when the head output fluctuates due to the head characteristics or outer inner head positions 2 Programmable filter circuit The programmable filter circuit has a low pass filter function that eliminates unnecessary high frequency noise component and a high frequency boost up function that equalizes the waveform of the read signal Cut off freq...

Page 65: ...ates data according to the survivor path sequence 4 6 4 Digital PLL circuit The drive uses constant density recording to increase total capacity This is different from the conventional method of recording data with a fixed data transfer rate at all data area In the constant density recording method data area is divided into zones by radius and the data transfer rate is set so that the recording de...

Page 66: ...ontrolled according to the servo data that is written on the data side beforehand 4 7 1 Servo control circuit Figure 4 6 is the block diagram of the servo control circuit The following describes the functions of the blocks MPU HDC RDC Head Spindle motor CSR VCM Position Sense VCM current CSR Current Sense Resister VCM Voice Coil Motor 1 2 Servo burst capture 3 DAC 4 SVC Power Amp 5 Spindle motor c...

Page 67: ... head position from the servo data on the data surface From the servo area on the data area surface via the data head the burst signals of EVEN1 ODD EVEN2 are output as shown in Figure 4 8 in subsequent to the servo mark gray code that indicates the cylinder position and index information The servo signals do A D convert by Fourier demodulator in the servo burst capture circuit At that time the AG...

Page 68: ...plitude circuit that receives signals from the spindle motor control circuit and feeds currents to the spindle motor 7 VCM current sense resistor CSR This resistor controls current at the power amplifier by converting the VCM current into voltage and feeding back 4 14 C141 E250 ...

Page 69: ...rd band This area is located inside the user area and the rotational speed of the VCM can be controlled on this cylinder area for head moving 2 Data area This area is used as the user data area SA area 3 Outer guard band This area is located at outer position of the user data area and the rotational speed of the spindle can be controlled on this cylinder area for head moving C141 E250 4 15 ...

Page 70: ...o frame 172 servo frames per revolution CYLn 1 CYLn CYLn 1 n even number W R Recovery Servo Mark Gray Code W R Recovery Servo Mark Gray Code W R Recovery Servo Mark Gray Code EVEN1 ODD EVEN2 Post code PAD Diameter direction Figure 4 7 Physical sector servo configuration on disk surface 4 16 C141 E250 ...

Page 71: ...d recovery This area is used to absorb the write read transient and to stabilize the AGC 2 Servo mark This area generates a timing for demodulating the gray code and position demodulating the burst signal by detecting the servo mark 3 Gray code including sector address bits This area is used as cylinder address The data in this area is converted into the binary data by the gray code demodulation c...

Page 72: ...e head is stopped at the reference cylinder from there Track following control starts 2 Seek operation Upon a data read write request from the host the MPU confirms the necessity of access to the disk If a read write instruction is issued the MPU seeks the desired track The MPU feeds the VCM current via the D A converter and power amplifier to move the head The MPU calculates the difference speed ...

Page 73: ...phase W phase to U phase W phase to V phase U phase to V phase U phase to W phase and V phase to W phase after that repeating this order The above operations mean the generation of rotational magnetic field d During phase switching the spindle motor starts rotating in low speed and generates a back electromotive force The SVC detects this back electromotive force and reports to the MPU using a PHA...

Page 74: ...This page is intentionally left blank ...

Page 75: ... 5 1 Physical Interface 5 2 Logical Interface 5 3 Host Commands 5 4 Command Protocol 5 5 Ultra DMA Feature Set 5 6 Timing This chapter gives details about the interface and the interface commands and timings C141 E250 5 1 ...

Page 76: ...G ULTRA DMA DATA BURSTS DA 0 2 DEVICE ADDRESS CS0 CHIP SELECT 0 CS1 CHIP SELECT 1 RESET RESET CSEL CABLE SELECT MSTR Master ENCSEL ENABLE CSEL GND GROUND DIOR I O READ HDMARDY DMA READY DURING ULTRA DMA DATA IN BURSTS HSTROBE DATA STROBE DURING ULTRA DMA DATA OUT BURST Host IORDY I O READY DDMARDY DMA READY DURING ULTRA DMA DATA OUT BURSTS DSTROBE DATA STROBE DURING ULTRA DMA DATA IN BURSTS IDD 5V...

Page 77: ...21 23 25 27 29 31 33 35 37 39 41 43 MSTR PUS KEY RESET DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 GND DMARQ DIOW STOP DIOR HDMRDY HSTROBE IORDY DDMARDY DSTROBE DMACK INTRQ DA1 DA0 CS0 DASP 5 VDC GND B D F 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 MSTR ENCSEL ENCSEL KEY GND DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 KEY GND GND GND CSEL GND Reserved IOCS16 PDIAG ...

Page 78: ...P signal asserted by the host later indicates that the transfer has been suspended DIOR I Read strobe signal from the host to read the device register or data port HDMARDY I Flow control signal for Ultra DMA data In transfer READ DMA command This signal is asserted by the host to inform the device that the host is ready to receive the Ultra DMA data In transfer The host can negate the HDMARDY sign...

Page 79: ... is present This signal is pulled up to 5 V through 10 kΩ resistor at each device IORDY O This signal requests the host system to delay the transfer cycle when the device is not ready to respond to a data transfer request from the host system DDMARDY O Flow control signal for Ultra DMA data Out transfer WRITE DMA command This signal is asserted by the device to inform the host that the device is r...

Page 80: ... to the device O indicates output signal from the device to the host I O indicates common output or bi directional signal between the host and the device 5 2 Logical Interface The device can operate for command execution in either address specified mode cylinder head sector CHS or Logical block address LBA mode The IDENTIFY DEVICE information indicates whether the device supports the LBA mode When...

Page 81: ...ce Head Device Head X 1F6 L H H H H Status Command X 1F7 L L X X X Invalid Invalid Control block registers H L H H L Alternate Status Device Control X 3F6 H L H H H X 3F7 Notes 1 The Data register for read or write operation can be accessed by 16 bit data bus DATA0 to DATA15 2 The registers for read or write operation other than the Data registers can be accessed by 8 bit data bus DATA0 to DATA7 3...

Page 82: ...command executed by the device The contents of this register are valid when the ERR bit of the Status register is 1 This register contains a diagnostic code after power is turned on a reset or the EXECUTIVE DEVICE DIAGNOSTIC command is executed Status at the completion of command execution other than diagnostic command Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ICRC UNC X IDNF X ABRT TK0NF AM...

Page 83: ...mand For instance it is used with SET FEATURES command to enable or disable caching 4 Sector Count register X 1F2 The Sector Count register indicates the number of sectors of data to be transferred in a read or write operation between the host system and the device When the value in this register is X 00 the sector count is 256 With the EXT system command the sector count is 65536 when value of th...

Page 84: ... command the contents of this register are updated to the current cylinder number Under the LBA mode this register indicates LBA bits 15 to 8 Under the LBA mode of the EXT system command LBA bits 39 to 32 are set in the first setting and LBA bits 15 to 8 are set in the second setting 7 Cylinder High register X 1F5 The contents of this register indicate high order 8 bits of the disk access start cy...

Page 85: ...mand Bit 1 HS1 CHS mode head address 1 2 1 bit 25 for LBA mode Unused under the LBA mode of the EXT command Bit 0 HS0 CHS mode head address 0 2 0 bit 24 for LBA mode Unused under the LBA mode of the EXT command 9 Status register X 1F7 The contents of this register indicate the status of the device The contents of this register are updated at the completion of each command When the BSY bit is clear...

Page 86: ... Ready DRDY bit This bit indicates that the device is capable to respond to a command The IDD checks its status when it receives a command If an error is detected not ready state the IDD clears this bit to 0 This is cleared to 0 at power on and it is cleared until the rotational speed of the spindle motor reaches the steady speed Bit 5 The Device Write Fault DF bit This bit indicates that a device...

Page 87: ...r each command which are written to certain registers before the Command register is written 5 2 3 Control block registers 1 Alternate Status register X 3F6 The Alternate Status register contains the same information as the Status register of the command block register The only difference from the Status register is that a read of this register does not imply Interrupt Acknowledge and INTRQ signal...

Page 88: ... Bit 1 nIEN bit enables an interrupt INTRQ signal from the device to the host When this bit is 0 and the device is selected an interruption INTRQ signal can be enabled through a tri state buffer When this bit is 1 or the device is not selected the INTRQ signal is in the high impedance state 5 3 Host Commands The host system issues a command to the device by writing necessary parameters in related ...

Page 89: ... Y Y Y N D STANDBY IMMEDIATE 1 1 0 1 0 1 1 0 0 0 1 0 0 0 0 0 N N N N D IDLE IMMEDIATE 1 1 0 1 0 1 1 0 0 0 1 0 0 0 1 1 N N N N D UNLOAD IMMEDIATE 1 1 0 1 0 1 1 0 0 0 1 0 0 0 1 1 Y N Y Y D STANDBY 1 1 0 1 0 1 1 0 0 0 1 0 1 1 0 0 N Y N N D IDLE 1 1 0 1 0 1 1 0 0 0 1 0 1 1 1 1 N Y N N D CHECK POWER MODE 1 1 0 1 0 1 1 0 1 0 0 1 0 0 0 1 N N N N D SLEEP 1 1 0 1 0 1 1 0 1 0 0 1 0 1 1 0 N N N N D SMART 1 0...

Page 90: ... PASSWORD 1 1 1 1 0 1 1 0 N N N N D READ NATIVE MAX ADDRESS 1 1 1 1 1 0 0 0 N N N N D SET MAX 1 1 1 1 1 0 0 1 Y Y Y Y Y READ SECTOR S EXT O 0 0 1 0 0 1 0 0 N Y Y Y D READ DMA EXT O 0 0 1 0 0 1 0 1 N Y Y Y D READ NATIVE MAX ADDRESS EXT O 1 1 1 1 1 0 0 0 N N N N D READ MULTIPLE EXT O 0 0 1 0 1 0 0 1 N Y Y Y D READ LOG EXT O 0 0 1 0 1 1 1 1 N Y Y Y D WRITE SECTOR S EXT O 0 0 1 1 0 1 0 0 N Y Y Y D WRI...

Page 91: ...R Retry at error 1 Without retry 0 With retry Y Necessary to set parameters Y Necessary to set parameters under the LBA mode N Not necessary to set parameters The parameter is ignored if it is set N May set parameters D The device parameter is valid and the head parameter is ignored O Option customizing D The command is addressed to the master device but both the master device and the slave device...

Page 92: ...inder address LSB LBA 1F3H SN Start sector No LBA LSB 1F2H SC Transfer sector count 1F1H FR xx At command completion I O registers contents to be read Bit 7 6 5 4 3 2 1 0 1F7H ST Status information 1F6H DH x L x DV Head No LBA MSB 1F5H CH End cylinder address MSB LBA 1F4H CL End cylinder address LSB LBA 1F3H SN End sector No LBA LSB 1F2H SC X 00 1F1H ER Error information CM Command register FR Fea...

Page 93: ...of the CH CL and SN registers indicate the LBA bits bits of the DH register are the MSB most significant bit and bits of the SN register are the LSB least significant bit 2 At error occurrence the SC register indicates the remaining sector count of data transfer 3 In the table indicating I O registers contents in this subsection bit indication is omitted C141 E250 5 19 ...

Page 94: ... clears the BSY bit and generates an interrupt This command can be issued in the LBA mode At command issuance I O registers setting contents 1F7H CM 0 0 0 1 x x x x 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER xx xx xx xx Error...

Page 95: ...of the Status register is always set prior to the data transfer regardless of an error condition Upon the completion of the command execution command block registers contain the cylinder head and sector addresses in the CHS mode or logical block address in the LBA mode of the last sector read If an unrecoverable error occurs in a sector the read operation is terminated at the sector where the erro...

Page 96: ...x L x DV EndheadNo LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 00 1 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register 5 22 C141 E250 ...

Page 97: ...arget sector retries are attempted irrespectively of the R bit setting The data stored in the buffer and CRC code and ECC bytes are written to the data field of the corresponding sector s Upon the completion of the command execution the command block registers contain the cylinder head and sector addresses of the last sector written If an error occurs during multiple sector write operation the wri...

Page 98: ...x DV EndheadNo LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 00 1 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register 5 24 C141 E250 ...

Page 99: ... I O registers setting contents 1F7H CM 0 0 1 1 1 1 0 0 1F6H DH x L x DV StartheadNo LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB Transfer sector count xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH x L x DV EndheadNo LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER End cyli...

Page 100: ...S mode or the logical block address in the LBA mode of the sector where the error occurred The Sector Count register indicates the number of sectors that have not been verified At command issuance I O registers setting contents 1F7H CM 0 1 0 0 0 0 0 R 1F6H DH x L x DV StartheadNo LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA...

Page 101: ...and head position in which the sector is specified with the logical block address At command issuance I O registers setting contents 1F7H CM 0 1 1 1 x x x x 1F6H DH x L x DV Head No LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR Cylinder No MSB LBA Cylinder No LSB LBA Sector No LBA LSB xx xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH x L x DV Head N...

Page 102: ...e an interrupt A diagnostic status of the device 0 is read by the host system When a diagnostic failure of the device 1 is detected the host system can read a status of the device 1 by setting the DV bit selecting the device 1 When device 1 is not present The device 0 posts only the results of its own self diagnosis The device 0 clears the BSY bit of the Status register and generates an interrupt ...

Page 103: ...ters setting contents 1F7H CM 1 0 0 1 0 0 0 0 1F6H DH x x x DV Head No LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH x x x DV Head No LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER xx xx 01H 01H Diagnostic code C141 E250 5 29 ...

Page 104: ...his command terminates normally The parameters set by this command are retained even after reset or power save operation regardless of the setting of disabling the reverting to default setting The device ignores the L bit specification and operates with only CHS mode specification At command issuance I O registers setting contents 1F7H CM 1 0 0 1 0 0 0 1 1F6H DH x x x DV Max head No 1F5H CH 1F4H C...

Page 105: ... ER Error information This command rewrites the microcode of the device firmware When this command is accepted the device does beginning the data transfer of the microcode or the microcode rewriting according to Subcommand code Rewriting is also possible simultaneously with the data transfer Refer to Table 5 5 In the data transfer of Subcommand code 01h transfer by which data is divided into multi...

Page 106: ...2h SN SC 0100h FR 0lh 3 CMD 92h SN SC 0100h FR 0lh 4 CMD 92h SN SC 0100h FR 0lh 5 CMD 92h SN SC 0000h FR 07h Transfer from 0 to 127 KB Transfer from 128 to 255 KB Transfer from 256 to 383 KB Transfer from 384 to 511 KB Firmware rewriting execution Transfer example 2 1 CMD 92h SN SC 0400h FR 0lh 2 CMD 92h SN SC 0000h FR 07h Transfer of 512 KB Firmware rewriting execution Transfer example 3 1 CMD 92...

Page 107: ...ates an interrupt This command does not support the APS timer function At command issuance I O registers setting contents 1F7H CM X 94 or X E0 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER xx xx xx xx Error information C141 E250...

Page 108: ... information 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER xx xx xx xx Error information Unload Feature When the device received the IDLE IMMEDIATE command with the UNLOAD FEATURE the head s is unloaded to the ramp position After the device completed the unload operation the INTRQ signal will be asserted and the BUSY flag will be cleared The time until the head s unload to the ramp p...

Page 109: ...he unwritten data And the device keeps the unloaded state until receiving a Soft Hard Reset or a new command except IDLE IMMEDIATE command with the Unload Feature At command issuance I O registers setting contents 1F7H CM X E1 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR X 55 X 4E X 4C xx X 44 At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH...

Page 110: ...unction become invalid If the APS timer function becomes valid then the APS timer begins counting down after completing the next media access command such as the READ or the WRITE If the device has not received any command during specified period then the device enters standby mode automatically Under the standby mode the spindle motor is stopped Thus when the command involving a seek such as READ...

Page 111: ...ange to the standby mode automatically after specified period When the device enters the state which is waiting Host Command the timer starts countdown If any command is not issued while the timer is counting down the device automatically enters the standby mode If any command is issued while the timer is counting down the timer is initialized and the command is executed The timer restarts countdo...

Page 112: ...Interface At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER xx xx xx xx Error information 5 38 C141 E250 ...

Page 113: ... clears the BSY bit and generates an interrupt Power save mode Sector Count register During moving to Standby mode Standby mode X 00 Idle mode X FF Active mode X FF At command issuance I O registers setting contents 1F7H CM X 98 or X E5 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H ...

Page 114: ...e sleep mode the spindle motor is stopped and the ATA interface section is inactive All I O register outputs are in high impedance state The only way to release the device from sleep mode is to execute a software or hardware reset At command issuance I O registers setting contents 1F7H CM X 99 or X E6 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion ...

Page 115: ...egister and C2h in the CH register If the key values are incorrect the Aborted Command error is issued If the failure prediction function is disabled the device returns the Aborted Command error to subcommands other than those of the SMART Enable Operations with the FR register set to D8h If the failure prediction function is enabled the device collects and updates data on specific items The value...

Page 116: ...sed since the last time that attributes were saved then the attributes are saved However if the automatic attribute save function is disabled the attributes are not saved Upon receiving this subcommand a device asserts BSY enables or disables the automatic attribute save function and clears BSY X D3 SMART SAVE ATTRIBUTE VALUES When the device receives this subcommand it asserts the BSY bit saves d...

Page 117: ... this sub command asserts the BSY bit and when it has prepared to receive data from the host computer it sets DRQ and clears the BSY bit Next it receives data from the host computer and writes the specified log sector in the SN register SN SC Log sector 09h 01h SMART selective self test log 80h 9Fh 01h 10h Host vendor log The host can write any desired data in the host vendor log X D8 SMART ENABLE...

Page 118: ...ved whether the drive s power is switched on or off If 24 hours have passed since the power was switched on or since the last time that off line data were collected off line data collection is performed without relation to any command from the host computer The host must regularly issue the SMART READ DATA subcommand FR register D0h SMART SAVE ATTRIBUTE VALUES subcommand FR register D3h or SMART R...

Page 119: ... ER Key failure prediction status C2h 2Ch Key failure prediction status 4Fh F4h xx xx Error information The attribute value information is 512 byte data the format of this data is shown the following Table 5 8 The host can access this data using the SMART READ DATE subcommand FR register D0h The insurance failure threshold value data is 512 byte data the format of this data is shown the following ...

Page 120: ...ta collection capability 170 171 Trouble prediction capability flag 172 Error logging capability 173 Self test error detection point 174 Simple self test Quick Test execution time min 175 Comprehensive self test Comprehensive Test execution time min 176 Conveyance self test execution time min 177 to 181 Reserved 182 to 1FE Vendor unique 1FF Check sum Table 5 9 Format of insurance failure threshold...

Page 121: ...e ID is defined as follows Attribute ID Attribute name 0 Indicates unused attribute data 1 Read Error Rate 2 Throughput Performance 3 Spin Up Time 4 Start Stop Count 5 Reallocated Sector Count 7 Seek Error Rate 8 Seek Time Performance 9 Power On Hours Count 10 Spin Retry Count 12 Drive Power Cycle Count 192 Emergency Retract Cycle Count 193 Load Unload Cycle Count 194 HDA Temperature 195 ECC On th...

Page 122: ...drive fault prediction function is disabled 6 to 15 Reserve bit Current attribute value It indicates the normalized value of the original attribute value The value deviates in a range of 01h to 64h range of 01h to C8h for the ultra ATA CRC error rate It indicates that the closer the value is to 01h the higher the possibility of a failure The host compares the attribute value with the threshold val...

Page 123: ... Self test execution status Bit Meaning 0 to 3 Remainder of the self test is indicated as a percentage in a range of 0h to 9h corresponding to 0 to 90 4 to 7 Self test execution status 0h Self test has ended successfully or self test has not been executed 1h Self test is suspended by the host 2h Self test is interrupted by a soft hard reset from the host 3h Self test cannot be executed 4h Self tes...

Page 124: ...is received 3 If this bit is 1 it indicates that the SMART Off line Read Scanning Technology is supported 4 If this bit is 1 it indicates that the SMART Self test function is supported 5 If this bit is 1 it indicates that the SMART Conveyance Self test is supported 6 If this bit is 1 it indicates that the SMART Selective Self test is supported 7 Reserved bits Failure prediction capability flag Tab...

Page 125: ...mit of a varying attribute value The host compares the attribute values with the thresholds to identify a failure Table 5 15 Log directory data format Byte Item 00 01 SMART Logging Version 02 Number of sectors of Address 01h 03 04 05 0B Reserved Number of sectors of Address 02h Reserved 0C Number of sectors of Address 06h 0D 11 Reserved 12 Number of sectors of Address 09h 13 FF Reserved 100 Number...

Page 126: ... Table 5 16 and the SMART Comprehensive Error Log see Table 5 17 and saves the information on media The host issues the SMART Read Log Sector sub command FR register D5h SN register 01h SC register 01h and can read the SMART Summary Error Log The host issues the SMART Read Log Sector sub command FR register D5h SN register 02h SC register 33h and can read the SMART Comprehensive Error Log 5 52 C14...

Page 127: ...ve Head register value 39 Command register value 3A to 3D Fifth Command data structure Elapsed time after the power on sequence unit ms 3E Reserved 3F Error register value 40 Sector Count register value 41 Sector Number register value 42 Cylinder Low register value 43 Cylinder High register value 44 Drive Head register value 45 Status register value 46 to 58 Vendor unique 59 State 5A 5B Error log ...

Page 128: ... Vendor unique Status Meaning 0 Unclear status 1 Sleep status 2 Standby status 3 Active status BSY bit 0 4 Off line data collection being executed 5 to F Reserved Table 5 17 Data format of SMART Comprehensive Error Log Byte First sector Next sector 00h SMART Error Logging 01h Reserved 01h Index Pointer Latest Error Data Structure Reserved 02h 5Bh 1 st Error Log Data Structure Data Structure 5n 1 5...

Page 129: ... 1 Self test number SN Register Value 03 Self test execution status 04 05 Life time Total power on time hours 06 Self test error No 07 to 0A Error LBA 0B to 19 Vendor unique 1A to 1F9 Self test log 2 to 21 Each log data format is the same as that in byte 02 to 19 1FA 1FB Vendor unique 1FC Self test index 1FD 1FE Reserved 1FF Check sum Self test number Indicates the type of self test executed Self ...

Page 130: ... test 00h 00h 1F4h 1F5h Current Span under test 00h 00h 1F6h 1F7h Feature Flags 00h 00h 1F8h Offline Execution Flag 00h 1F9h Selective Offline Scan Number 00h 1FAh 1FBh Vender Unique Reserved 00h 00h 1FCh 1FDh Selective Self test pending time min 00h 00h 1FEh 1FFh Check sum 00h FFh Test span Selective self test log provides for the definition of up to five test spans If the starting and ending LBA...

Page 131: ...t is pending 4 When set to one off line scan after selective test is active 5 15 Reserved Bit l shall be written by the host and returned unmodified by the device Bit 3 4 shall be written as zeros by the host and the device shall modify them as the test progress Selective Self test pending time min The selective self test pending time is the time in minutes from power on to the resumption of the o...

Page 132: ...osted FR values Command C0h DEVICE CONFIGURATION RESTORE C1h DEVICE CONFIGURATION FREEZE C2h DEVICE CONFIGURATION IDENTIFY C3h DEVICE CONFIGURATION SET 00h BFh C4h FFh Reserved At command issuance I O register contents 1F7h CM 1 0 1 1 0 0 0 1 1F6h DH x x x DV xx 1F5h CH 1F4h CL 1F3h SN 1F2h SC 1F1h FR xx xx xx xx C0h C1h C2h C3h At command completion I O register contents 1F7h ST Status informatio...

Page 133: ...IDENTIFY FR C2h The DEVICE CONFIGURATION IDENTIFY command returns a 512 byte data structure is shown in Table 5 21 The content of this data structure indicates the selectable commands modes and feature sets that the device is capable of supporting If a DEVICE CONFIGURATION SET command has been issued reducing the capabilities the response to an IDENTIFY DEVICE command will reflect the reduced set ...

Page 134: ...ted Automatic Acoustic Management is prohibited beforehand by SET FEATURES command FR C2h If a DEVICE CONFIGURATION SET command has already modified the original settings as reported by a DEVICE CONFIGURATION IDENTIFY command if DEVICE CONFIGURATION FREEZE LOCK is set if any of the bit modification restrictions described are violated or if a Host Protected Area has been established by the executio...

Page 135: ...Bit 1 1 Ultra DMA mode 1 and below are supported Bit 0 1 Ultra DMA mode 0 is supported 3 6 Maximum LBA address Reflected in IDENTIFY information WORD60 61 WORD100 103 7 X 30CF X 39CF Command set feature set supported Reflected in IDENTIFY information WORD82 87 Bit 15 14 Reserved Bit 13 1 SMART Conveyance self test supported Bit 12 1 SMART Selective self test supported Bit 11 1 FUA Forced Unit Acce...

Page 136: ...ved 255 X xxA5 Integrity word Bits 15 8 contains the data structure checksum that is the two s complement of the sum of all byte in words 0 through 254 and the byte consisting of bits 7 0 of word 255 When 48 bit LBA of the option customize is supported same number of LBA as WORD60 61 is displayed 5 62 C141 E250 ...

Page 137: ...e number of requested sectors is not divided evenly having the same number of sectors block count as many full blocks as possible are transferred then a final partial block is transferred The number of sectors in the partial block to be transferred is n where n remainder of number of sectors block count If the READ MULTIPLE command is issued before the SET MULTIPLE MODE command is executed or when...

Page 138: ...A LSB Transfer sector count xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH x L x DV EndheadNo LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 00 1 Error information 1 If the command is terminated due to an error the remaining number of sectors for which data was not transferred is s...

Page 139: ...ssued before the SET MULTIPLE MODE command is executed or when WRITE MULTIPLE command is disabled the device rejects the WRITE MULTIPLE command with an ABORTED COMMAND error Disk errors encountered during execution of the WRITE MULTIPLE command are posted after attempting to write the block or the partial block that was transferred Write operation ends at the sector where the error was encountered...

Page 140: ...registers contents to be read 1F7H ST Status information 1F6H DH x L x DV EndheadNo LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 00 Error information 5 66 C141 E250 ...

Page 141: ... all subsequent READ MULTIPLE and WRITE MULTIPLE commands Execution of these commands is then enabled If the value of the Sector Count register is not a supported block count an ABORTED COMMAND error is posted and the READ MULTIPLE and WRITE MULTIPLE commands are disabled If the contents of the Sector Count register is 0 when the SET MULTIPLE MODE command is issued the READ MULTIPLE and WRITE MULT...

Page 142: ...ace At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER xx xx xx Sector count block Error information 5 68 C141 E250 ...

Page 143: ...TRQ signal and posts a status to the host system The format of the error information is the same as the READ SECTOR S command In LBA mode The logical block address is specified using the start head No start cylinder No and first sector No fields At command completion the logical block address of the last sector and remaining number of sectors of which data was not transferred like in the CHS mode ...

Page 144: ...x DV EndheadNo LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 00 1 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register 5 70 C141 E250 ...

Page 145: ...verable medium error that the command execution cannot be continued is detected the data transfer is stopped without transferring data of sectors after the erred sector The device generates an interrupt using the INTRQ signal and posts a status to the host system The format of the error information is the same as the WRITE SECTOR S command A host system can select the following transfer mode using...

Page 146: ...x DV EndheadNo LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 00 1 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register 5 72 C141 E250 ...

Page 147: ...it of Status register clears the BSY bit and generates an interrupt After that the host system can read up to 512 bytes of data from the buffer At command issuance I O registers setting contents 1F7H CM 1 1 1 0 0 1 0 0 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH x x x DV xx 1F5...

Page 148: ...rror has occurred while the data is being read the error generation address is put into the command block register before ending the command This error sector is deleted from the write cache data and the remaining cache data is written into the medium by the execution of the next Flush Cache command At command issuance I O register contents 1F7h CM 1 1 1 0 0 1 1 1 1F6h DH x x x DV xx 1F5h CH 1F4h ...

Page 149: ... bit when the device is ready to receive the data After that 512 bytes of data is transferred from the host and the device writes the data to the buffer then generates an interrupt At command issuance I O registers setting contents 1F7H CM 1 1 1 0 1 0 0 0 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents to be read 1F7H ST Statu...

Page 150: ...o and generates an interrupt After that the host system reads the information out of the sector buffer Table 5 22 shows the values of the parameter words and the meaning in the buffer At command issuance I O registers setting contents 1F7H CM 1 1 1 0 1 1 0 0 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents to be read 1F7H ST St...

Page 151: ...e Identify Device command At command issuance I O registers setting contents 1F7H CM 1 1 1 0 1 1 1 0 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER xx xx xx xx Error information C141 E250 5 77 ...

Page 152: ...7 46 Set by a device Model name ASCII code 40 characters left 47 X 8010 Maximum number of sectors per interrupt on READ WRITE MULTIPLE command 48 X 0000 Reserved 49 X 2B00 Capabilities 4 50 X 400x Capabilities 5 51 X 0200 PIO data transfer mode 6 52 X 0200 Reserved 53 X 0007 Enable disable setting of words 54 58 and 64 70 88 7 54 Variable Number of current Cylinders 55 Variable Number of current H...

Page 153: ... 15 86 16 Valid of command sets function 16 87 17 Default of command sets function 17 88 X xx3F Ultra DMA transfer mode 18 89 Set by a device Security Erase Unit execution time 1 LSB 2 min 19 90 X 0000 Enhanced Security Erase Unit execution time 1 LSB 2 min 91 Variable Advance power management level 92 Variable Master password revision 93 20 Hardware configuration 20 94 Variable Acoustic Managemen...

Page 154: ...lete 738Ch The device requires the SET FEATURES sub command after the power on sequence in order to spin up The Identify information is incomplete 8C73h The device requires the SET FEATURES sub command after the power on sequence in order to spin up The Identify information is incomplete C837h The device requires the SET FEATURES sub command after the power on sequence in order to spin up The Iden...

Page 155: ...the word 54 58 8 Word 59 Transfer sector count currently set by READ WRITE MULTIPLE command Bit 15 9 Reserved Bit 8 1 Enable the multiple sector transfer Bit 7 0 Transfer sector count currently set by READ WRITE MULTIPLE command without interrupt supports 2 4 8 and 16 sectors 9 Word 63 Multiword DMA transfer mode Bit 15 11 Reserved Bit 10 1 multiword DMA mode 2 is selected Bit 9 1 multiword DMA mo...

Page 156: ...NOP command Bit 13 1 Supports the READ BUFFER command Bit 12 1 Supports the WRITE BUFFER command Bit 11 Undefined Bit 10 1 Supports the Host Protected Area feature set Bit 9 1 Supports the DEVICE RESET command Bit 8 1 Supports the SERVICE interrupt Bit 7 1 Supports the release interrupt Bit 6 1 Supports the read cache function Bit 5 1 Supports the write cache function Bit 4 1 Supports the PACKET c...

Page 157: ...a Status Notification feature set Bit 3 1 Supports the Advanced Power Management feature set Bit 2 1 Supports the CFA Compact Flash Association feature set Bit 1 1 Supports the READ WRITE DMA QUEUED command Bit 0 1 Supports the DOWNLOAD MICROCODE command Option customizing 14 WORD 84 Bit 15 0 Bit 14 1 Bit 13 1 Supports the IDLE IMMDIATE with UNLOAD FEATURE Bit 12 11 Reserved Bit 10 1 URG bit suppo...

Page 158: ...ed Bit 10 1 Supports the Host Protected Area function Bit 9 1 Supports the DEVICE RESET command Bit 8 1 Enables the SERVICE interrupt From the SET FEATURES command Bit 7 1 Enables the release interrupt From the SET FEATURES command Bit 6 1 Enables the read cache function From the SET FEATURES command Bit 5 1 Enables the write cache function Bit 4 1 Enables the P PACKET command set Bit 3 1 Supports...

Page 159: ...he Removable Media Status Notification function Bit 3 1 Enables the Advanced Power Management function Bit 2 1 Supports the CFA Compact Flash Association feature set Bit 1 1 Supports the READ WRITE DMA QUEUED command Bit 0 1 Supports the DOWNLOAD MICROCODE command Option customizing 17 WORD 87 Bit 15 0 Bit 14 1 Bit 13 1 Supports the IDLE IMMDIATE with UNLOAD FEATURE Bit 12 11 Reserved Bit 10 1 URG...

Page 160: ...de 1 is selected Bit 8 1 Mode 0 is selected Bit 7 0 Supportable Ultra DMA transfer mode Bit 5 1 Supports the Mode 5 Bit 4 1 Supports the Mode 4 Bit 3 1 Supports the Mode 3 Bit 2 1 Supports the Mode 2 Bit 1 1 Supports the Mode 1 Bit 0 1 Supports the Mode 0 19 WORD 89 Value 2 minutes MHW2080AT X 28 80 minutes MHW2060AT X 1E 60 minutes MHW2040AT X 14 40 minutes 20 WORD 93 Bits 15 0 Bit 14 1 Bit 13 1 ...

Page 161: ...4 1 Device 0 assertion of PDIAG was detected Bit 3 1 Device 0 an error was not detected in the self diagnosis Bit 2 1 Method for deciding the device No of Device 0 00 Reserved 01 Using a jumper 10 Using the CSEL signal 11 Other method Bit 0 1 In the case of device 0 21 WORD 94 Bit 15 8 X FE Recommended acoustic management value Bit 7 0 X XX Current set value FE C0 Performance mode BF 80 Acoustic m...

Page 162: ...it 8 Security level 0 High 1 Maximum Bit 7 6 Reserved Bit 5 1 Enhanced security erase supported Bit 4 1 Security counter expired Bit 3 1 Security frozen Bit 2 1 Security locked Bit 1 1 Security enabled Bit 0 1 Security supported 5 88 C141 E250 ...

Page 163: ... X 03 Set the data transfer mode 1 X 05 Enables the advanced power management function 2 X 42 Enables the Acoustic management function 3 X 55 Disables read cache function X 66 Disables the reverting to power on default settings after software reset 1 X 82 Disables the write cache function X 85 Set the advanced power management mode to Mode 0 X AA Enables the read cache function X BB Specifies the ...

Page 164: ... to the Features register By issuing this command with setting a value to the Sector Count register the transfer mode can be selected Upper 5 bits of the Sector Count register defines the transfer type and lower 3 bits specifies the binary mode value The IDD supports following values in the Sector Count register value If other value than below is specified an ABORTED COMMAND error is posted PIO de...

Page 165: ...es not receive any commands for a specific time The sequence in which the power management level shifts is from Active Idle to Low Power Idle to Standby The Mode 2 level requires the longest shifting time depending on the APM level settings The settings of the APM level revert to their default values Mode 1 when power on or a hardware reset occurs for the drive APM Level Sector Count Register Mode...

Page 166: ...he drive across power on hardware and software resets AAM Level Sector Count Register Performance mode Fast Seek Acoustic mode Slow Seek Abort Non Operate C0h FEh 80h BFh 01h 7Fh 00h FFh High speed seek to which gives priority to the performance operates as for Performance mode and low speed seek by which the seek sound is suppressed operates as for Acoustic mode Setting the seek mode by this comm...

Page 167: ...5 Reserved 1 to 16 Password 32 bytes 17 Master password version number Valid is Bit 0 1 18 to 255 Reserved Table 5 25 Relationship between combination of Identifier and Security level and operation of the lock function Identifier Level Description User High The specified password is saved as a new user password The lock function is enabled after the device is turned off and then on LOCKED MODE can...

Page 168: ...1 1 1 0 0 0 1 1F6h DH x x x DV xx 1F5h CH 1F4h CL 1F3h SN 1F2h SC 1F1h FR xx xx xx xx xx At command completion I O register contents 1F7h ST Status information 1F6h DH x x x DV xx 1F5h CH 1F4h CL 1F3h SN 1F2h SC 1F1h ER xx xx xx xx Error information 5 94 C141 E250 ...

Page 169: ...s selected The password is compared with the user password already set If the passwords are the same LOCKED MODE is canceled Otherwise the Aborted Command error is returned If the password comparison fails the device decrements the UNLOCK counter The UNLOCK counter initially has a value of five When the value of the UNLOCK counter reaches zero this command or the SECURITY ERASE UNIT command causes...

Page 170: ...Interface At command completion I O register contents 1F7h ST Status information 1F6h DH x x x DV xx 1F5h CH 1F4h CL 1F3h SN 1F2h SC 1F1h ER xx xx xx xx Error information 5 96 C141 E250 ...

Page 171: ... erased unnecessarily by the SECURITY ERASE UNIT command Issuing this command during FROZEN MODE returns the Aborted Command error At command issuance I O register contents 1F7h CM 1 1 1 1 0 0 1 1 1F6h DH x x x DV xx 1F5h CH 1F4h CL 1F3h SN 1F2h SC 1F1h FR xx xx xx xx xx At command completion I O register contents 1F7h ST Status information 1F6h DH x x x DV xx 1F5h CH 1F4h CL 1F3h SN 1F2h SC 1F1h ...

Page 172: ...ommand invalidates the user password the master password is retained To recover the master password issue the SECURITY SET PASSWORD command and reset the user password If the SECURITY ERASE PREPARE command is not issued immediately before this command is issued the Aborted Command error is returned Issuing this command while in FROZEN MODE returns the Aborted Command error At command issuance I O ...

Page 173: ...If this command is reissued in FROZEN MODE the command is completed and FROZEN MODE remains unchanged Issuing this command during LOCKED MODE returns the Aborted Command error The following medium access commands return the Aborted Command error when the device is in LOCKED MODE EREAD SECTORS EXT WRITE SECTORS EXT WRITE VERIFY READ VERIFY SECTORS EXT READ MULTIPLE EXT WRITE MULTIPLE EXT FUA EXT RE...

Page 174: ... 1 1 0 1 0 1 1F6h DH x x x DV xx 1F5h CH 1F4h CL 1F3h SN 1F2h SC 1F1h FR xx xx xx xx xx At command completion I O register contents 1F7h ST Status information 1F6h DH x x x DV xx 1F5h CH 1F4h CL 1F3h SN 1F2h SC 1F1h ER xx xx xx xx Error information 5 100 C141 E250 ...

Page 175: ... SECURITY SET PASSWORD command and reset the user password If the user password or master password transferred from the host does not match the Aborted Command error is returned Issuing this command while in LOCKED MODE or FROZEN MODE returns the Aborted Command error The section about the SECURITY FREEZE LOCK command describes LOCKED MODE and FROZEN MODE Table 5 26 Contents of security password W...

Page 176: ...Interface At command completion I O register contents 1F7h ST Status information 1F6h DH x x x DV xx 1F5h CH 1F4h CL 1F3h SN 1F2h SC 1F1h ER xx xx xx xx Error information 5 102 C141 E250 ...

Page 177: ...N registers Then it clears BSY and generates an interrupt At command issuance I O registers setting contents 1F7H CM 1 1 1 1 1 0 0 0 1F6H DH x L x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH x x x DV Max head LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER Max cylinder MSB Max LBA Max cylind...

Page 178: ...ss space an ID Not Found error will result When SC register bit 0 VV Value Volatile is 1 the value set by this command is held even after power on and the occurrence of a hard reset When the VV bit is 0 the value set by this command becomes invalid when the power is turned on or a hard reset occurs and the maximum address returns to the value most lately set when VV bit 1 The value by VV bit 0 is ...

Page 179: ... LSB Max LBA 1F3H SN Max sector Max LBA LSB 1F2H SC xx 1F1H ER Error information SET MAX SET PASSWORD FR 01h This command requests a transfer of 1 sector of data from the host and defines the contents of SET MAX password The password is retained by the device until the next power cycle The READ NATIVE MAX ADDRESS command is not executed just before this command The command is the SET MAX ADDRESS c...

Page 180: ... SET_MAX_LOCK state After this command is completed any other SET MAX commands except SET MAX UNLOCK and SET MAX FREEZE LOCK commands are rejected And the device returns command aborted The device remains in the SET MAX LOCK state until a power cycle or the acceptance of SET MAX UNLOCK or SET MAX FREEZE LOCK command The READ NATIVE MAX ADDRESS command is not executed just before this command The c...

Page 181: ...red shall be compared with the stored password If the password compare fails the device returns command aborted and decrements the Unlock counter and remains in the Set Max Lock state On the acceptance of the SET MAX LOCK command the Unlock counter is set to a value of five When this counter reaches zero then SET MAX UNLOCK command returns command aborted until a power cycle If the password compar...

Page 182: ...the device to SET_MAX_Frozen state After the device made a transition to the Set Max Freeze Lock state the following SET MAX commands are rejected then the device returns command aborted SET MAX ADDRESS SET MAX SET PASSWORD SET MAX LOCK SET MAX UNLOCK If the Device is in the SET_MAX_UNLOCK state with the SET MAX FREEZE LOCK command then the device returns command aborted The READ NATIVE MAX ADDRES...

Page 183: ... CM 1 1 1 1 1 0 0 1 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN xx xx xx 1F2H SC xx 1F1H FR 04 At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH 1F5H CH 1F4H CL 1F3H SN 1F2H SC xx xx xx xx xx 1F1H ER Error information C141 E250 5 109 ...

Page 184: ...I O registers setting contents 1F7h CM 0 0 1 0 0 1 0 0 1F6h DH 1 L 1 DV xx 1F5h CH P 1F5h CH C 1F4h CL P 1F4h CL C 1F3h SN P 1F3h SN C 1F2h SC P 1F2h SC C 1F1h FR P 1F1h FR C LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx C Current P Previous At command completion I O registers contents to be read 1F7h ST Status information 1F6h DH 1 L 1 DV xx 1F5...

Page 185: ...registers setting contents 1F7h CM 0 0 1 0 0 1 0 1 1F6h DH 1 L 1 DV xx 1F5h CH P 1F5h CH C 1F4h CL P 1F4h CL C 1F3h SN P 1F3h SN C 1F2h SC P 1F2h SC C 1F1h FR P 1F1h FR C LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx C Current P Previous At command completion I O registers contents to be read 1F7h ST Status information 1F6h DH 1 L 1 DV xx 1F5h CH...

Page 186: ...s setting contents 1F7h CM 0 0 1 0 0 1 1 1 1F6h DH 1 L 1 DV xx 1F5h CH P 1F5h CH C 1F4h CL P 1F4h CL C 1F3h SN P 1F3h SN C 1F2h SC P 1F2h SC C 1F1h FR P 1F1h FR C xx xx xx xx xx xx xx xx xx xx C Current P Previous At command completion I O registers contents to be read 1F7h ST Status information 1F6h DH 1 L 1 DV xx 1F5h CH 1 1F5h CH 0 1F4h CL 1 1F4h CL 0 1F3h SN 1 1F3h SN 0 1F2h SC 1 1F2h SC 0 1F1...

Page 187: ...nce I O registers setting contents 1F7h CM 0 0 1 0 1 0 0 1 1F6h DH 1 L 1 DV xx 1F5h CH P 1F5h CH C 1F4h CL P 1F4h CL C 1F3h SN P 1F3h SN C 1F2h SC P 1F2h SC C 1F1h FR P 1F1h FR C LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx C Current P Previous At command completion I O registers contents to be read 1F7h ST Status information 1F6h DH 1 L 1 DV xx...

Page 188: ...to the transfer of data see Section 5 4 1 When command is issued I O register setting values 1F7H CM 0 0 1 0 1 1 1 1 1F6H DH x x x DV xx 1F5H CH P 1F5H CH C 1F4H CL P 1F4H CL C 1F3H SN P 1F3H SN C 1F2H SC P 1F2H SC C 1F1H FR P 1F1H FR C xx xx Sector offset 15 8 Sector offset 7 0 xx Log address Sector count 15 8 Sector count 7 0 xx xx C Current P Previous When command is completed read data in I O ...

Page 189: ...ansfer Sector count Number of sectors to be read from the specified log If the device does not support this command the device shall return the Command Aborted error If the Log address value the Sector count value or the Sector offset value is invalid the device shall return the Command Aborted error C141 E250 5 115 ...

Page 190: ... I O registers setting contents 1F7h CM 0 0 1 1 0 1 0 0 1F6h DH 1 L 1 DV xx 1F5h CH P 1F5h CH C 1F4h CL P 1F4h CL C 1F3h SN P 1F3h SN C 1F2h SC P 1F2h SC C 1F1h FR P 1F1h FR C LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx C Current P Previous At command completion I O registers contents to be read 1F7h ST Status information 1F6h DH 1 L 1 DV xx 1F...

Page 191: ...O registers setting contents 1F7h CM 0 0 1 1 0 1 0 1 1F6h DH 1 L 1 DV xx 1F5h CH P 1F5h CH C 1F4h CL P 1F4h CL C 1F3h SN P 1F3h SN C 1F2h SC P 1F2h SC C 1F1h FR P 1F1h FR C LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx C Current P Previous At command completion I O registers contents to be read 1F7h ST Status information 1F6h DH 1 L 1 DV xx 1F5h ...

Page 192: ...e highest address value is defined as the last value specified If the VV bit is not set to 1 the highest address is the default value After a power on reset is performed a host can issue the SET MAX ADDRESS EXT command only once if the VV bit is 1 If the SET MAX ADDRESS EXT command is issued twice or more an ID Not Found error occurs When the SET MAX ADDRESS EXT command is executed all SET MAX ADD...

Page 193: ...LBA 31 24 SET MAX LBA 7 0 1F2h SC P xx 1F2h SC C xx VV 1F1h FR P 1F1h FR C xx xx C Current P Previous At command completion I O registers contents to be read 1F7h ST Status information 1F6h DH 1 L 1 DV xx 1F5h CH 1 1F5h CH 0 1F4h CL 1 1F4h CL 0 1F3h SN 1 1F3h SN 0 1F2h SC 1 1F2h SC 0 1F1h ER SET MAX LBA 47 40 SET MAX LBA 23 16 SET MAX LBA 39 32 SET MAX LBA 15 8 SET MAX LBA 31 24 SET MAX LBA 7 0 xx...

Page 194: ... I O registers setting contents 1F7h CM 0 0 1 1 1 0 0 1 1F6h DH 1 L 1 DV xx 1F5h CH P 1F5h CH C 1F4h CL P 1F4h CL C 1F3h SN P 1F3h SN C 1F2h SC P 1F2h SC C 1F1h FR P 1F1h FR C LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx C Current P Previous At command completion I O registers contents to be read 1F7h ST Status information 1F6h DH 1 L 1 DV xx 1F...

Page 195: ... 1 1 1 1 0 1 1F6h DH 1 L 1 DV xx 1F5h CH P 1F5h CH C 1F4h CL P 1F4h CL C 1F3h SN P 1F3h SN C 1F2h SC P 1F2h SC C 1F1h FR P 1F1h FR C LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx C Current P Previous At command completion I O registers contents to be read 1F7h ST Status information 1F6h DH 1 L 1 DV xx 1F5h CH 1 1F5h CH 0 1F4h CL 1 1F4h CL 0 1F3h ...

Page 196: ... BSY protocols related to the transfer of data see Section 5 4 1 When command is issued I O register setting values 1F7H CM 0 0 1 1 1 1 1 1 1F6H DH x x x DV xx 1F5H CH P 1F5H CH C 1F4H CL P 1F4H CL C 1F3H SN P 1F3H SN C 1F2H SC P 1F2H SC C 1F1H FR P 1F1H FR C xx xx Sector offset 15 8 Sector offset 7 0 xx Log address Sector count 15 8 Sector count 7 0 xx xx C Current P Previous When command is comp...

Page 197: ...ransfer Sector count Number of sectors to be written to the specified log If the device does not support this command the device shall return the Command Aborted error If the Log address value the Sector count value or the Sector offset value is invalid the device shall return the Command Aborted error C141 E250 5 123 ...

Page 198: ... issuance I O registers setting contents 1F7h CM 0 1 0 0 0 0 1 0 1F6h DH 1 L 1 DV xx 1F5h CH P 1F5h CH C 1F4h CL P 1F4h CL C 1F3h SN P 1F3h SN C 1F2h SC P 1F2h SC C 1F1h FR P 1F1h FR C LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx C Current P Previous At command completion I O registers contents to be read 1F7h ST Status information 1F6h DH 1 L 1...

Page 199: ...h CM 1 1 0 0 1 1 1 0 1F6h DH 1 L 1 DV xx 1F5h CH P 1F5h CH C 1F4h CL P 1F4h CL C 1F3h SN P 1F3h SN C 1F2h SC P 1F2h SC C 1F1h FR P 1F1h FR C LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx C Current P Previous At command completion I O registers contents to be read 1F7h ST Status information 1F6h DH 1 L 1 DV xx 1F5h CH 1 1F5h CH 0 1F4h CL 1 1F4h CL...

Page 200: ...sters setting contents 1 1 1 0 0 1F6h DH 1 L 1 DV xx 1F5h CH P 1F5h CH C 1F4h CL P 1F4h CL C 1F3h SN P 1F3h SN C 1F2h SC P 1F2h SC C 1F1h FR P xx xx 1F1h FR C xx xx xx xx xx xx xx xx 1F7h CM 1 0 1 C Current P Previous At command completion I O registers contents to be read 1F7h ST Status information 1F6h DH 1 L 1 DV xx 1F5h CH 1 1F5h CH 0 1F4h CL 1 1F4h CL 0 1F3h SN 1 1F3h SN 0 1F2h SC 1 1F2h SC 0...

Page 201: ...DE V V V V STANDBY IMMEDIATE V V V V IDLE UNLOAD IMMEDIATE V V V V STANDBY V V V V IDLE V V V V CHECK POWER MODE V V V V SLEEP V V V V SMART V V V V V DEVICE CONFIGURATION V V V V READ MULTIPLE V V V V V V WRITE MULTIPLE V V V V V SET MULTIPLE MODE V V V V READ DMA V 2 V V V V V V WRITE DMA V 2 V V V V V READ BUFFER V V V V FLUSH CACHE V V V V V WRITE BUFFER V V V V IDENTIFY DEVICE V V V V IDENTIF...

Page 202: ... V V V V V READ LOG EXT O V V V V V V WRITE SECTOR S EXT O V V V V V WRITE DMA EXT O V 2 V V V V V SET MAX ADDRESS EXT O V V V V V WRITE MULTIPLE EXT O V V V V V WRITE DMA FUA EXT O V 2 V V V V V WRITE LOG EXT O V V V V V READ VERIFY SECTOR S EXT O V V V V V V WRITE MULTIPLE FUA EXT O V V V V V FLUSH CACHE EXT O V V V V V INVALID COMMAND V V V V V Valid on this command 1 See the command descriptio...

Page 203: ...NFIGURATION IDENTIFY READ BUFFER IDENTIFY DEVICE READ LOG EXT The execution of these commands includes the transfer one or more sectors of data from the device to the host Following shows the protocol outline a The host writes any required parameters to the Features Sector Count Sector Number Cylinder and Device Head registers b The host writes a command code to the Command register c The device s...

Page 204: ...ansfer by setting the DRQ bit Whether or not to transfer the data is determined for each host In other words the host should receive the relevant sector of data 512 bytes of uninsured dummy data or release the DRQ status by resetting Figure 5 3 shows an example of READ SECTOR S command protocol and Figure 5 4 shows an example protocol for command abort Figure 5 3 READ SECTOR S COMMAND protocol 5 1...

Page 205: ... that the host does not need to read the Status register for the reading of a single sector or the last sector in multiple sector reading If the timing to read the Status register does not meet above condition normal data transfer operation is not guaranteed When the host new command even if the device requests the data transfer setting in DRQ bit the correct device operation is not guaranteed Tra...

Page 206: ...Head registers b The host writes a command code in the Command register The drive sets the BSY bit of the Status register c When the device is ready to receive the data of the first sector the device sets DRQ bit and clears BSY bit d The host writes one sector of data through the Data register e The device clears the DRQ bit and sets the BSY bit f When the drive completes transferring the data of ...

Page 207: ...e to starting of the sector data transfer Note that the host does not need to read the Status register for the first and the last sector to be transferred If the timing to read the Status register does not meet above condition normal data transfer operation is not assured guaranteed When the host issues the command even if the drive requests the data transfer DRQ bit is set or when the host execut...

Page 208: ...OAD IMMEDIATE STANDBY IDLE CHECK POWER MODE SLEEP SMART ENABLE DISABLE AUTOSAVE SMART EXECUTE OFFLINE IMMEDIATE SMART ENABLE OPERATION SMART DISABLE OPERATION SMART RETURN STATUS DEVICE CONFIGURATION RESTORE DEVICE CONFIGURAION FREEZE LOCK SET MULTIPLE MODE FLUSH CACHE EXT SET FEATURES SECURITY ERASE PREPARE SECURITY FREEZE LOCK READ NATIVE MAX ADDRESS EXT SET MAX ADDRESS EXT Figure 5 6 shows the ...

Page 209: ...es not issue interruptions in any intermediate sector when a multisector command is executed The following outlines the protocol The interrupt processing for the DMA transfer differs the following point The interrupt processing for the DMA transfer differs the following point a The host writes any parameters to the Features Sector Count Sector Number Cylinder and Device Head register b The host in...

Page 210: ...device clears both BSY and DRQ bits and asserts the INTRQ signal Then the host reads the Status register g The host resets the DMA channel Figure 5 7 shows the correct DMA data transfer protocol g d f f d e Figure 5 7 Normal DMA data transfer 5 136 C141 E250 ...

Page 211: ...he device during an Ultra DMA data in burst or to the host for an Ultra DMA data out burst During an Ultra DMA burst a sender shall always drive data onto the bus and after a sufficient time to allow for propagation delay cable settling and setup time the sender shall generate a STROBE edge to latch the data Both edges of STROBE are used for data transfers so that the frequency of STROBE is limite...

Page 212: ...BE is used in cases that could apply to either DSTROBE or HSTROBE The following are general Ultra DMA rules a An Ultra DMA burst is defined as the period from an assertion of DMACK by the host to the subsequent negation of DMACK b A recipient shall be prepared to receive at least two data words whenever it enters or resumes an Ultra DMA burst 5 5 3 Ultra DMA data in commands 5 5 3 1 Initiating an ...

Page 213: ... of data onto DD 15 0 5 5 3 2 The data in transfer The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 3 3 and 5 6 3 2 for specific timing requirements 1 The device shall drive a data word onto DD 15 0 2 The device shall generate a DSTROBE edge to latch the new word no sooner than tDVS after changing the state of DD 15 0 The device shall gener...

Page 214: ... result of cable round trip delay and tRFS timing for the device 5 The host shall resume an Ultra DMA burst by asserting HDMARDY 5 5 3 4 Terminating an Ultra DMA data in burst a Device terminating an Ultra DMA data in burst The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 3 5 and 5 6 3 2 for specific timing requirements 1 The device shall i...

Page 215: ... with the results of its own CRC calculation If a miscompare error occurs during one or more Ultra DMA bursts for any one command at the end of the command the device shall report the first error that occurred see 5 5 5 12 The device shall release DSTROBE within tIORDYZ after the host negates DMACK 13 The host shall not negate STOP no assert HDMARDY until at least tACK after negating DMACK 14 The ...

Page 216: ...MARQ 9 The host shall drive DD 15 0 no sooner than tZAH after the device has negated DMARQ For this step the host may first drive DD 15 0 with the result of its CRC calculation see 5 5 5 10 If the host has not placed the result of its CRC calculation on DD 15 0 since first driving DD 15 0 during 9 the host shall place the result of its CRC calculation on DD 15 0 see 5 5 5 11 The host shall negate ...

Page 217: ...ACK asserted until the end of an Ultra DMA burst 7 The device may negate DDMARDY tZIORDY after the host has asserted DMACK Once the device has negated DDMARDY the device shall not release DDMARDY until after the host has negated DMACK at the end of an Ultra DMA burst 8 The host shall negate STOP within tENV after asserting DMACK The host shall not assert STOP until after the first negation of HSTR...

Page 218: ...at least one data word of an Ultra DMA burst has been transferred 2 The host shall pause an Ultra DMA burst by not generating an HSTROBE edge Note The device shall not immediately negate DMARQ to initiate Ultra DMA burst termination when the host stops generating HSTROBE edges If the host does not assert STOP in order to initiate Ultra DMA burst termination the device shall negate DDMARDY and wait...

Page 219: ...s negated DMARQ No data shall be transferred during this assertion The device shall ignore this transition on HSTROBE HSTROBE shall remain asserted until the Ultra DMA burst is terminated 6 The host shall place the result of its CRC calculation on DD 15 0 see 5 5 5 7 The host shall negate DMACK no sooner than tMLI after the host has asserted HSTROBE and STOP and the device has negated DMARQ and DD...

Page 220: ...DMARQ again until after the Ultra DMA burst is terminated 6 The host shall assert STOP with tLI after the device has negated DMARQ The host shall not negate STOP again until after the Ultra DMA burst is terminated 7 If HSTROBE is negated the host shall assert HSTROBE with tLI after the device has negated DMARQ No data shall be transferred during this assertion The device shall ignore this transiti...

Page 221: ...ts of its CRC calculation function to the device on DD 15 0 with the negation of DMACK f The device shall then compare the CRC data from the host with the calculated value in its own CRC calculation function If the two values do not match the device shall save the error and report it at the end of the command A subsequent Ultra DMA burst for the same command that does not have a CRC error shall no...

Page 222: ...ribes recommended values for series termination at the host and the device Table 5 28 Recommended series termination for Ultra DMA Signal Host Termination Device Termination DIOR HDMARDY HSTROBE 22 ohm 82 ohm DIOW STOP 22 ohm 82 ohm CS0 CS1 33 ohm 82 ohm DA0 DA1 DA2 33 ohm 82 ohm DMACK 22 ohm 82 ohm DD15 through DD0 33 ohm 33 ohm DMARQ 82 ohm 22 ohm INTRQ 82 ohm 22 ohm IORDY DDMARDY DSTROBE 82 ohm...

Page 223: ... setup time for DIOR DIOW 25 ns t2 Pulse width of DIOR DIOW 70 ns t2i Recovery time of DIOR DIOW 25 ns t3 Data setup time for DIOW 20 ns t4 Data hold time for DIOW 10 ns t5 Time from DIOR assertion to read data available 50 ns t6 Data hold time for DIOR 5 ns t9 Data register selection hold time for DIOR DIOW 10 ns t10 Time from DIOR DIOW assertion to IORDY low level 35 ns t11 Time from validity of...

Page 224: ...0 tG tF Write DD 15 0 tG tH Symbol Timing parameter Min Max Unit tD Pulse width of DIOR DIOW 70 ns tE Data Access time for DIOR 50 ns tF Data hold time for DIOR 5 ns tG Data setup time for DIOR DIOW 20 ns tH Data hold time for DIOW 10 ns tI DMACK setup time for DIOR DIOW 0 ns t CS 1 0 Available time for DIOR DIOW 25 ns Figure 5 10 Multiword DMA data transfer timing mode 2 5 150 C141 E250 ...

Page 225: ...data in burst 5 6 3 2 contains the values for the timings for each of the Ultra DMA Modes DMARQ device DMACK host STOP host HDMARDY host DSTROBE device DD 15 0 DA0 DA1 DA2 CS0 CS1 tUI tENV tFS tENV tZAD tFS tZAD tDVH tAZ tZIORDY tACK tACK tACK tVDS tDZFS tZFS Note The definitions for the STOP HDMARDY and DSTROBE signal lines are not in effect until DMARQ and DMACK are asserted Figure 5 11 Initiati...

Page 226: ... at recipient from STROBE edge until data may become invalid 2 5 tDVS 70 48 31 20 6 7 4 8 Data valid setup time at sender from data valid until STROBE edge 3 tDVH 6 2 6 2 6 2 6 2 6 2 4 8 Data valid hold time at sender from STROBE edge until data may become invalid 3 tCS 15 10 7 7 5 5 CRC word setup time at device 2 tCH 5 5 5 5 5 5 CRC word hold time device 2 tCVS 70 48 31 20 6 7 10 CRC word valid ...

Page 227: ...0 50 50 50 Time from STROBE edge to negation of DMARQ or assertion of STOP when sender terminates a burst 1 Except for some instances of tMLI that apply to host signals only the parameters tUI tMLI and tLI indicate sender to recipient or recipient to sender interlocks i e one agent either sender or recipient is waiting for the other agent to respond with a signal before proceeding tUI is an unlimi...

Page 228: ...6 Sender IC data valid hold time from STROBE edge until data may become invalid 2 1 The correct data value shall be captured by the recipient given input data with a slew rate of 0 4 V ns rising and falling and the input STROBE with a slew rate of 0 4 V ns rising and falling at tDSIC and tDHIC timing as measured through 1 5V 2 The parameters tDVSIC and tDVHIC shall be met for lumped capacitive loa...

Page 229: ...HIC tDS tDSIC tDH tDHIC t2CYC tCYC tDVS tDVSIC tDVH tDVHIC tDH tDHIC tDH tDHIC tDVH tDVHIC tDS tDSIC Note DD 15 0 and DSTROBE signals are shown at both the host and the device to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device Figure 5 12 Sustained Ultra DMA...

Page 230: ...e DMACK host STOP host HDMARDY host DSTROBE device DD 15 0 device Notes 1 The host may assert STOP to request termination of the Ultra DMA burst no sooner than tRP after HDMARDY is negated 2 After negating HDMARDY the host may receive zero one two or three more data words from the device Figure 5 13 Host pausing an Ultra DMA data in burst 5 156 C141 E250 ...

Page 231: ...device DMACK host DD 15 0 HDMARDY host DSTROBE device STOP host DA0 DA1 DA2 CS0 CS1 tMLI tLI tLI tLI tACK tACK tIORDYZ tSS tZAH tAZ tCVS tCVH CRC tACK Note The definitions for the STOP HDMARDY and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 14 Device terminating an Ultra DMA data in burst C141 E250 5 157 ...

Page 232: ...ce tLI tMLI tRP tZAH tAZ tRFS tLI tMLI tCVS tCVH tACK tACK tACK tIORDYZ CRC DA0 DA1 DA2 CS0 CS1 DMACK host STOP host HDMARDY host DSTROBE device DD 15 0 Note The definitions for the STOP HDMARDY and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 15 Host terminating an Ultra DMA data in burst 5 158 C141 E250 ...

Page 233: ...MARQ device DMACK host STOP host DDMARDY device HSTROBE host DD 15 0 host DA0 DA1 DA2 CS0 CS1 tUI tACK tENV tZIORDY tUI tLI tACK tACK tDVH tDVS tDZFS Note The definitions for the STOP DDMARDY and HSTROBE signal lines are not in effect until DMARQ and DMACK are asserted Figure 5 16 Initiating an Ultra DMA data out burst C141 E250 5 159 ...

Page 234: ...C tDVS tDVSIC tDVS tDVSIC tDVH tDVHIC tDH tDHIC tDS tDSIC tDH tDHIC tDS tDSIC tDH tDHIC tDVH tDVHIC Note DD 15 0 and HSTROBE signals are shown at both the device and the host to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host Figure 5 17 Sustained Ultra DMA ...

Page 235: ...ost STOP host DDMARDY device HSTROBE host DD 15 0 host tRP tRFS Notes 1 The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than tRP after DDMARDY is negated 2 After negating DDMARDY the device may receive zero one two or three more data words from the host Figure 5 18 Device pausing an Ultra DMA data out burst C141 E250 5 161 ...

Page 236: ...Q device DMACK host STOP host DDMARDY device HSTROBE host DD 15 0 host tLI tLI tSS tLI tMLI tACK tIORDYZ tACK tACK tCVH tCVS CRC DA0 DA1 DA2 CS0 CS1 Note The definitions for the STOP DDMARDY and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 19 Host terminating an Ultra DMA data out burst 5 162 C141 E250 ...

Page 237: ...evice DMACK host STOP host DDMARDY device HSTROBE host DD 15 0 host DA0 DA1 DA2 CS0 CS1 tLI tLI tRP tRFS tMLI tMLI tCVS tCVH tIORDYZ tACK tACK tACK CRC Note The definitions for the STOP DDMARDY and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 20 Device terminating an Ultra DMA data out burst C141 E250 5 163 ...

Page 238: ...reset 2 Master and slave devices are present 2 drives configuration tP Clear Reset Slave device Master device tN DASP PDIAG BSY BSY DASP tQ tR tS Symbol Timing parameter Min Max Unit tM Pulse width of RESET 25 µs tN Time from RESET negation to BSY set 400 ns tP Time from RESET negation to DASP or DIAG negation 1 ms tQ Self diagnostics execution time 30 s tR Time from RESET negation to DASP asserti...

Page 239: ...CHAPTER 6 Operations 6 1 Device Response to the Reset 6 2 Power Save 6 3 Defect Processing 6 4 Read ahead Cache 6 5 Write Cache C141 E250 6 1 ...

Page 240: ...of the DASP signal Then the master device checks a PDIAG signal to see if the slave device has successfully completed the power on diagnostics If the master device cannot confirm assertion of the DASP signal within 500 ms the master device recognizes that no slave device is connected After the slave device device 1 releases its own power on reset state the slave device shall report its presence an...

Page 241: ...ower is turned on 6 1 2 Response to hardware reset Response to RESET hardware reset through the interface is similar to the power on reset Upon receipt of hardware reset the master device checks a DASP signal for up to 500 ms to confirm presence of a slave device The master device recognizes the presence of the slave device when it confirms assertion of the DASP signal Then the master device check...

Page 242: ...conds The asserted PDIAG signal is negated 30 seconds after it is asserted if the command is not received Max 31 sec Max 450 ms Max 30 sec Max 1 ms If presence of a slave device is confirmed PDIAG is checked for up to 31 seconds Checks DASP for up to 500 ms DASP PDIAG BSY bit Reset Status Reg BSY bit Slave device Master device Figure 6 2 Response to hardware reset Note Master Device does not check...

Page 243: ...ence and the result of the self diagnostics to the master device as described below PDIAG signal negated within 1 ms and asserted within 30 seconds The asserted PDIAG signal is negated 30 seconds after it is asserted if the command is not received When the IDD is set to a slave device the IDD asserts the DASP signal when negating the PDIAG signal Max 31 sec Max 30 sec Max 1 ms If the slave device ...

Page 244: ...cs to the master device as described below PDIAG signal negated within 1 ms and asserted within 5 seconds The asserted PDIAG signal is negated 5 seconds after it is asserted if the command is not received If the command is received the PDIAG signal is negated according to timing at which the command is received When the IDD is set to a slave device the IDD asserts the DASP signal when negating the...

Page 245: ...s mode all the electric circuit in the device are active or the device is under seek read or write operation A device enters the active mode under the following conditions The media access system is received 2 Active idle mode In this mode circuits on the device are set to power save mode The device enters the Active idle mode under the following conditions After completion of the command executio...

Page 246: ... low power idle state APM Mode 2 The time specified by the STANDBY or IDLE command has elapsed after completion of the command A reset is issued in the sleep mode When one of following commands is issued the command is executed normally and the device is still stayed in the standby mode Reset hardware or software STANDBY command STANDBY IMMEDIATE command INITIALIZE DEVICE PARAMETERS command CHECK ...

Page 247: ...rnated with the spare area depending on media defect location information The media defect location information is registered in the system space specified for the user area according to the format at shipment of the media from the plant 6 3 1 Spare area The following type of area is prepared as the spare area in user areas 1 Spare cylinder for alternate assignment This cylinder is used during aut...

Page 248: ...rs Figure 6 5 shows an example where sector physical 5 with cylinder 0 and head 0 is defective Sector physical Cylinder 0 Head 0 Defec tive sector Not used 778 779 780 777 778 779 Note When an access request for sector 5 is issued physical sector 6 must be accessed instead of physical sector 5 Figure 6 5 Sector slip processing 2 Track slip processing In this method defective tracks not used there ...

Page 249: ...ot performed If error recovery is not successful even if a write fault error retry is executed automatic alternating processing is performed Figure 6 6 shows an example where automatic alternating processing is applied to sector physical 5 with cylinder 0 and head 0 Sector physical Cylinder 0 Head 0 Defec tive sector Not used Alternate cylinder 0 Head 0 This is assigned to an unassigned sector Alr...

Page 250: ...edia As the result faster data access becomes possible for the host 6 4 1 DATA buffer structure This device contains a data buffer This buffer is divided into two areas one area is used for MPU work and the other is used as a read cache for another command See Figure 6 7 a 2MB buffer 2 097 152 bytes For MPU work For R W command 2 097 152 bytes Figure 6 7 Data buffer structure The read ahead operat...

Page 251: ... caching operation is not performed 2 Data that is a target of caching The data that is a target of caching are as follows 1 Read ahead data that is read from disk media and saved to the data buffer upon completion of execution of a command that is a target of caching 2 Pre read data that is read from disk media and saved to the data buffer before execution of a command that is a target of caching...

Page 252: ...ID COMMAND 1 2Commands that partially invalidate caching data When data in the buffer or on media is overwritten the overwritten data is invalidated READ SECTOR s READ MULTIPLE READ DMA READ SECTOR s EXT READ DMA EXT READ MULTIPLE EXT WRITE SECTOR s WRITE MULTIPLE WRITE DMA WRITE SECTOR s EXT WRITE DMA EXT WRITE MULTIPLE EXT WRITE DMA FUA EXT WRITE MULTIPLE FUA EXT SMART 2 A hard reset is issued o...

Page 253: ...at the requested data reading position Read segment HAP host address pointer DAP disk address pointer 2 During reading of read requested data the request data that has already been read is sent to the host system Read requested data Free space HAP DAP Read requested data is stored until this point 3 When reading of read requested data is completed and transfer of the read requested data to the hos...

Page 254: ...a DAP disk address pointer HAP host address pointer 2 During reading of read requested data the request data that has already been read is sent to the host system Cache valid data Free space Read requested data DAP disk address pointer HAP host address pointer 3 When reading of read requested data is completed and transfer of the read requested data to the host system is completed the read ahead o...

Page 255: ...ived during the read ahead operation a transfer of the read requested data starts while the read ahead operation is in progress 1 An example is the state shown below where the previous read command is executing sequential reading First HAP is set at the location where hit data is stored HAP It is reset to the hit data location for transfers HAP end location of the previous read command DAP end loc...

Page 256: ... LAST LBA 1 HAP is set at the address where partial hit data is stored and Transfer is started Cache valid data Partial hit data HAP host address pointer 2 DAP and HAP are set at the head of Buffer newly allocated and insufficient data is read Read segment HAP host address pointer DAP disk address pointer 3 When reading the read requested data ends and the transmission of the read requested data t...

Page 257: ...d 2 Invalidation of cached data If an error occurs during writing onto media write processing is repeated up to as many times as specified for retry processing If retry fails for a sector because the retry limit is reached automatic alternate sector processing is executed for the sector If the automatic alternate sector processing fails the data in the sector for which automatic alternate sector p...

Page 258: ...disabling Enabling and disabling of the Write Cache function can be set only with the SET FEATURES command The setting does not changed even when the error status is reported The initial setting is stored in the system area of media System area information is loaded whenever the power is turned on 5 Reset response When a reset is received while cached data is stored on the data buffer data of the ...

Page 259: ...s that are targets of write caching are received the host has difficulty determining which command caused the error An error report is not issued to the host if automatic alternating processing for the error is performed normally Therefore the host cannot execute a retry for the unrecoverable error while Write Cache is enabled Be very careful on this point when using this function If a write error...

Page 260: ...This page is intentionally left blank ...

Page 261: ...ifications of the drive do not always correspond to these parameters The BIOS of a PC AT cannot make full use of the physical specifications of these drivers To make the best use of these drives a BIOS that can handle the standard parameters of these drives is required Command Commands are instructions to input data to and output data from a drive Commands are written in command registers Data blo...

Page 262: ...s stopped and circuits other than the interface control circuit are sleeping The drive enters sleep mode when the host issues the SLEEP command Reserved Reserved bits bytes and fields are set to zero and unusable because they are reserved for future standards Rotational delay Time delay due to disk rotation The mean delay is the time required for half a disk rotation The mean delay is the average ...

Page 263: ...om the drive to the host when command execution is ended The status indicates the command termination state VCM Voice coil motor The voice coil motor is excited by one or more magnets In this drive the VCM is used to position the heads accurately and quickly C141 E250 GL 3 ...

Page 264: ...This page is intentionally left blank ...

Page 265: ...ite fault E ECC Error checking and correction ER Error register ERR Error EU European Union F FR Feature register H HA Host adapter HDD Hard disk drive I IDNF ID not found IRQ14 Interrupt request 14 L LED Light emitting diode M MB Mega byte MB S Mega byte per seconds MPU Micro processor unit P PCA Printed circuit assembly PIO Programmed input output R RLL Run length limited RoHS The Restrictions o...

Page 266: ...This page is intentionally left blank ...

Page 267: ...ents of security password 5 101 air filter 4 3 contents of SECURITY SET PASSWORD data 5 93 alternate status register 5 13 alternating processing control block register 5 13 for defective sector 6 10 controller circuit 2 3 4 4 ambient temperature 3 5 CSEL setting 3 12 APM 1 13 5 91 current and power dissipation 1 8 ATA interface 2 3 current attribute value 5 48 attribute ID 5 47 current fluctuation...

Page 268: ...failure threshold value data 5 46 device control register 5 14 device overview 1 1 FR 01h 5 105 device pausing ultra DMA data FR 02h 5 106 out burst 5 161 FR 03h 5 107 device response to reset 6 2 FR 04h 5 108 device specification 1 4 FR C0h 5 59 device terminating ultra DMA data FR C1h 5 59 in burst 5 157 FR C2h 5 59 out burst 5 163 FR C3h 5 59 device head register 5 11 frame 3 3 diagnostic code ...

Page 269: ...e drive 3 11 phases of operation 5 138 physical interface 5 2 physical sector servo configuration on disk surface 4 16 L PIO data transfer 5 149 large capacity 1 2 PIO data transfer timing 5 149 limitation of mounting 3 3 PIO data transferring command from device to host 5 129 load unload function 1 12 location of breather 3 4 PIO data transferring command from host to device 5 132 location of set...

Page 270: ... read write preamplifier PreAMP 4 9 SET MAX ADDRESS EXT 5 118 read ahead cache 6 12 SET MAX FREEZE LOCK 5 108 read ahead cache system 1 3 SET MAX LOCK 5 106 RECALIBRATE 5 20 SET MAX SET PASSWORD 5 105 recommended power off sequence 1 13 SET MAX UNLOCK 5 107 recommended series termination for ultra DMA 5 148 SET MULTIPLE MODE 5 67 shock and vibration 1 10 reliability 1 11 shock and vibration specif...

Page 271: ...ut command 5 143 ultra DMA data burst timing requirement 5 152 ultra DMA data transfer 5 151 ultra DMA feature set 5 137 ultra DMA sender and recipient timing requirement 5 154 ultra DMA termination with pull up or pull down 5 148 unload feature 5 34 UNLOAD IMMEDIATE 5 34 unrecoverable read error 1 12 using read segment buffer 6 15 V VCM current sense resistor CSR 4 14 viterbi detection circuit 4 ...

Page 272: ...This page is intentionally left blank ...

Page 273: ...ral appearance Technical level Organization Clarity Accuracy Illustration Glossary Acronyms Abbreviations Index Comments Suggestions List any errors or suggestions for improvement Page Line Contents Please send this form to the address below We will use your comments in planning future editions Address Fujitsu Learning Media Limited 37 10 Nishikamata 7 chome Oota ku Tokyo 144 0051 JAPAN Fax 81 3 3...

Page 274: ...This page is intentionally left blank ...

Page 275: ...MHW2080AT MHW2060AT MHW2040AT DISK DRIVES PRODUCT MANUAL C141 E250 01EN MHW2080AT MHW2060AT MHW2040AT DISK DRIVES PRODUCT MANUAL C141 E250 01EN ...

Page 276: ......

Page 277: ......

Page 278: ......

Reviews:

No comments