EMA-MB91F467S-LS-176M07
Chapter
5: CPLD
FMEMCU-UG-910070-17
© Fujitsu Microelectronics Europe GmbH
- 22 -
5.2 CPLD
Constraints
NET "ASx" LOC = "P13" ;
NET "BAAx" LOC = "P14" ;
NET "CSx<0>" LOC = "P2" ;
NET "CSx<1>" LOC = "P1" ;
NET "CSx<2>" LOC = "P3" ;
NET "CSx<3>" LOC = "P5" ;
NET "CSx<4>" LOC = "P6" ;
NET "CSx<5>" LOC = "P7" ;
NET "CSx<6>" LOC = "P8" ;
NET "CSx<7>" LOC = "P12" ;
NET "DIR_U400" LOC = "P39" | SLEW = FAST ;
NET "DIR_U401" LOC = "P38" | SLEW = FAST ;
NET "DIR_U404" LOC = "P36" | SLEW = FAST ;
NET "DIR_U405" LOC = "P37" | SLEW = FAST ;
NET "ECSx" LOC = "P32" ;
NET "IORDx" LOC = "P18" ;
NET "IOWRx" LOC = "P19" ;
NET "OEx_U404" LOC = "P34" | SLEW = FAST ;
NET "OEx_U405" LOC = "P33" | SLEW = FAST ;
NET "RDx" LOC = "P44" ;
NET "S401<1>" LOC = "P31" ;
NET "S401<2>" LOC = "P30" ;
NET "S401<3>" LOC = "P29" ;
NET "S401<4>" LOC = "P28" ;
NET "S401<5>" LOC = "P27" ;
NET "S401<6>" LOC = "P23" ;
NET "S401<7>" LOC = "P22" ;
NET "WEx" LOC = "P16" ;
NET "WRx<0>" LOC = "P40" ;
NET "WRx<1>" LOC = "P41" ;
NET "WRx<2>" LOC = "P43" ;
NET "WRx<3>" LOC = "P42" ;
5.3 CPLD programming jumper (J491)
The CPLD is re-configurable by programming via J491. Please refer to
HTU
www.xilinx.com
UTH
for
details and tools for Xilinx CPLD configuration.
J491 pin
Name
1
GND
2
TDO
3
TCK
4
TMS
5
TDI
6
VREF
