D3081, D3131, D3082 (RX900 S1)
Technical Manual
23
Features
3.2.1
CPU Memory Riser (CPUMEMR) configuration
The memory modules are connected to the CPU by a memory buffer named
Millbrook. There are 4 Milbrooks and 8 DDR channels available on the
CPUMEMR to accommodate up to 16 DIMM memory modules. Each Millbrook
has two DDR channels and two DIMM memory modules are connected to each
channel.
The DIMM slot number is defined as 2 characters:
●
First digit ("1" or "2")
Sequence number within the same DDR3 channel
●
Second digit ("A" to "H")
DDR3 channel number on an individual CPUMEMR
Example:
DIMM 1A = DIMM 0, channel 0; DIMM 1B = DIMM 0, channel 0
DIMM 2A = DIMM 1, channel 0; DIMM 2B = DIMM 1, channel 0
Table 2
shows the relation between the DIMM slot number, the Millbrook
identifier, the DDR channel number, and the DIMM memory module number
within the same DDR channel.
DIMM slot
number
Millbrook
identifier
DDR
channel
number
DIMM memory module
number within the
same DDR channel
1H
C
1
0
2H
C
1
1
1G
C
0
0
2G
C
0
1
2E
D
0
1
1E
D
0
0
2F
D
1
1
1F
D
1
0
1D
A
1
0
Table 2: DIMM memory module connection on the CPUMEMR
