Freetech P6F127, Manual

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Mainboard User’s Manual
40 Chipset Features Setup
4.4. Chipset Features Setup
Selecting “Chipset Features Setup” on the main program screen dis-
plays this menu:
CMOS Setup Utility – Copyright (C) 1984 – 2000 Award Software
Advanced Chipset Features
Item Help
Bank 0/1 DRAM Timing SDRAM 8/10ns
Bank 2/3 DRAM Timing SDRAM 8/10ns
Bank 4/5 DRAM Timing SDRAM 8/10ns
DRAM Clock Host CLK
SDRAM Cycle Length 3
Memory Hole Disabled
P2C/C2P Concurrency Enabled
System BIOS Cacheable Disabled
Video RAM Cacheable Disabled
AGP Aperture Size 64M
AGP-4x Mode Enabled
AGP Driving Control Auto
X AGP Driving Value DA
AGP Fast Write Disabled
OnChip USB Enabled
USB Keyboard Support Disabled
OnChip Sound Auto
CPU to PCI Write Buffer Enabled
PCI Dynamic Bursting Enabled
Menu Level
↑ ↑ ↓ ↓ → → ← ← : MoveEnter : Select +/-/PU/PD:Value: F10: Save ESC: Exit F1:General Help
F5:Previous Values F6:Fail-Safe Defaults F7:Optimized Defaults
Figure 4-4: Chipset features setup
This screen controls the board’s chipset settings. All entries related to
the DRAM timing on the screen are automatically configured. Do not
make any changes unless you are familiar with the chipset.
Bank 0/1 2/3 4/5 DRAM Timing: This item allows you to select the
value in the field, depending on whether the board has paged
DRAMs or EDO (extended data output) DRAMs. The following op-
tions are allowed:
•
FP/EDO 70ns
•
FP/EDO 60ns
•
Normal
•
Medium
•
Fast
•
Turbo