BIOS Configuration
Advanced Chipset Features
39
SDRAM RAS-to-CAS Delay:
This sets the relative delay between
the Row Address Strobe (RAS) and the Column Address Strobe
(CAS). Options are “2” and “3” (default).
SDRAM RAS Precharge Time:
Defines the length of time that the
Row Address Strobe (RAS) is allowed to pre-charge. Options are “2”
and “3” (default).
System BIOS Cacheable:
When set to “Enabled” (default), the Sys-
tem BIOS will be cached for faster execution.
Video BIOS Cacheable:
When set to “Enabled,” the graphics card’s
local memory will be cached for faster execution. The default setting
is “Disabled.”
Memory Hole At 15M-16M:
If Set to “Enabled”, when the system
memory size is equal to or greater than 16M bytes, the physical
memory address from 15M to 16M will be passed to PCI or ISA and
there will be a 1 MB hole in your system memory. This option is de-
signed for some OS with special add-in cards which need 15-16 MB
memory space. The default setting is “Disabled.”
CPU Latency Timer:
This item sets a timing parameter for CPU ac-
cess. Since the CPU timing is determined by the system hardware,
leave this item at the default value.
Delayed Transaction:
The chipset has an embedded 32-bit posted
write buffer to support delay transactions cycles. Enable to support
compliance with PCI specification version 2.1. The default is “En-
abled.”
AGP Graphics Aperture Size:
This option determines the effective
size of the AGP Graphic
Aperture
, where memory-mapped graphic
data structures are located.
Display Cache Frequency:
This item sets the frequency for the sys-
tem memory bus. If you have installed 133 MHz memory, you can
change the frequency to 133 MHz.
System Memory Frequency:
This item sets the main memory fre-
quency. When you use an external graphics card, you can adjust this
to enable the best performance for your system.
Summary of Contents for P6F125
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