Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
21-88
Freescale Semiconductor
External Memory Controller (EMC)
21.5.1.2
Peripheral Hierarchy on the External Memory Controller
To achieve high bus speed interfaces for synchronous SRAMs or SDRAMs, a hierarchy of the
memories/peripherals connected to the EMC is suggested.
shows an example of such a
hierarchy.
Figure 21-50. External Memory Controller Peripheral Hierarchy
The multiplexed address and data bus sees the capacitive loading of the data pins of the fast SDRAMs or
synchronous SRAMs, plus one load for an address latch, plus one load for a buffer to the slow memories.
The loadings of all other memories and peripherals are hidden behind the buffer and the latch. The system
designer needs to investigate the loading scenario and ensure that I/O timings can be met with the loading
determined by the connected components.
Muxed Address and Data
Unmuxed Address
LA[2:0]
LAD[23:0]
LALE
LBCTL
EMC
Latch
Buffer
DQ
SDRAM
A
DQ
SSRAM
D
Q
LE
A
DIR
B
LAD[23:3]
LAD[23:3]
D[23:0]
A[MLB-1:11]+A[9:0]
LSDA10
A10
Slower memories
and peripherals
Buffered Data
A
DQ