MPC8572E Advanced Mezzanine Card Hardware Getting Started Guide, Rev. 1.0
Freescale Semiconductor
11
Module Management Support
SW5
SW5.1
ON
[SW5.1:2] = ON:ON. CCB:SYSCLK = 4:1 (266 MHz)
[SW5.1:2] = OFF:ON. CCB:SYSCLK = 8:1 (533 MHz)
[SW5.1:2] = ON:OFF. CCB:SYSCLK = 10:1 (666 MHz)
1
[SW5.1:2] = OFF:OFF. CCB:SYSCLK = 12:1 (800 MHz)
SW5.2
OFF
SW5.3
OFF
[SW5.3:4] = ON:ON. e500 Core #0:CCB = 1.5:1
[SW5.3:4] = OFF:ON. e500 Core #0:CCB = 2:1
1
[SW5.3:4] = ON:OFF. e500 Core #0:CCB = 2.5:1
[SW5.3:4] = OFF:OFF. e500 Core #0:CCB = 3.5:
SW5.4
ON
SW5.5
OFF
[SW5.5:6] = ON:ON. e500 Core #1:CCB = 1.5:1
[SW5.5:6] = OFF:ON. e500 Core #1:CCB = 2:1
1
[SW5.5:6] = ON:OFF. e500 Core #1:CCB = 2.5:1
[SW5.5:6] = OFF:OFF. e500 Core #1:CCB = 3.5:1
SW5.6
ON
SW5.7
OFF
[SW5.7:8] = ON:ON. Boot ROM Location = PCI-Express
[SW5.7:8] = OFF:ON. Boot ROM Location = Serial RapidIO
[SW5.7:8] = ON:OFF. Boot ROM Location = DDR Memory
[SW5.7:8] = OFF:OFF. Boot ROM Location = 32-bit Local FLASH Memory
1
SW5.8
OFF
SW500
SW500.1
ON
[SW500.1:3]=ON:ON:ON.DDR Clock Ratio = 3:1 DDRCLK (200 MHz)
[SW500.1:3]=OFF:ON:ON.DDR Clock Ratio = 4:1 DDRCLK (266 MHz)
[SW500.1:3]=ON:OFF:ON.DDR Clock Ratio = 6:1 DDRCLK (400 MHz)
[SW500.1:3]=OFF:OFF:ON.DDR Clock Ratio = 8:1 DDRCLK (533 MHz)
[SW500.1:3]=ON:ON:OFF.DDR Clock Ratio = 10:1 DDRCLK (666 MHz)
1
[SW500.1:3]=OFF:ON:OFF.DDR Clock Ratio = 12:1 DDRCLK (800 MHz)
[SW500.1:3]=ON:OFF:OFF. RESERVED
[SW500.1:3]=OFF:OFF:OFF.DDR Clock Ratio = SYNCHRONOUS
SW500.2
ON
SW500.3
OFF
SW500.4
OFF
[SW500.4:5] = ON:ON. MPC8572E acts as agent on all interfaces
[SW500.4:5] = OFF:ON. MPC8572E acts as end point on PCIE #1 host
[SW500.4:5] = ON:OFF. MPC8572E acts as end point on SRIO & PCIE #1 host
[SW500.4:5] = OFF:OFF. MPC8572E acts as the host processor
1
SW500.5
OFF
SW500.6
ON
[SW500.6:8] = OFF:ON:ON. IO Port Selection = SRIO 100-MHz clock, 2.5 Gbps (x4)
[SW500.6:8] = ON:OFF:ON. IO Port Selection = SRIO/PCIE 100-MHz clock, 2.5 Gbps
[SW500.6:8] = OFF:OFF:ON. IO Port Selection = SRIO/PCIE 100-MHz clock, 1.25/2.5 Gbps (x4)
[SW500.6:8] = OFF:ON:OFF. IO Port Selection = SRIO 100-MHz clock, 1.25 Gbps (x4)
[SW500.6:8] = ON:ON:OFF. IO Port Selection = SRIO 125 MHz, 3.125 Gbps (x4)
1
SW500.7
ON
SW500.8
OFF
SW501
SW501.1
OFF
[SW501.1] = ON Boot Sequence Configuration = Boot Sequencer Enabled
[SW501.1] = OFF Boot Sequence Configuration = Boot Sequencer Disabled
SW501.2
OFF
CPU Boot Config:
[SW501.2:3] = ON:ON.CPU boot hold-off both cores
[SW501.2:3] = OFF:ON. E500 Core 0 allowed to boot, Core 1 in boot hold-off
1
[SW501.2:3] = ON:OFF. E500 Core 1 allowed to boot, Core 0 in boot hold-off
[SW501.2:3] = OFF:OFF. Both cores boot without external master
SW501.3
ON
Table 6. Complete Switch Settings (continued)
Feature
Default Settings
[OFF = 1, ON = 0)
Comments
