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MPC8572E Advanced Mezzanine Card Hardware Getting Started Guide, Rev. 1.0

Freescale Semiconductor

11

 

Module Management Support

SW5

SW5.1

ON

[SW5.1:2] = ON:ON. CCB:SYSCLK = 4:1 (266 MHz)
[SW5.1:2] = OFF:ON. CCB:SYSCLK = 8:1 (533 MHz)
[SW5.1:2] = ON:OFF. CCB:SYSCLK = 10:1 (666 MHz)

1

[SW5.1:2] = OFF:OFF. CCB:SYSCLK = 12:1 (800 MHz)

SW5.2

OFF

SW5.3

OFF

[SW5.3:4] = ON:ON. e500 Core #0:CCB = 1.5:1
[SW5.3:4] = OFF:ON. e500 Core #0:CCB = 2:1

1

[SW5.3:4] = ON:OFF. e500 Core #0:CCB = 2.5:1
[SW5.3:4] = OFF:OFF. e500 Core #0:CCB = 3.5:

SW5.4

ON

SW5.5

OFF

[SW5.5:6] = ON:ON. e500 Core #1:CCB = 1.5:1
[SW5.5:6] = OFF:ON. e500 Core #1:CCB = 2:1

1

[SW5.5:6] = ON:OFF. e500 Core #1:CCB = 2.5:1
[SW5.5:6] = OFF:OFF. e500 Core #1:CCB = 3.5:1

SW5.6

ON

SW5.7

OFF

[SW5.7:8] = ON:ON. Boot ROM Location = PCI-Express
[SW5.7:8] = OFF:ON. Boot ROM Location = Serial RapidIO
[SW5.7:8] = ON:OFF. Boot ROM Location = DDR Memory
[SW5.7:8] = OFF:OFF. Boot ROM Location = 32-bit Local FLASH Memory

1

SW5.8

OFF

SW500

SW500.1

ON

[SW500.1:3]=ON:ON:ON.DDR Clock Ratio = 3:1 DDRCLK (200 MHz)
[SW500.1:3]=OFF:ON:ON.DDR Clock Ratio = 4:1 DDRCLK (266 MHz)
[SW500.1:3]=ON:OFF:ON.DDR Clock Ratio = 6:1 DDRCLK (400 MHz)
[SW500.1:3]=OFF:OFF:ON.DDR Clock Ratio = 8:1 DDRCLK (533 MHz)
[SW500.1:3]=ON:ON:OFF.DDR Clock Ratio = 10:1 DDRCLK (666 MHz)

1

[SW500.1:3]=OFF:ON:OFF.DDR Clock Ratio = 12:1 DDRCLK (800 MHz)
[SW500.1:3]=ON:OFF:OFF. RESERVED
[SW500.1:3]=OFF:OFF:OFF.DDR Clock Ratio = SYNCHRONOUS

SW500.2

ON

SW500.3

OFF

SW500.4

OFF

[SW500.4:5] = ON:ON. MPC8572E acts as agent on all interfaces
[SW500.4:5] = OFF:ON. MPC8572E acts as end point on PCIE #1 host
[SW500.4:5] = ON:OFF. MPC8572E acts as end point on SRIO & PCIE #1 host
[SW500.4:5] = OFF:OFF. MPC8572E acts as the host processor

1

SW500.5

OFF

SW500.6

ON

[SW500.6:8] = OFF:ON:ON. IO Port Selection = SRIO 100-MHz clock, 2.5 Gbps (x4)
[SW500.6:8] = ON:OFF:ON. IO Port Selection = SRIO/PCIE 100-MHz clock, 2.5 Gbps
[SW500.6:8] = OFF:OFF:ON. IO Port Selection = SRIO/PCIE 100-MHz clock, 1.25/2.5 Gbps (x4)
[SW500.6:8] = OFF:ON:OFF. IO Port Selection = SRIO 100-MHz clock, 1.25 Gbps (x4)
[SW500.6:8] = ON:ON:OFF. IO Port Selection = SRIO 125 MHz, 3.125 Gbps (x4)

1

SW500.7

ON

SW500.8

OFF

SW501

SW501.1

OFF

[SW501.1] = ON Boot Sequence Configuration = Boot Sequencer Enabled
[SW501.1] = OFF Boot Sequence Configuration = Boot Sequencer Disabled

SW501.2

OFF

CPU Boot Config:
[SW501.2:3] = ON:ON.CPU boot hold-off both cores
[SW501.2:3] = OFF:ON. E500 Core 0 allowed to boot, Core 1 in boot hold-off

1

[SW501.2:3] = ON:OFF. E500 Core 1 allowed to boot, Core 0 in boot hold-off
[SW501.2:3] = OFF:OFF. Both cores boot without external master

SW501.3

ON

Table 6. Complete Switch Settings (continued)

Feature

Default Settings

[OFF = 1, ON = 0)

Comments

Summary of Contents for MPC8572E

Page 1: ...debugger are beyond the scope of this document Required Reading It is assumed that the reader is familiar with the MPC8572E microprocessor and MPC8572E PowerQUICC III Integrated Host Processor Family...

Page 2: ...ground debugging mode CCB Core complex bus COP Computer operating properly CPLD Complex programmable logic device DIP Dual in line package DSP Digital signal processor DUART Dual universal asynchronou...

Page 3: ...Dual In line Package DIP switches SW4 SW5 SW500 and SW501 and eight jumper headers J1 J7 and HD1 The default DIP switch positions provide Power On Reset configuration values for the MPC8572EAMC board...

Page 4: ...ndary Side Switch Positions Table 2 Default Switch Settings Feature Default Settings OFF 1 ON 0 Comments SW4 SW4 1 OFF Reserved SW4 2 OFF Reserved SW4 3 OFF Reserved SW4 4 ON SW4 4 MMC H W Select ON M...

Page 5: ...ation Boot Sequencer Disabled SW501 2 OFF CPU Boot Config SW501 2 3 OFF ON E500 Core 0 allowed to boot Core 1 in boot hold off SW501 3 ON SW501 4 ON RIO System Size SW501 4 ON Large system size up to...

Page 6: ...e card is inserted the correct way An example is shown in Figure 3 Figure 3 Inserting the MPC8572EAMC into a Chassis 3 Perform Initial Board Power Up and Check LEDs A complete list of all LEDs on the...

Page 7: ...AMC SERDES LOS D504 Orange Loss of signal No loss of signal Port 1 AMC SERDES Ethernet Tx activity D505 Yellow Tx Ethernet activity No Tx Ethernet activity Port 1 AMC SERDES Ethernet Rx activity D506...

Page 8: ...connected to the MPC8572EAMC Note the orientation of pin 1 red edge of ribbon cable with pin 1 on J4 3 Switch on power to the board 4 Check for completion of the reset sequence see step 3 and power i...

Page 9: ...en reconnected Any board settings that users wish to make should be checked for validity against a recent version of the MPC8572E PowerQUICC III Integrated Host Processor Family Reference Manual Opera...

Page 10: ...Extract the hot swap handle 2 The BLUE LED flashes and then stays ON 3 When the BLUE LED is ON the AdvancedMC can be removed from the chassis Figure 6 Hot Swapping in a Chassis NOTE While the chassis...

Page 11: ...666 MHz 1 SW500 1 3 OFF ON OFF DDR Clock Ratio 12 1 DDRCLK 800 MHz SW500 1 3 ON OFF OFF RESERVED SW500 1 3 OFF OFF OFF DDR Clock Ratio SYNCHRONOUS SW500 2 ON SW500 3 OFF SW500 4 OFF SW500 4 5 ON ON M...

Page 12: ...ory Table 7 provides a revision history for this getting started guide SW501 4 ON RIO System Size SW501 4 ON Large system size up to 65 536 devices1 SW501 4 OFF Small system size up to 256 devices Not...

Page 13: ...MPC8572E Advanced Mezzanine Card Hardware Getting Started Guide Rev 1 0 Freescale Semiconductor 13 Revision History THIS PAGE INTENTIONALLY LEFT BLANK...

Page 14: ...MPC8572E Advanced Mezzanine Card Hardware Getting Started Guide Rev 1 0 14 Freescale Semiconductor Revision History THIS PAGE INTENTIONALLY LEFT BLANK...

Page 15: ...MPC8572E Advanced Mezzanine Card Hardware Getting Started Guide Rev 1 0 Freescale Semiconductor 15 Revision History THIS PAGE INTENTIONALLY LEFT BLANK...

Page 16: ...less against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthori...

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