Freescale Semiconductor MPC5632M, Manual

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MPC563XM Reference Manual, Rev. 1
394 Freescale Semiconductor
Preliminary—Subject to Change Without Notice
access), the EBI errors the access on the internal bus and does not start the access (nor assert TEA)
externally.
Table 13-26 shows which external transfers are generated by the EBI for the misaligned access cases in
Table 13-25 , for each port size.
The number of external transfers for each internal AHB master request is determined by the HSIZE value
for that request relative to the port size. For example, a half-word write to @0x3 (misaligned case #4) with
16-bit port size results in 4 external 16-bit transfers because the transfer granularity of 32 bits. For cases
where two or more external transfers are required for one internal transfer request, these external accesses
are considered part of a "small access" set, as described in
Section 13.5.2.6, “Small Accesses (Small Port
Size and Short Burst Length) .
Since all transfers are aligned on the external bus, normal timing diagrams and protocol apply. Note that
the TSIZ[0:1] signals are not intended to be used for misaligned accesses, so they are not specified in
Table 13-26 .
Table 13-25. Misalignment Cases Supported by a 32 bit AMBA EBI (internal bus)
#
1
1
Misaligned case number. Only transfers where HUNALIGN=1 are numbered as misaligned cases. The
missing case numbers cannot occur on a 32 bit AMBA implementation.
Program Size and
byte offset
Address
[30:31]
2,3
2
Address on internal master AHB bus, not necessarily address on external ADDR pins.
3
Address Z is incremented by one 32 bit word compared to previous access on the AMBA bus.
Data Bus Byte Strobes
4
4
Internal byte strobe signals on AHB bus. Shown with Big-Endian byte ordering in this table, even though
internal master AHB bus uses Little-Endian byte-ordering (EBI flips order internally).
HSIZE
5
5
Internal signal on AHB bus; 00=8-bits, 01=16 bits, 10=32 bits. HSIZE is driven according to the smallest
aligned container that contains all the requested bytes. This results in extra EBI external transfers in some
cases.
HUNALIGN
6
6
Internal signal on AHB bus that indicates that this transfer is misaligned (when 1).
1 Half @0x1 01 0110 10 1
4
-
Half @0x3
(2 AHB transfers)
11
z00
0001
1000 01
7
00
7
For this case, the EBI internally treats HSIZE as 00 (1-byte access).
1
0
8 Word @0x1
(2 AHB transfers)
01 0111
1000 10
00 1
0
9 Word @0x2
(2 AHB transfers)
10 0011
1100 10
01 1
0
10
11 Word @0x3
(2 AHB transfers)
11
z00
0001
1110 10
7
10
1
1
Table 13-26. Misalignment Cases Supported by a 32 bit AMBA EBI (external bus)
#
1
PS
2
Program Size
and byte offset
ADDR[30:31]
3,4
WE_BE[0:3]
5
1 0 Half @0x1 00 1001
1 00
10 1011
0111