JP2 - I2C Boot ROM Enable
DSPAUDIOEVM Users Guide, Rev. 2.4
This document contains information on a new product. Specifications and information herein are subject ot change without notice.
Freescale Semiconductor
13
4.5.9
JP11 - SDO4/SDI1 Configuration
This jumper set controls the input source for SDI1. A jumper in the N position feeds the SDI1 signal from the AKM 4114 S/PDIF receiver. A
jumper in the O position feeds the SDI1 signal from ADC1. There is no available jumper setting for use of the SDO4 signal.
4.5.10
JP12 - Master Clock Configuration Control
This set of jumpers allows for numerous routing options of the master clock. A jumper in the P position feeds the master clock from the
AKM4114 SPDIF receiver to the ESAI HCKT, HCKR and ACI pins as well as the AKM4114 SPDIF transmitter, ADC, DAC1-3 and DAC4-6.
A jumper in the R position connects/shorts the HCKT_1 signal to the HCKT, HCKR and ACI signals. Jumper positions P and R may be used
together to feed the AKM4114 SPDIF master clock to the HCKT_1 input. Jumper position Q is reserved for future expansion.
4.5.11
JP13 - SPDIF Lock LED Source Select
This jumper set controls the source for the SPDIF lock LED, D6, on the motherboard. A jumper in location T allows connects LED, D6, to
the AKM4114 lock signal output. Jumper position S is reserved for future expansion.
4.5.12
JP14 - SPDIF Lock Connection
This jumper connects the AKM4114 lock signal to GPIO signal PF6 if jumper set JP13 has a jumper in location T.
4.6
JP2 - I
2
C Boot ROM Enable
This set of jumpers allows the on-board serial EEPROM to be removed from the SHI bus. Jumper location V connects the serial data line to
the DSP MISO signal and location W connects the serial clock line to the DSP SCK signal. Both jumpers must be placed to use bootstrap
mode 9.
4.7
P1 - ESAI Receive In
This header allows for external connections to ESAI and ESAI_1 receiver signals and GPIO. The odd row is ground while the even row of
pins is signal. This provides ground isolation between each signal when used with ribbon cable connectors.
4.8
P2 - ESAI Transmit Out
This header allows for external connections to ESAI and ESAI_1 transmitter signals and GPIO. The odd row is ground while the even row of
pins is signal. This provides ground isolation between each signal when used with ribbon cable connectors.
