Table Of Contents
Paragraph
Page
Number
Number
DSPAUDIOEVM Users Guide, Rev. 2.4
This document contains information on a new product. Specifications and information herein are subject ot change without notice.
TOC-2
Freescale Semiconductor
3.5.1
TIO0 – Timmer Port .............................................................................................................................................. 9
3.5.2
JP1 - Synchronous/Asynchronous Clock Control .................................................................................................. 9
3.5.3
JP2 – Single/Double Speed Clocking Control .....................................................................................................10
3.5.4
JP3 - FST_1 Connection ......................................................................................................................................10
3.5.5
JP4 – SCKT_1 Connection ..................................................................................................................................10
3.5.6
JP5 - FSR_1 Connection ......................................................................................................................................10
3.5.7
JP6 - SCKR_1 Connection ...................................................................................................................................10
3.5.8
JP7 - DSP MUTE Control ....................................................................................................................................10
3.5.9
JP8 - INT_0/SPDIF Error Flag Connection .........................................................................................................10
3.5.10
JP9 - SDO5/SDI0 Configuration .........................................................................................................................10
3.5.11
JP10 SDO4/SDI1 Configuration ..........................................................................................................................10
Chapter 4 DSP56371 DAUGHTERBOARD
4.1
DSPX37XDB1 ...........................................................................................................................................................11
4.2
Mode Selection ...........................................................................................................................................................11
4.3
Memory ......................................................................................................................................................................11
4.4
JP1 - Clock Selection .................................................................................................................................................11
4.5
Daughterboard Audio I / O and Clock Control Header ..............................................................................................12
4.5.1
JP3 - Synchronous/Asynchronous Clock Control ................................................................................................12
4.5.2
JP4 – Single/Double Speed Clocking Control .....................................................................................................12
4.5.3
JP5 - DSP MUTE Control ....................................................................................................................................12
4.5.4
JP6 - FSR_1 Connection ......................................................................................................................................12
4.5.5
JP7 - SCKR_1 Connection ...................................................................................................................................12
4.5.6
JP8 - SCKT_1 Connection ...................................................................................................................................12
4.5.7
JP9 - FST_1 Connection ......................................................................................................................................12
4.5.8
JP10 - SDO5/SDI0 Configuration .......................................................................................................................12
4.5.9
JP11 - SDO4/SDI1 Configuration .......................................................................................................................13
4.5.10
JP12 - Master Clock Configuration Control ........................................................................................................13
4.5.11
JP13 - SPDIF Lock LED Source Select ..............................................................................................................13
4.5.12
JP14 - SPDIF Lock Connection ..........................................................................................................................13
4.6
JP2 - I2C Boot ROM Enable ......................................................................................................................................13
4.7
P1 - ESAI Receive In .................................................................................................................................................13
4.8
P2 - ESAI Transmit Out .............................................................................................................................................13
Chapter 5 DSP56374 Daughterboard
5.1
DSPX374DB1 ............................................................................................................................................................14
5.2
Mode Selection ...........................................................................................................................................................14
5..3
Memory ......................................................................................................................................................................14
5.4
JP12 – Clock Selection ...............................................................................................................................................14
5.5
Daughterboard Audio I/O and Clock Control Header ................................................................................................15
5.5.1
JP1 – Synchronous/Asynchronous Clock Control ...............................................................................................15
5.5.2
JP2 – Single/Double Speed Clocking Control .....................................................................................................15
5.5.3
JP3 – FSR_1 Connection .....................................................................................................................................15
5.5.4
JP4 – SCKR_1 Connection ..................................................................................................................................15
5.5.5
JP5 – SDO5/SDI0 Configuration .........................................................................................................................15
5.5.6
JP6 – SDO4/SDI1 Configuration .........................................................................................................................15
5.5.7
JP7 – Watchdog Timer Connection .....................................................................................................................15
5.5.8
JP8 – SD03/SDI2 Configuration ..........................................................................................................................15
5.5.9
JP9 – FST/FST_1 Selection .................................................................................................................................16
5.5.10
JP10 – SCKT/SCKT_1 Selection ........................................................................................................................16
5.5.11
JP11 – DSP Mute Control ...................................................................................................................................16
5.5.12
JP13 – I2C Boot ROM Enable .............................................................................................................................16
