Daughterboard Audio I/O and Clock Control Header
DSPAUDIOEVM Users Guide, Rev. 2.4
This document contains information on a new product. Specifications and information herein are subject ot change without notice.
Freescale Semiconductor
15
5.5
Daughterboard Audio I/O and Clock Control Header
5.5.1
JP1 – Synchronous/Asynchronous Clock Control
This jumper set controls whether or not the DSP is in synchronous or asynchronous mode. Position A allows the DSP GPIO (pin PG7) to
choose the mode. Position B forces the mode to be asynchronous and no jumper forces synchronous mode. In synchronous mode FST is
connected to FSR and SCKT is connected to SCKR on the ESAI port of the DSP.
5.5.2
JP2 – Single/Double Speed Clocking Control
This jumper pair controls whether or not the motherboard is in single or double speed mode. Position C forces the motherboard into double
speed mode. Position D allows the DSP GPIO (pin PG6) to control the mode and no jumper forces single speed mode. This jumper is useful
when implementing a DTS 96/24 decoder.
5.5.3
JP3 – FSR_1 Connection
This jumper connects/shorts the FSR and FSR_1 signals together. No jumper means that the FSR_1 signal stops at header P1.
5.5.4
JP4 – SCKR_1 Connection
This jumper connects/shorts the SCKR and SCKR_1 signals together. No jumper means that the SCKR_1 signal stops at header P1.
5.5.5
JP5 – SDO5/SDI0 Configuration
This jumper pair controls the input source for SDI0. A jumper in position G feeds the SDI0 signal from the AKM 4114 S/PDIF receiver. A
jumper in position H feeds the SDI0 signal from ADC1. There is no available jumper setting for use of the SDO5 signal.
5.5.6
JP6 – SDO4/SDI1 Configuration
This jumper set controls the signal connections of SDO4/SDI1. Depending on the ESAI configuration in the DSP, this signal can be configured
as an output (SDO4) or an input (SDI1). A jumper in position I feeds the SDI1 signal from ADC1. A jumper in position J feeds the SDO4
signal to DAC4-6.
5.5.7
JP7 – Watchdog Timer Connection
This jumper connects the on-chip watchdog timer output to the DSP reset circuit. By placing a jumper in position K the on-chip watchdog
timer can generate a hardware reset to the DSP. If no jumper is placed the watchdog timer is removed from the reset circuit.
5.5.8
JP8 – SD03/SDI2 Configuration
This jumper pair controls the signal connections of SDO3/SDI2. Depending on the ESAI configuration in the DSP, this signal can be
configured as an output (SDO3) or an input (SDI1). A jumper in position L feeds the SDI1 signal from the ADC2 microphone source. A
jumper in position M feeds the SDO3 signal to DAC 4-6.
Table 5-2. Daughterboard Audio I/O and clock Control Header
SYNC/ASYNC
SNG
/DBL
FSR_1
SCKR_
1
SD
05/
SD
10
SD
04/
SD
11
WDT/RESET
SD
03/
SD
12
FS
T
_
1
FST
SCKT_
1
SCKT
DS
P
MU
T
E
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
JP1
JP2
JP3
JP4
JP5
JP6
JP7
JP8
JP9
JP10
JP11
