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Memory Configuration
► Memory Features / ECC Configuration
Press <Enter> to go to its submenu.
► DRAM Clock Mode
This option is used to configuation Memory Frequency,Timings and Subtimings. Setting values
are: [Auto], [Limit],[Manual].
[Auto]: DRAM SPD profile1;
[Limit]: DRAM SPD profile2;
[Manual]: DRAM by Manual.
► DRAM Voltage Offset
This option is used to change the DRAM voltage in a step of 50mV. The voltage can be incre
-
mented from +50mV to +600mV.
► DRAM Timing Mode
When both DCTs (DRAM controller) are enabled in unganged mode, BIOS must initialize the
frequency of each DCT in order, you also can configure the timings manually.
Settings are : [Auto], [Both].[Both] will appear only in AM2+ CPU.
► tCL (CAS Latency)
The number of memory clocks it takes a DRAM to return data after the read CAS_L is assert-
ed depends on the memory clock frequency. The value that BIOS programs into the memory
controller is a function of the target clock frequency. The target clock frequency is determined
from the supported CAS latencies at given clock frequencies of each DIMM.
► tRCD (RAS-to-CAS Delay)
This item allows you to select a delay time (in clock cycles) between the CAS# and RAS#
strobe signals.
► tRP (Precharge Command Period)
This item allows you to select the row precharge time (in clock cycles).
► tRAS (Active-to-Precharge Delay)
This item allows you to set the minimum RAS# active time (in clock cycles).
► tRTP (Internal Read to Precharge Command Delay)
Internal READ Command to PRECHARGE Command delay
CMOS Setup Utility - Copyright (C) 1985-2009, American Megatrends, Inc.
Memory Configuration
► Memory Features
Help Item
► ECC Configuration
[Press Enter]
DRAM Clock Mode [Auto] Adjust the CPUs
DRAM Voltage Offset [+100mV]
Integrated Memory
Current DRAM Voltage :1.920 V (+100mV)
Controller
Target DRAM Voltage
:1.920 V (+100mV)
DRAM Timing Mode [Auto]
↑↓←→:Move Enter:Select +/-/:Value F10:Save ESC:Exit F1:General Help
F2/F3:Change Colors
F9:Optimized Defaults
[Press Enter]
