FS453/4 AND FS455/6
DATA SHEET: HARDWARE REFERENCE
9. Component Placement
This section gives guidelines for the placement and layout of components associated with the FS453.
A printed circuit board (PCB) with a minimum of four layers is recommended for all designs utilizing the
FS453. We recommend that layers 1 (top) and 4 (bottom) are used for signals, and that layers 2 and 3
are used for power and ground respectively. This provides the designer with ample access to all system
traces and eases the process of manual design modification.
Place components associated with the FS453 as close as possible to their respective pins. Locate the
FS453 near the power supply connector, the video input connector, and the video output connector.
Place the FS453 above a solid ground plane to shield EMI radiation. Additionally, do not route signal
traces under the FS453.
9.1 Power/Ground
9.1.1 Power
To meet standard CMOS device voltage specifications, the FS453 can be powered by +3.3 Volts. In
addition, the digital core of the chip can be powered by +1.8 Volts. However, since 5 Volt systems are
still common, the FS453 can tolerate up to 5 Volt inputs.
If the switching power supply noise is greater than or equal to 200 mV, use a linear regulator to filter the
analog power supply. It is best not to use unfiltered switching power supplies because they can produce
substantial amounts of electrical noise. Excess electrical noise can induce visible artifacts on analog
video signals, and should be avoided at all costs. To minimize electrical noise, always provide sufficient
filtering and high frequency bypassing on the power supplies. This will insure better video quality and
reduce EMI radiation.
Within the FS453, separate power is routed to each functional section of the die, including the phase
locked loops, D/A converters, digital processors and digital drivers.
Segregate the power pins into analog
and digital power planes. Use separate voltage regulators for analog and digital power. It is important to
isolate the analog plane from any electrical noise generated by the digital plane. We recommend
isolating each power supply section from its respective voltage regulator with a series inductor/ferrite
bead and a 4.7
µ
F capacitor connected to ground. The ferrite bead filters high frequency switching noise,
while the 4.7
µ
F capacitor filters low-frequency power supply ripple and acts as a reservoir for heavy
currents drawn by D/A converters.
Make sure you apply clean analog power to the V
DD_PA
, V
DD_OSC
, and V
DD_DA
pins. For high-frequency
power supply noise rejection, place a 0.1
µ
F capacitor adjacent to each group of pins. To reduce the
lead inductance, locate all capacitors as close as possible to the device and use the shortest possible
leads (consistent with reliable operation). Chip capacitors are best for minimizing lead inductance. If
necessary, you can substitute radial lead ceramic capacitors since they
are better than axial lead
capacitors for self-resonance. Chip capacitors are also recommended for power supply decoupling.
Connect these capacitors as close to their respective power and ground pins as possible, using short and
wide traces to minimize lead inductance. When two or more 0.1
µ
F bypass capacitors are adjacent,
consider exchanging one of them with a 100pF to 1000pF capacitor to reduce higher frequency noise
from the power supply. Figure 11 on page 31 shows the recommended power filter networks.
JANUARY, 2005, VERSION 3.0
30
COPYRIGHT
©
2003-4 FOCUS ENHANCEMENTS, INC.
FOCUS Enhancements Semiconductor
