FS453/4 AND FS455/6
DATA SHEET: HARDWARE REFERENCE
The recommended network shown in Figure 12 on page 33 will deliver robust video quality. It
incorporates a source-terminating 75 Ohm resistor and a filter tuned for 37.5 Ohm impedance (assuming
a matching 75 Ohm terminating resistor at the load). Table 10 below shows the correct component
values to use for typical Standard and High Definition Television applications. For applications that utilize
both HDTV and SDTV outputs, place HDTV filters on DACs A, B, & C and an SDTV filter on DAC D. Use
DAC D for SDTV composite video, and the other DACs for all other video formats.
Output Filters
CA
LB
CC
SDTV
270p
F
1.8uH 330p
F
HDTV
47pF 330n
H
68pF
Table 10: Output Filter Component Values
9.4 CLOCK/OSCILLATOR
9.4.1 Reference Crystal Oscillator
The quality of the image produced by the FS453
is directly related to the quality of the reference clock
input to the chip. The FS453 can use either a dedicated external oscillator or the internal oscillator circuit
with an inexpensive crystal as its reference clock. The reference clock must exhibit 50 parts per million
(ppm) or better frequency tolerance (30 ppm preferred), and poses low jitter characteristics.
Any jitter or frequency deviation of the oscillating circuit will be transferred directly to the encoder’s color
subcarrier. Jitter within the valid clock cycle interval will result in hue noise on the color subcarrier on the
order of 0.9-1.6 degrees per nanosecond. Random hue noise can result in degradation in the AM/PM
noise ratio (typically around 40dB for consumer media such as videodiscs and VCRs). Periodic or
coherent hue noise can result in differential phase error (which is limited to 10 degrees by FCC cable TV
standards).
Any frequency deviation of the clock signal from nominal will challenge the subcarrier tracking capability
of the destination receiver. This may range from a few ppm for broadcast equipment to a few hundred
ppm for consumer equipment. Crystal based clock sources with a maximum total deviation of 30 ppm
across the temperature range of 0 C to 70 C will produce the best results for consumer and industrial
applications. Any clock interruption (even during vertical blanking interval) which results in misregistration
of the clock input, or nonstandard pixel counts per line, can cause phase excursions outside the NTSC
limit of +/- 40 degrees.
When using the internal oscillator circuit, you must meet the following conditions to ensure that the FS453
encoder operates properly. The crystal must be specified at 27.000 MHz +/- 50 ppm in parallel
resonance (not series resonance). The external load capacitance needs to be equal to the specified
capacitance value of the crystal. External load capacitors should have their ground connection very close
to the FS453. A variable cap may be used to tune the external load capacitors. Since the crystal
generates a timing reference for the FS453 encoder, it is important that electrical noise not couple into
the circuit. Do not route traces with fast edge transition rates under or adjacent to these pins. Place the
oscillating circuit as close as possible to the FS453. Traces connected from point to point should overlay
the ground plane. If you use an external clock source, make sure it meets CMOS level specifications in
addition to the frequency tolerance specifications.
9.4.2 FS453 Pixel Clock
In addition to the 27 MHz reference clock, the FS453 relies on a variable pixel clock to control the timing
of the digital video signal from the graphics controller (Pseudo-master mode only). This pixel clock is
generated by the FS453, sent to the graphics controller, and then returned to the FS453 along with the
JANUARY, 2005, VERSION 3.0
34
COPYRIGHT
©
2003-4 FOCUS ENHANCEMENTS, INC.
FOCUS Enhancements Semiconductor
