Fluke 9000A-006, Service Manual, Page: 23 / 64

2-9
9000A-006 Service
Assuming no STOP edge has yet been received, and assuming the enable level is in the
enabled state, the enable gate (U49) provides a GATE-ON signal to the clock gate (U24
and U23) (and to the events and waveform sections).
At the time of the first CLOCK pulse after the START signal edge, the clock gate
produces its first gated CLOCK pulse to the CRC and events sections. The CLOCK pulse
is a result of the edged CLOCK signal applied to the clock gate. The clock gate remains
enabled until the selected STOP signal occurs and the stop flip-flop (U48B) changes state
to inhibit the enable gate (U49). The enable gate inhibits the clock gate and halts the
generation of gated CLOCK pulses. The output of the stop flip-flop is also fed to the
control section as a status line back to the Troubleshooter.
Once the STOP edge has been received and the stop flip-flop is set, the control section
must produce a CLEAR-GATE signal. The CLEAR-GATE signal is required for the next
START edge to set the start flip-flop and begin a new gate time.
FIGURE 2-3. Gate Section, Block Diagram