3 - 8
VC15 Mainboard Manual
Memory Hole At 15M-16M
When set at Enabled, the memory hole at 15MB address will be relocated
to the 15M-16MB address range of the ISA or PCI cycle when the CPU
accesses the 15M-16MB address area. When set at Disabled, the memory
hole at 15MB address will be treated as a DRAM cycle when the CPU
accesses the 15M-16MB address area. The options are: Disabled, Enabled.
DRAM Data Integrity Mode
The feature allows you to set the DRAM data integrity mode.
The options are: Non-ECC, ECC.
Memory Frequency For
This feature allows users to set the memory frequency.
Dram Read Thermal Mgmt
The feature allows users to set the DRAM Read Thermal Management
register which in the Intel core chip for the trade-off between system tem-
perature and its performance. The options are: Disabled, Enabled.
System BIOS Cacheable
Setting at Enabled will allow the caching of the BIOS ROM F0000H-FFFFFH,
resulting in better system performance. It may cause system error when
some programd try to access the memory area.
The options are: Disabled, Enabled.
Video BIOS Cacheable
Setting at Enabled will allow the caching of the video BIOS ROM at C0000H-
C7FFFH, resulting in better video performance. It may cause system error
when some programd try to access the memory area.
The options are: Disabled, Enabled.
Video RAM Cacheable
Setting at Enabled will allow the caching of the video RAM at A0000H-
BFFFFH, resulting in better video performance. It may cause system error
when some programd try to access the memory area.
The options are: Disabled, Enabled.