µ E Z
G U I U s e r ’ s M a n u a l
P a g e
|
23
9/13/2023
Copyright ©2023, Future Designs, Inc.
Revision 1.2
Pin
Pin Name
Pin Description
RXD1
–
UART Channel 1 Receive Data
I
9
GPIO6.12/TXD1
GPIO6.12
–
General Purpose I/O
I/O
TXD1
–
UART Channel 1 Transmit Data
O
10
Ground (GND)
Power
11
USB1_DM
USB_D- 1 - USB port 1 bidirectional D- line.
I/O
12
USB1_DP
USB_D+1 - USB port 1 bidirectional D+ line.
I/O
13
GPIO5.5/CTIN2/T3_MAT2/USB1_VBUS
GPIO5.5
–
General Purpose I/O
I/O
CTIN2
–
SCT input 2. Capture input 2 of timer 0
I
T3_MAT2
–
Match output 2 of timer 3
O
USB1_VBUS
–
USB Channel 1 VBus input
I
14
GPIO4.11/MCOB1/USB1H_OVC/RXD0
GPIO4.11
–
General Purpose I/O
I/O
MCOB1
–
Motor Control PWM Channel 1 output B
O
USB1H_OVC
–
USB Channel 1 Power Fault (same as USB1_PWR_FAULT)
I
RXD0
–
UART Channel 0 Receive Data
I
15
GPIO5.18/MCOA1/USB1H_PPWR/TXD0
GPIO5.18
–
General Purpose I/O
I/O
MCOA1
–
Motor Control PWM Channel 1 output A
O
USB1H_PPWM
–
USB Channel 1 Host VBus Drive Signal
O
TXD0
–
UART Channel 0 Transmit Data
O
16
GPIO4.14/MCOB2/I2STX_SDA/MOSI0
GPIO4.14
–
General Purpose I/O
I/O
MCOB2
–
Motor Control PWM Channel 2 output B
O
I2STX_SDA
–
I2S Audio Transmit Serial Data
I/O
MOSI
–
SPI Channel 0 Master Output, Slave Input Serial Data
I/O
17
GPIO4.13/MCOA2/I2STX_WS/MISO0
GPIO4.13
–
General Purpose I/O
I/O
MCOA2
–
Motor Control PWM Channel 0 output A
O
I2STX_WS
–
I2S Audio Transmit Word Select
I/O
MISO0
–
SPI Channel 0 Master Input, Slave Output Serial Data
I/O
18
I2STX_SCK/SSP0SCK
Connected to pin F13 of LPC4357 BGA (P3_0)
I/O
I2STX_SCK
–
I2S Audio Transmit Clock
I/O
SSP0SCK
–
SPI Channel 0 Serial Clock
I/O
19
GPIO5.9/I2SRX_SDA/CAN0TD
GPIO5.9
–
General Purpose I/O
I/O
I2SRX_SDA
–
I2S Audio Receive Serial Data
I/O
CAN0TD
–
CAN Channel 0 Transmit Data
O
20
GPIO5.8/I2SRX_WS/CAN0RD
GPIO5.8
–
General Purpose I/O
I/O
I2SRX_WS
–
I2S Audio Receive Word Select
I
CAN0RD
–
CAN Port 0 Receive Data
I
21
I2SRX_SCK
Connected to pin M12 of LPC4357 BGA (P6_0)
I2SRX_SCK
–
I2S Audio Receive Clock
I
22
Ground (GND)
Power
23
RESET_INn
External reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to
take on their default states, and processor execution to begin at address 0.
TTL with hysteresis, 5 V tolerant
I
24
RESET_OUTn
RSTOUT - This is a 3.3 V pin. LOW on this pin indicates LPC4357 being in Reset state
O
25
GPIO2.4/DAC/CTOUT2
GPIO2.4
–
General Purpose I/O
I/O
DAC
–
DAC Output
O
CTOUT2
–
SCT Output 2, Match output 2 of timer 0
O
26
GPIO2.1/ADC0.1/CTOUT1
GPIO2.1
–
General Purpose I/O
I/O
ADC0.1
–
ADC0 & ADC1, input channel 1
I
CTOUT1
–
SCT Output 1, Match output 3 of timer 3
O
27
GPIO0.12/ENET_MDIO/U2_UCLK/
T0_CAP3/CAN1_TD
GPIO0.12
–
General Purpose I/O
I/O
ENET_MDIO
–
Ethernet MIIM data input and output
I/O
U2_UCLK
–
UART Channel 2 Serial Clock input/output
I/O
T0_CAP3
–
Capture input 3 of timer 0
I