52
6F8 - 6FF
Register shadow memory for read back of
otherwise write-only bits.
700 - 7FF
I2C shared area.
P
ICO
B
LAZE
R
EGISTER
M
AP
All of the following registers can only be accessed when the register access enable signal
is set. This is accomplished by making any access to locations 00 through 0xf6. Any
access to location 0xf7 clears the register access enable signal. Accesses within the 0xf8
through 0xff register area do not affect the state of the register access enable signal.
0
X
F8
B
AUD
R
ATE
P
ERIOD
,
LOW
8
BITS AND
F
RAME
C
OUNT
.
0
X
F9
B
AUD
R
ATE
P
ERIOD
,
HIGH
8
BITS AND
F
GET
8
DATA
.
The Baud rate is derived by dividing the pixel clock frequency by the number entered here.
In the MV13, the pixel clock runs at 66.667 MHz and the default setting for 9600 baud
would be 6944. The last value written to the Baud Rate high 8-bits register can be read
back from scratchpad location 0x2f9 when register access is disabled. When register
access is enabled, reading 0xF9 returns the byte of flash data from the "Fget8" sequencer.
Reading 0xF8 returns the frame count in four successive reads. Frame count is latched
whenever address 0x00 is read.
0
X
FA S
ENSOR
C
ONTROL
.
The Bits are:
Bit
7
Read-only "Y" pending. Indicates that a CC2 event has occurred and the
PicoBlaze should forward it to the Data FPGA as a "Y" command.
Bit
6
Read-only "Z" pending. Indicates that a CC3 event has occurred and the
PicoBlaze should forward it to the Data FPGA as a "Z" command.
Bit
5
Reserved.
Bit Serial trigger. Must be toggled in software to trigger the sensor control logic in
