35
Comparators in the Control FPGA check for changes in the DAC settings and re-load the
DAC's whenever the values are changed. This can happen as a result of the host
command to set camera state, or the host command to restore state from flash.
C
ALIBRATION
Both the MV13 and MV40 sensors have automated ADC calibration to reduce column-wise
fixed-pattern noise. This is initiated at sensor reset or by using the CAL_START_N input.
The Control FPGA always uses the sensor reset to initiate calibration. In addition, the
MV40 sensor allows direct access to the internal calibration values on a serial interface
consisting of the DATA_CLK, DATA, RE_N, and WE_N pins. This version of the Control
FPGA does not use this interface.
Automatic calibration is initiated after power-up when the sensor is released from reset.
Reset is released before the Data FPGA is loaded to allow the sensor to stabilize during
the load process. Reset is re-asserted for two clock cycles at the end of the initialization
sequence, about TBD milliseconds after the reference voltage DAC's are updated from
flash. This causes the sensor to re-calibrate with the new reference voltage settings.
After power-on initialization, the sensor is only calibrated on demand by the host using the
Reset and Calibrate Sensor command. It is not automatically calibrated after changing the
reference voltages. Thus the camera control GUI is responsible for periodic calibration as
required.
P
OWER
-
ON
I
NITIALIZATION
The Control FPGA has a small embedded micro that runs through an initialization
sequence at power-on. This same micro also implements the host, USB, and Data FPGA
communication protocols and deals with flash memory and DAC's.
Immediately after power-on, the voltage reference DAC's are programmed with factory
default values. This allows the sensor to stabilize under conditions close to the actual
operating environment.
Page zero is read from the flash memory. This page holds information necessary to locate
actual power-on data in the flash.
The sensor is released from reset and allowed to self calibrate and stabilize.
The Data FPGA is loaded from flash. If the offset or length stored in the header is not
valid, the embedded micro skips to step 10. This may take several seconds depending on
the FPGA size.
